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The following document contains information on Cypress products.
AN04-00224-1E
Spread S pectrum Clock Generator
SSCG
Asynchronous data transfer with SSCG
AN04-00224-1E
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Copyright© 2009 FUJITSU MICRELECTRONICS LIMITED all rights reserved
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AN04-00224-1E
Revision History
Rev
Date
Remark
1.0
2009/5/18
First Edition
2
AN04-00224-1E
Subject
Revision History.................................................................................................................... 2
Subject.................................................................................................................................. 3
1
Introduction.................................................................................................................... 4
2
Idea of asynchronous transfer (asynchronization design) ............................................. 5
2.1
Example for adapting to asynchronous communication system ............................. 5
2.2
Example for the adapting to strict jitter system ....................................................... 6
Figure 2. shows the adapting to strict jitter system............................................................ 6
2.3
Method of designing asynchronization of SSCG .................................................... 7
3
AN04-00224-1E
1
Introduction
The document shows how to achieve the asynchronous data transfer with SSCG.
(SSCG : Spread Spectrum Clock Generator).
4
AN04-00224-1E
2
Idea of asynchronous transfer (asynchronization design)
There ar e some not using SS clo ck system directly . For example, USB
and CAN is
defined by severe jitter standard. So in the case of using SSCG in these system, SS clock
modulation rate is only sprea d in the range of defined st andard.
Also, it is
imaginable
that the jitter specific ation of the clock receiver device is severe, in the same case. But
according to the specifica tion of SSCG, small modulation rate setting can only small EMI
effect.
It is introduce how to think of the aysnchr onization design with FIFO and Line-buffer etc.
for using SSCG and getting the effective EMI decrease.
2.1
Example for adapting to asynchronous communication system
Figure 1. shows the example for adapting to asynchronous communication system.
In
the asynchronous communication, it is easily imagi nable to e xceed the permissible error o f
the data sending and receiving if the SS clock is used as it is. When The synchronization
circuit by FIFO is prep
ared o n the receiving device side as figure 1, th
e system ca n
communicate with SS clock.
Achievement of asynchron ous co mmunication with SSCG , It is necessary to use
number of columns for FIFO, it depends on th
communication baud rate etc.,
SS Off
the
e modulation rate of SS clock and the
is about 8 to 24 columns in the case of +/- 0.5 %.
Large EMI level
Sending Device
Receiving Device
Data
CLK1
SS On
CLK2
The modulation is removed with FIFO.
Sending Device
Small EMI level
Data
CLK1
SSCG
SSCLK
Receiving Device
FIFO
CLK2
Figure 1.Application example for adapting to asynchronous communication with SS clock
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AN04-00224-1E
2.2
Example for the adapting to strict jitter system
Figure 2. shows the adapting to strict jitter system.
The basis idea of the system configuration is same Figure 1.
When The synchronization circuit by FIFO is
prep ared o n th e receivin g device side as
figure 1, the system can communicate with SS clock. In the case that the system operation
becomes ab normal dir ectly using SS clock, it is necessary to use the FIFO circuit in the
clock receiver circuit. SS clock can use with the circuit in these system.
SS Off
Large EMI level
Transfer Device
Application of strict jitter standards
Receiver Device
Data
~♪
CLK
The modulation is removed with FIFO
SS On
Transfer Device
Data
Receiver Device
The part where the jitter
standard is severe is separated
FIFO
~♪
Small EMI level
SSCLK
SSCG
Figure 2. Example for the adapting to strict system
6
CLK
AN04-00224-1E
2.3
Method of designing asynchronization of SSCG
SSCG has PLL in it. So the input clock
to SSCG (source clock) and output clock
from
SSCG are a synchronizations. When the dat a transfe r with SS clo ck, it is necessary to
design the asynchronization system between input clock and output clock.
It is explained by 3 examples.
(1) Input frequency=Output frequency (x1-folks)
It can design the asynchronization system with center spread SSCG and FIFO etc.
(2) Input frequency>Output frequency (x1-folks, down-spread)
It can d esign the asynchro nization system with down sprea d SSCG and memory or
FIFO etc. that has enough capacity to save the transfer data.
(3) Input frequency<Output frequency
In the case that the minimum of SS clock frequency is higher than the input frequency, it
can design the asynchronization system with SSCG and FIFO etc..
(The above condition is:
input frequency < output frequency • (1 +/- modulation rate)
)
About each example of composition and timing chart shows figure 3., 4. and 5.
About the standard number of FIFO’s columns in the case of using SS clock, the table1.
is shown. Please refer it.
Input Data
Data
Transmitter
FIFO
n stage
Clk in
Output Data
Data
Receiver
Clk Out
Output Enable
Example of six stage
composition
SSCG
Full
FIFO n/2 stage
Empty
Read begins from part
where (n/2) data of
FIFO3 step collected
D0
D0
D1
D0
D1
D2
D1
D2
D3
D3
D4
D5
D6
D2
D2 D3
D3 D4
D4 D5
D4
D5
D6
D7
D4 D5
D5 D6 D7
D6 D7 D8
D7 D8 D9
D8 D9 D10
CLK-in
Input Data
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11
D3
D4 D5 D6 D7
Output Enable
CLK-out (SS-Clock)
Output Data
D0
D1
D2
Figure 3. example of composition and timing chart in the case of (1) situation
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Input Data
Data
Transmitter
Output Data
Data
Receiver
memory
Clk in
WE
RE
Clk Out
SSCG
CLK-in
D0
Input Data
D1
D2
D3
D4
D5
Write Enable(WE)
Read Enable(RE)
CLK-out (SS-Clock)
Output Data
D0
D1 D2D3D4
Figure 4. example of composition and timing chart in the case of (2) situation
Input Data
Data
Transmitter
FIFO
2stages
Clk in
Output Data
Data
Receiver
empty
Clk Out
SSCG (x2)
FIFO
Empty
D0
D3 D4
D2
D1
D5
D8
D7
D6
D9
D10
CLK-in
Input Data
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11
Empty(Data Valid)
CLK-out (SS-Clock)
Output Data
D0
D1
D2
D3 D4D5
D6
D7 D8 D9
Figure 5. example of composition and timing chart in the case of (3) situation
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D10
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Table 1. Standard number of FIFO’s columns in the case that using SS clock
Basic
spec.
Sub spec, Function settings
MB88151A
100
110
FREQ1,0=LH
FREQ1,0=HL
MB88154A
111
112
±1.0%
±1.5%
16.6~33.4MHz
8
20
FREQ=L
16.6~33.4MHz
10
22
FREQ=H
33.0~67.0MHz
14
36
FREQ=L
40.0~80.0MHz
16
42
67.0~134MHz
24
68
FREQ1,0=LL
16.6~40.0MHz
10
22
FREQ1,0=HL
33.0~67.0MHz
14
36
FREQ1,0=HH
40.0~80.0MHz
16
42
FREQ1,0=LH
67.0~134MHz
24
112
33.0~67.0MHz
14
24
36
113
16.6~40.0MHz
10
16
22
FREQ1,0=HH
MB88153A
FIFO number of columns in each
modulation depth
±0.5%
FREQ1,0=LL
MB88152A
Frequency
110
111
FREQ=H
±2.0%
68
110,112
12.5~25.0MHz
6
8
111,113
25.0~50.0MHz
8
12
MB88161
MLTP=L
20.0~28.0MHz
6
8
12
MB88162
MLTP=L
12.0~28.0MHz
6
8
12
MB88155
- END -
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