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The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–21358–5E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 2.5 GHz Prescaler
MB15E07SL
■ DESCRIPTION
The FUJITSU SEMICONDUCTOR MB15E07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/
65 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15E07SL uses the latest BiCMOS process,
as a result the supply current is typically 3.5 mA at 2.7 V. A refined charge pump supplies well-balanced
output currents of 1.5 mA and 6 mA. The charge pump current is selectable by serial data.
■ FEATURES
• High frequency operation: 2.5 GHz Max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 3.5 mA Typ (VCC = Vp = 2.7 V, Ta = +25°C, in locking state)
ICC = 4.0 mA Typ (VCC = Vp = 3.0 V, Ta = +25°C, in locking state)
• Direct power saving function: Power supply current in power saving mode
Typ 0.1 μA (VCC = Vp = 3.0 V, Ta = +25°C), Max 10 μA (VCC = Vp = 3.0 V)
• Dual modulus prescaler: 32/33 or 64/65
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
• Pin compatible with MB15E07, MB15E07L
Copyright©2003-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.9
MB15E07SL
■ PIN ASSIGNMENTS
16-pin SSOP
16-pin QFN
OSCOUT OSCIN R
OSCIN
1
16
R
OSCOUT
2
15
P
VP
3
14
LD/fout
VCC
VP
1
4 Top view 13
ZC
VCC
2
Do
3
GND
4
DO
5
12
PS
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
(FPT-16P-M05)
2
16
15
14
P
13
12 LD/fout
Top view
11 ZC
10 PS
9
5
Xfin
LE
8
6
7
fin Clock Data
(LCC-16P-M69)
DS04–21358–5E
MB15E07SL
■ PIN DESCRIPTIONS
Pin no.
SSOP QFN
Pin name
I/O
Descriptions
1
15
OSCIN
I
Programmable reference divider input. Connection to a TCXO.
2
16
OSCOUT
O
Oscillator output.
3
1
VP
–
Power supply voltage input for the charge pump.
4
2
VCC
–
Power supply voltage input.
5
3
DO
O
Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
6
4
GND
–
Ground.
7
5
Xfin
I
Prescaler complementary input, which should be grounded via a capacitor.
8
6
fin
I
Prescaler input.
Connection to an external VCO should be done via AC coupling.
9
7
Clock
I
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10
8
Data
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
11
9
LE
I
Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
I
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H”; Normal Do output.
ZC = “L”; Do becomes high impedance.
12
13
10
11
PS
ZC
14
12
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15
13
φP
O
Phase comparator N-channel open drain output for an external charge
pump. Phase can be selected via programming of the FC bit.
16
14
φR
O
Phase comparator CMOS output for an external charge pump. Phase can
be selected via programming of the FC bit.
DS04–21358–5E
3
MB15E07SL
■ BLOCK DIAGRAM
fr
(15)
OSCIN 1
Reference
oscillator
circuit
Phase
comparator
(14)
16 φR
(13)
15 φP
(16)
OSCOUT 2
Binary 14-bit
reference counter
SW FC LDS CS
14-bit latch
4-bit latch
(1)
VP 3
Lock
detector
fp
LD/fr/fp
selector
(12)
14 LD/fout
..
Charge pump
DO
(3)
5
Current switch
VCC
C
N
T
(2)
4
19-bit shift register
...
...
7-bit latch
11-bit latch
Binary 7-bit
swallow counter
Binary 11-bit
programmable
counter
(11)
13 ZC
Intermittent
mode control
(power save)
(10)
12 PS
(9)
11 LE
(4)
GND 6
1-bit
control
latch
(5)
Xfin 7
MD
Prescaler
32/33
64/65
(6)
fin 8
(8)
10 Data
(7)
9 Clock
: SSOP
(
4
) : QFN
DS04–21358–5E
MB15E07SL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
Condition
VCC
Rating
Unit
Min
Max
–
–0.5
4.0
V
VP
–
VCC
6.0
V
VI
–
–0.5
VCC + 0.5
V
VO
Except Do
GND
VCC
V
VO
Do
GND
VP
V
Tstg
–
–55
+125
°C
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Typ
Max
VCC
2.4
3.0
3.6
V
VP
VCC
–
5.5
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS04–21358–5E
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MB15E07SL
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
Power supply current*1
Power saving current
Operating frequency
“L” level input current
“H” level input current
“L” level input current
“H” level input current
“L” level input current
Typ
Max
Unit
fin = 2500 MHz,
VCC = VP = 2.7 V
(VCC = VP = 3.0 V)
–
3.5
(4.0)
–
mA
IPS
ZC = “H” or open
–
0.1*2
10
μA
fin
fIN
–
700
–
2500
MHz
OSCIN
–
3
–
40
MHz
SSOP
–15
–
+2
QFN
–12
–
+2
Pfin
OSCIN*3
“H” level input current
Min
ICC*1
Input sensitivity
“L” level input voltage
Value
OSCIN
fin*3
“H” level input voltage
Condition
Data,
Clock,
LE, PS,
ZC
50 Ω system
(Refer to the
measurement
circuit.)
dBm
VOSC
–
0.5
–
VCC
VIH
–
VCC × 0.7
–
–
VIL
–
–
–
VCC × 0.3
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
IIH
–
0
–
+100
IIL*
4
–
–100
–
0
IIH*4
–
–1.0
–
+1.0
–100
–
0
Vp-p
V
Data,
Clock,
LE, PS
OSCIN
ZC
I *
Pull up input
IL 4
φP
μA
μA
VOL
Open drain output
–
0.4
φR,
“L” level output voltage LD/fout
VOH
VCC = VP = 3.0 V, IOH = –1 mA VCC – 0.4
–
–
VOL
VCC = VP = 3.0 V, IOL = 1 mA
–
–
0.4
“H” level output voltage
VDOH
VCC = VP = 3.0 V,
IDOH = –0.5 mA
VP – 0.4
–
–
VDOL
VCC = VP = 3.0 V,
IDOL = 0.5 mA
–
–
0.4
–
–
2.5
nA
1.0
–
–
mA
“L” level output voltage
“H” level output voltage
Do
“L” level output voltage
High impedance cutoff
current
Do
IOFF
VCC = VP = 3.0 V,
VOFF = 0.5 V to VP – 0.5 V
“L” level output current
φP
IOL
Open drain output
φR,
LD/fout
“L” level output current
“H” level output current
V
V
V
IOH
–
–
–
–1.0
IOL
–
1.0
–
–
CS bit = “H”
–
–6.0
–
CS bit = “L”
–
–1.5
–
CS bit = “H”
–
6.0
–
CS bit = “L”
–
1.5
–
mA
IDOL
VCC = 3 V,
VP = 3 V,
VDO = VP/2
Ta = +25°C
IDOL/IDOH
IDOMT*5
VDO = VP/2
–
3
–
%
vs VDO
DOVD 6
0.5 V ≤ VDO ≤ VP – 0.5 V
–
10
–
%
DOTA 7
– 40°C ≤ Ta ≤ +85°C
–
10
–
%
“H” level output current
IDOH*4
Do
“L” level output current
Charge pump current
rate
–
μA
vs Ta
I
*
I
*
mA
(Continued)
6
DS04–21358–5E
MB15E07SL
(Continued)
*1 : Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.
*2 : VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode
*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = VP = 3.0 V, Ta = +25°C (|I3| – |I4|) / [(|I3| + |I4|) /2] × 100(%)
*6 : VCC = VP = 3.0 V, Ta = +25°C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)
*7 : VCC = VP = 3.0 V, VDO = VP/2 (|IDO(85°C) – IDO(–40°C)| /2) / (|IDO(85°C) + IDO(–40°C)| /2) × 100(%) (Applied to each IDOL, IDOH)
I1
I3
I2
IDOL
IDOH
I4
I2
I1
0.5
Vp/2
Vp − 0.5 V Vp
Charge Pump Output Voltage (V)
DS04–21358–5E
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MB15E07SL
■ FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M : Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is
taken high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT)
Destination of serial data
H
For the programmable reference divider
L
For the programmable divider
(1) Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
SW
FC LDS CS
CNT
R1 to R14
SW
FC
LDS
CS
: Control bit
: Divide ratio setting bit for the programmable reference counter (3 to 16,383)
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/fOUT signal select bit
: Charge pump current select bit
18
19
[Table 1]
[Table 2]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
Note: Start data input with MSB first.
(Continued)
8
DS04–21358–5E
MB15E07SL
(Continued)
Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT
: Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
[Table 1]
[Table 3]
[Table 4]
Note: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio
(R)
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N)
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A)
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
DS04–21358–5E
9
MB15E07SL
Table 5. Prescaler Data Setting
SW
Prescaler divide ratio
H
32/33
L
64/65
Table 6. Charge Pump Current Setting
CS
Current value
H
±6.0 mA
L
±1.5 mA
Table 7. LD/fout Output Select Data Setting
LD/fOUT output signal
LDS
H
fout signal
L
LD signal
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor
pin (fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP
is shown below.
Table 8. FC Bit Data Setting (LDS = “H”)
FC = High
FC = Low
DO
φR
φP
fr > fP
H
L
L
fr < fP
L
H
Z*
fr = fP
Z*
L
Z*
LD/fout
fout = fr
DO
φR
φP
L
H
Z*
H
L
L
Z*
L
Z*
LD/fout
fout = fp
* : High-Z
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
* : When the LPF and VCO characteristics are similar
to (1), set FC bit high.
(1)
* : When the VCO characteristics are similar to (2), set
FC bit low.
PLL
LPF
VCO
VCO
Output
Frequency
(2)
LPF Output Voltage
10
DS04–21358–5E
MB15E07SL
3. Do Output Control
Table 9. ZC Pin Setting
ZC pin
Do output
H
Normal output
L
High impedance
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal
operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference
frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump
and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 μs.
Note : PS pin must be set “L” for Power-ON.
OFF
ON
tV ≥ 1 μs
VCC
Clock
Data
LE
tPS ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 μs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: L → H) 100 ns later after setting serial data.
DS04–21358–5E
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MB15E07SL
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
Invalid data
∼
Data
MSB
LSB
∼
∼
Clock
t2
t1
t3
t6
t7
LE
∼
t4
t5
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
Min
Typ
Max
Unit
Parameter
Min
Typ
Max
Unit
t1
20
–
–
ns
t5
100
–
–
ns
t2
20
–
–
ns
t6
20
–
–
ns
t3
30
–
–
ns
t7
100
–
–
ns
t4
30
–
–
ns
Note : LE should be “L” when the data is transferred into the shift register.
12
DS04–21358–5E
MB15E07SL
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
t WU
t WL
LD
[FC = “H”]
DO
[FC = “L”]
DO
Notes : • Phase error detection range: –2π to +2π
• Pulses on Do signal during locked state are output to prevent dead zone.
• LD output becomes low when phase is tWU or more. LD output becomes high when phase error
is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz)
tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz)
• LD becomes high during the power saving mode (PS = “L”).
DS04–21358–5E
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MB15E07SL
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF
0.1 μF
1000 pF
0.1 μF
1000 pF
S•G
S•G
50 Ω
fin
Xfin GND
DO
VCC
VP OSCOUT OSCIN
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
Clock Data LE
PS
ZC LD/fout φP
φR
VCC
50 Ω
Oscilloscope
Controller (setting divide ratio)
Note: SSOP-16
14
DS04–21358–5E
MB15E07SL
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
Input sensitivity Pfin (dBm)
Input sensitivity − Input frequency (Prescaler: 64/65)
Ta = +25 °C
10
0
SPEC
−10
−20
−30
VCC = 2.4 V
VCC = 3.0 V
−40
VCC = 3.6 V
−50
0
200
400
600
800
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000
Input frequency fin (MHz)
Input sensitivity − Input frequency (Prescaler: 32/33)
Ta = +25 °C
10
Input sensitivity Pfin (dBm)
0
SPEC
−10
−20
−30
VCC = 2.7 V
VCC = 3.0 V
−40
VCC = 3.6 V
−50
0
200
400
600
800
1000
1200
1400
1600
1800 2000
2200
2400
2600
2800 3000
Input frequency fin (MHz)
DS04–21358–5E
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MB15E07SL
2. OSCIN input sensitivity
Input sensitivity − Input frequency
Ta = +25 °C
10
Input sensitivity VOSC (dBm)
SPEC
0
−10
−20
−30
−40
VCC = 2.4 V
VCC = 3.0 V
−50
VCC = 3.6 V
−60
0
16
50
100
Input frequency fOSC (MHz)
150
200
DS04–21358–5E
MB15E07SL
3. Do output current
1.5 mA mode
VDO - IDO
Ta = +25°C
VCC = 3.0 V
Vp = 3.0 V
Charge pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
IDOH
–10.00
0
4.800
.6000/div
Charge pump output voltage VDO (V)
6.0 mA mode
VDO - IDO
Ta = +25°C
VCC = 3.0 V
Vp = 3.0 V
Charge pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
–10.00
0
4.800
.6000/div
Charge pump output voltage VDO (V)
DS04–21358–5E
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MB15E07SL
4. fin input impedance
1 : 12.646 Ω
–57.156 Ω
1 GHz
2 : 22.156 Ω
–12.136 Ω
1.5 GHz
4
3 : 33.805 Ω
11.869 Ω
2 GHz
4 : 23.715 Ω
8.9629 Ω
2.5 GHz
3
2
1
START
500.000 000 MHz
STOP 2 500.000 000 MHz
5. OSCIN input impedance
1:
9.917 Ω
–3.643 Ω
3 MHz
2 : 3.7903 Ω
–4.812 Ω
10 MHz
3:
4
1.574 Ω
–3.4046 Ω
20 MHz
3
12 4 : 453.12 Ω
–1.9213 Ω
40 MHz
START
18
1.000 000 MHz
STOP
50.000 000 MHz
DS04–21358–5E
MB15E07SL
■ REFERENCE INFORMATION
Test Circuit
S.G
fVCO = 810.45 MHz
KV = 17 MHz/V
fr = 25 kHz
fOSC = 14.4 MHz
LPF
OSCIN
fin
LPF
Do
9.1 kΩ
4.2 kΩ
4700 pF
Spectrum
Analyzer
VCC =VP = 3.0 V
VVCO = 2.3 V
Ta = +25 °C
CP : 6 mA mode
VCO
1500 pF
0.047 μF
PLL Reference Leakage
REF –5.0 dBm
10 dB/
ATT 10 dB
MKR
25.0 kHz
–78.0 dB
RBW
1 kHz
SAMPLE
VBW
1 kHz
SWP 1.0 s
SPAN 200 kHz
CENTER 810.000 MHz
PLL Phase Noise
REF –5.0 dBm
10 dB/
ATT 10 dB
MKR
2.28 kHz
–53.1 dB
RBW
100 Hz
SAMPLE
VBW
100 Hz
SWP 10 s
SPAN 20.0 kHz
CENTER 810.000 MHz
(Continued)
DS04–21358–5E
19
MB15E07SL
(Continued)
PLL Lock Up time
810 MH→826 MHz within ± 1 kHz
Lch→Hch
1.30 ms
PLL Lock Up time
826 MH→810 MHz within ± 1 kHz
Hch→Lch
1.28 ms
846.000 MHz
838.000 MHz
826.000 MHz
818.000 MHz
806.000 MHz
798.000 MHz
500.0 μs/div
826.004000 MHz
810.004000MHz
826.000000 MHz
810.000000MHz
825.996000 MHz
809.996000MHz
500.0 μs/div
20
500.0 μs/div
500.0 μs/div
DS04–21358–5E
MB15E07SL
■ APPLICATION EXAMPLE
VP
10 kΩ
OUTPUT
VCO
LPF
12 kΩ
12 kΩ
10 kΩ
Lock Det.
From
a controller
φR
φP
LD/fout
ZC
PS
LE
Data
Clock
16
15
14
13
12
11
10
9
MB15E07SL
1
2
3
4
5
6
7
8
OSCIN
OSCOUT
VP
VCC
DO
GND
Xfin
fin
1000 pF
1000 pF
1000 pF
0.1 μF
0.1 μF
TCXO
VP: 5.5 V Max
Notes : • SSOP-16
• In case of using a crystal resonator, it is necessary to optimize matching between the crystal
and this LSI, and perform detailed system evaluation. It is recommended to consult with a
supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback
resistor is 100 kΩ (Typ).)
DS04–21358–5E
21
MB15E07SL
■ USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting device into or removing device from a socket.
-Protect leads with a conductive sheet when transporting a board-mounted device.
22
DS04–21358–5E
MB15E07SL
■ ORDERING INFORMATION
Part number
Package
MB15E07SLPFV1
16-pin, Plastic SSOP
(FPT-16P-M05)
MB15E07SLWQN
16-pin plastic QFN
(LCC-16P-M69)
DS04–21358–5E
Remarks
23
MB15E07SL
■ PACKAGE DIMENSIONS
16-pin plastic SSOP
(FPT-16P-M05)
16-pin plastic SSOP
(FPT-16P-M05)
Lead pitch
0.65 mm
Package width ×
package length
4.40 × 5.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.45mm MAX
Weight
0.07g
Code
(Reference)
P-SSOP16-4.4×5.0-0.65
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
*1 5.00±0.10(.197±.004)
0.17±0.03
(.007±.001)
9
16
*2 4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
+0.20
1.25 –0.10
+.008
.049 –.004
LEAD No.
1
8
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.10(.004)
C
(Mounting height)
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8
0.13(.005)
M
0~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(Stand off)
(.004±.004)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
24
DS04–21358–5E
MB15E07SL
(Continued)
16-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
4.00 mm × 4.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.04 g
(LCC-16P-M69)
16-pin plastic QFN
(LCC-16P-M69)
2.60±0.10
(.102±.004)
4.00±0.10
(.157±.004)
4.00±0.10
(.157±.004)
INDEX AREA
0.25±0.05
(.010±.002)
2.60±0.10
(.102±.004)
0.40±0.05
(.016±.002)
0.50(.020)
TYP
0.02
(.001
C
+0.03
–0.02
+.001
–.001
1PIN CORNER
(C0.35 (C.014))
0.75±0.05
(.030±.002)
(0.20(.008))
)
2010 FUJITSU SEMICONDUCTOR LIMITED HMbC16-69Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS04–21358–5E
25
MB15E07SL
MEMO
26
DS04–21358–5E
MB15E07SL
MEMO
DS04–21358–5E
27
MB15E07SL
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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