A4910 Automotive 3-Phase MOSFET Driver Features and Benefits Description •High-current 3-phase gate drive for N-channel MOSFETs •3-phase current sense amplifiers •SPI-compatible serial or direct parallel control •Cross-conduction protection •Programmable dead time •Top-off charge pump for 100% PWM •Uncommitted buffer amplifier •5.5 to 50 V supply voltage range •CMOS inputs, 3.3 to 5 V logic supply •Extensive diagnostics output •Low-current sleep mode The A4910 is a three-phase controller for use with N-channel external power MOSFETs and is specifically designed for automotive applications. PACKAGE: 48-pin LQFP with exposed thermal pad (suffix JP) A unique charge-pump regulator provides full (>10 V) gate drive for battery voltages down to 7 V, and allows the A4910 to operate with a reduced gate drive down to 5.5 V. A bootstrap capacitor is used to provide the above battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows DC (100% duty cycle) operation. Full control over all six power MOSFETs in the 3-phase bridge is provided, allowing motors to be driven with block commutation or sinusoidal excitation. The power MOSFETs are protected from shoot-through by integrated crossover control and programmable dead time. Continued on the next page… Applications •Electronic power steering (EPS, EHPS, EAS) •Hydraulic pumps •Engine cooling fan •Gearbox actuator Not to scale Typical Application Drawing VBAT VBAT Regulator Control DSP or Microcontroller A4910 Diagnostics Current Sense A4910-DS, Rev. 2 3-Phase BLDC Motor A4910 Automotive 3-Phase MOSFET Driver Description (continued) Current in each half bridge can be measured using integrated current sense amplifiers. These are three user-configurable differential amplifiers, with below-ground common-mode range and excellent transient response and settling time, allowing them to be used in low-side current-sense applications. Integrated diagnostics provide indication of undervoltage, overtemperature, and power bridge faults, and can be configured to protect the power MOSFETs under most short-circuit conditions. Detailed diagnostics are available as a serial data word. The A4910 is supplied in a small footprint (81 mm2) 48-pin LQFP with exposed thermal pad (suffix JP). It is lead (Pb) free, with 100% matte-tin leadframe plating. SELECTION GUIDE Part Number A4910KJPTR-T Package Packing* 1500 pieces per 13-in. reel 7 mm × 7 mm, 1.6 mm nominal height LQFP with exposed thermal pad *Contact Allegro™ for additional packing options. ABSOLUTE MAXIMUM RATINGS with respect to AGND, PGND connected directly to AGND Characteristic Load Supply Voltage Symbol Notes VBB Rating Unit –0.3 to 50 V Logic Supply Voltage VDD –0.3 to 6 V Terminal VREG VREG –0.3 to 16 V Terminal CP1 VCP1 –0.3 to 16 V VCP2 VCP1 – 0.3 to VREG + 0.3 V –0.3 to 6 V –0.3 to VDD + 0.3 V Terminal CP2 Logic Inputs STRn, SDI, SCK, RESETn, COASTn, xHI, and xLO terminals Logic Outputs SDO, and DIAG terminals Sense Amplifier Inputs CSAP, CSAM, CSBP, CSBM, CSCP, and CSCM terminals Sense Amplifier Outputs CSAO, CSBO, and CSCO terminals Operational Amplifier Inputs OPAP and OPAM terminals Operational Amplifier Outputs OPAO terminals Terminal VBRG –4 to 6.5 V –0.3 to VDD + 0.3 V –0.3 to 6.5 V –0.3 to VDD + 0.3 V VBRG –5 to 55 V Terminals CA, CB, and CC 1 VCx –0.3 to VREG + 50 V Terminals GHA, GHB, and GHC 2 VGHx VCx – 16 to VCx + 0.3 V Terminals SA, SB, and SC 2 VSx VCx – 16 to VCx + 0.3 V Terminals GLA, GLB, and GLC VGLx VREG – 16 to 18 V Terminals LSSA, LSSB, and LSSC VLSSx VREG – 16 to 18 V –40 to 150 °C Continuous 150 °C Overtemperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours, determined by design characterization 175 °C –55 to 150 °C Ambient Operating Temperature Range Maximum Junction Temperature Storage Temperature Range TA TJ(max) Tstg Limited by power dissipation 1 For example, at VREG = 13 V the most positive rating is 13 V + 50 V = 63 V, while at VREG = 8 V the most positive rating is 8 V + 50 V = 58 V. 2 For example, at V REG = 13 V the most negative rating is VCx – 16 V = –0.3 V – 16 V = –16.3 V, and the most positive rating is VCx + 0.3 V = VREG + 50 V + 0.3 V = 13 V + 50 V + 0.3 V = 63.3 V. If VREG = 8 V, the most negative rating remains at –16.3 V, and the most positive rating is 58.3 V. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4910 Automotive 3-Phase MOSFET Driver Table of Contents Specifications 1 1 1 1 1 2 2 3 4 5 6 6 6 7 7 8 9 10 11 12 12 12 12 13 14 Features and Benefits Description Applications Typical Application Drawing Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Functional Block Diagram Electrical Characteristics Supply and Reference Gate Output Drive Logic Inputs and Outputs Logic Inputs and Outputs, Dynamic Current Sense Amplifiers Uncommitted Operational Amplifier Protection Characteristic Definitions Timing Diagrams Serial Interface Timing Gate Drive Timing, Phase Gate Drive Timing, COASTn Propagation Delay Timing Logic Truth Tables Characteristic Performance 15 Functional Description 16 16 17 17 19 20 20 Input and Output Terminal Functions Power Supplies Gate Drives Logic Control Inputs Current Sense Amplifiers Uncommitted Operational Amplifier 20 20 20 21 23 23 23 Diagnostics DIAG Output System Faults MOSFET Faults Fault Actions Fault States Fault Masking Serial Interface 24 25 25 27 27 27 28 28 29 Application Information 30 30 30 30 30 31 31 31 31 31 32 33 34 35 Configuration and Control Registers Diagnostic Register Serial Register Definition Configuration Register 0 (Config0) Configuration Register 1 (Config1) Diagnostic Register Mask Register Run Register Dead Time Selection Fault Blanking Time Selection Bootstrap Capacitor Selection Bootstrap Charging Bootstrap Charge Management VREG Capacitor Selection Supply Decoupling Power Dissipation Braking Current Sense Amplifier Input/Output Structures Layout Recommendations Package Outline Drawing THERMAL CHARACTERISTICS: May require derating at maximum conditions; see Power Dissipation section Characteristic Symbol Package Thermal Resistance (Junction to Ambient) RθJA Package Thermal Resistance (Junction to Pad) RθJP Test Conditions* Value Unit On 4-layer PCB based on JEDEC standard 23 °C/W On 2-layer PCB with 3 in.2 of copper area each side 44 °C/W 2 °C/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4910 25 OPAM 26 OPAO 27 CSCP 28 CSCM 29 CSCO 30 CSBP 31 CSBM 32 CSBO 33 CSAP 34 CSAM 35 CSAO 36 LSSC Automotive 3-Phase MOSFET Driver GLC 37 24 OPAP GHC 38 23 CLO SC 39 22 CHI CC 40 21 BLO LSSB 41 20 BHI GLB 42 19 ALO PAD GHB 43 18 AHI SB 44 17 DIAG CB 45 16 SDO RESETn 12 COASTn 11 VDD 10 7 VBB 9 6 PGND AGND 5 CP1 8 4 CP2 VBRG 3 VREG 13 STRn 2 14 SCK GHA 48 1 15 SDI GLA 47 SA LSSA 46 CA Pinout Diagram Terminal List Table Name Number AGND 9 Function Analog ground Name Number GHC 38 Function High-side gate drive, phase C AHI 18 Control input high side, phase A GLA 47 Low-side gate drive, phase A ALO 19 Control input low side, phase A GLB 42 Low-side gate drive, phase B BHI 20 Control input high side, phase B GLC 37 Low-side gate drive, phase C BLO 21 Control input low side, phase B LSSA 46 Low-side source, phase A LSSB 41 Low-side source, phase B CA 2 Bootstrap capacitor, phase A CB 45 Bootstrap capacitor, phase B LSSC 36 Low-side source, phase C CC 40 Bootstrap capacitor, phase C OPAM 25 Operational amplifier input – CHI 22 Control input high side, phase C OPAO 26 Operational amplifier output CLO 23 Control input low side, phase C OPAP 24 Operational amplifier input + COASTn 11 Coast input PAD – Exposed thermal pad CP1 5 Pump capacitor PGND 6 Power ground CP2 4 Pump capacitor RESETn 12 Standby mode control CSAM 34 Current sense input –, phase A SA 1 Motor connection, phase A CSAO 35 Current sense output, phase A SB 44 Motor connection, phase B CSAP 33 Current sense input +, phase A SC 39 Motor connection, phase C Current sense input –, phase B SCK 14 Serial clock input CSBM 31 CSBO 32 Current sense output, phase B SDI 15 Serial data input CSBP 30 Current sense input +, phase B SDO 16 Serial data output CSCM 28 Current sense input –, phase C STRn 13 Serial strobe (chip select) input CSCO 29 Current sense output, phase C VBB 7 Main power supply CSCP 27 Current sense input +, phase C VBRG 8 High-side drain voltage sense DIAG 17 Programmable diagnostic output VDD 10 Logic supply VREG 3 Gate drive supply output GHA 48 High-side gate drive, phase A GHB 43 High-side gate drive, phase B Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4910 Automotive 3-Phase MOSFET Driver Functional Block Diagram Battery + VDD DIAG Diagnostics and Protection STRn SCK SDI SDO Serial Interface CP2 CP1 CP CREG VBRG Phase A Charge Pump CA COASTn CBOOTA High Side Drive AHI Bootstrap Monitor ALO BHI VBAT VBB VREG Charge Pump Regulator VDS Monitor Control Logic VREG BLO CHI Low Side Drive Phase A shown; repeated for phases B and C GHA RGATE SA VDS Monitor Phase C Phase B GLA RGATE CLO RESETn LSSA CSAP OPAP CSAM OPAM CSAO OPAO AGND PGND Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4910 Automotive 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VDD = 5 V, VBB = 5.5 to 50 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VBB Functional Operating Range VBB Quiescent Current VDD Logic Supply VDD Quiescent Current VREG Output Voltage Bootstrap Diode Forward Voltage Bootstrap Diode Resistance VBB IBBQ RESETn = high, outputs low, VBB = 12 V IBBS RESETn = low, sleep mode, VBB = 12 V VDD 5.5 – 50 V – 10 14 mA – – 10 µA 3.0 – 5.5 V IDDQ RESETn = high, outputs low – 10 13 mA IDDS RESETn = low, sleep mode – – 10 µA VBB > 9 V, IREG = 0 to 30 mA 9 13 13.8 V 7.5 V < VBB ≤ 9 V, IREG = 0 to 20 mA 9 13 13.8 V 6 V < VBB ≤ 7.5 V, IREG = 0 to 15 mA 7.9 – – V VREG Vf BOOT rD 5.5 V < VBB ≤ 6 V, IREG < 9 mA 7.9 9.5 – V ID = 10 mA 0.4 0.7 1.0 V ID = 100 mA 1.5 2.2 2.8 V 6 11 22 Ω rD(100 mA) = (Vf BOOT(150 mA) – Vf BOOT(50mA)) / 100 mA Bootstrap Diode Current Limit IDBOOT 250 500 750 mA Top-Off Charge Pump Current Limit ITOCPM – 100 – µA High-Side Gate Drive Static Load Resistance RGSH 250 – – kΩ System Clock Period tOSC 45 50 55 ns GATE OUTPUT DRIVE Turn-On Time tr CLOAD = 10 nF, 20% to 80% points – 190 – ns Turn-Off Time tf CLOAD = 10 nF, 80% to 20% points – 120 – ns TJ = 25°C, IGHx = –150 mA 5 8 11 Ω TJ = 150°C, IGHx = –150 mA 10 15 20 Ω TJ = 25°C, IGLx = 150 mA 1.7 2.5 3.1 Ω TJ = 150°C, IGLx = 150 mA 2.9 4 5 Ω VCx – 0.2 – – V – – VSx + 0.3 V VREG – 0.2 – – V Pull-Up On-Resistance RDS(on)UP Pull-Down On-Resistance RDS(on)DN GHx Output Voltage (High) VGHH Bootstrap capacitor fully charged –10 µA < IGHx < 10 µA GHx Output Voltage (Low) VGHL GLx Output Voltage (High) VGLH GLx Output Voltage (Low) VGLL GHx Passive Pull-Down GLx Passive Pull-Down RGHPD RGLPD –10 µA < IGLx < 10 µA – – VLSSx + 0.3 V VBB = 0 V, VGHx – VSx < 0.1 V – 950 – kΩ VBB = 0 V, IGHx = 500 µA – 4 – kΩ VBB = 0 V, VGLx – VLSSx < 0.1 V – 950 – kΩ VBB = 0 V, IGLx = 500 µA – 4 – kΩ Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4910 Automotive 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VDD = 5 V, VBB = 5.5 to 50 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit GATE OUTPUT DRIVE (continued) Turn-Off Propagation Delay tP(off) Input change to unloaded gate output change (see figure 5) 60 90 140 ns Turn-On Propagation Delay tP(on) Input change to unloaded gate output change (see figure 5) 50 80 130 ns Propagation Delay Matching (Phase-to-Phase) ∆tPP Same phase change, DT[6..0] = 0 – 5 15 ns Propagation Delay Matching (On-to-Off) ∆tOO Single phase, DT[6..0] = 0 – 15 30 ns Propagation Delay Matching (GHx-to-GLx) ∆tHL Rising to rising edges, falling to falling edges, DT[6..0] = 0 – – 20 ns RESETn pin – – 0.2 × VDD V LOGIC INPUTS AND OUTPUTS Input Low Voltage VIL Input High Voltage VIH All other logic pins – – 0.3 × VDD V 0.7 × VDD – – V RESETn pin 200 350 – mV All other logic pins 250 500 – mV Input Hysteresis VIhys Input Pull-Up Resistor RPU STRn 30 50 70 kΩ Input Pull-Down Resistor RPD COASTn, RESETn, SCK, SDI, AHI, ALO, BHI, BLO, CHI, and CLO pins 30 50 70 kΩ Output Low Voltage VOL IOL= 1 mA – 0.2 0.4 V VOH IOL = –1 mA VDD – 0.4 VDD – 0.2 – V –1 – 1 µA Output High Voltage 1 Output Leakage (SDO pin) 1 ISDOlkg 0 V < VSDO < VDD , STRn = 1 LOGIC INPUTS AND OUTPUTS DYNAMIC PARAMETERS Reset Pulse Width tRST 0.2 – 4.5 µs Reset Shutdown Time tRSD 10 – – µs Clock High Time tSCKH A in Figure 2 50 – – ns Clock Low Time tSCKL B in Figure 2 50 – – ns Strobe Lead Time tSTLD C in Figure 2 30 – – ns Strobe Lag Time tSTLG D in Figure 2 30 – – ns Strobe High Time tSTRH E in Figure 2 300 – – ns Data Out Enable Time tSDOE F in Figure 2 – – 40 ns Data Out Disable Time tSDOD G in Figure 2 – – 30 ns Data Out Valid Time from Clock Falling tSDOV H in Figure 2 – – 40 ns Data Out Hold Time from Clock Falling tSDOH I in Figure 2 5 – – ns Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4910 Automotive 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VDD = 5 V, VBB = 5.5 to 50 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit LOGIC INPUTS AND OUTPUTS DYNAMIC PARAMETERS (continued) Data In Set-Up Time to Clock Rising tSDIS J in Figure 2 15 – – ns Data In Hold Time from Clock Rising tSDIH K in Figure 2 10 – – ns RESETn high to POR bit set – – 1 ms Wake Up from Reset tEN CURRENT SENSE AMPLIFIERS 2 (refer to Figure 1 for definitions) VIOS(SA) –10 – +10 mV Input Offset Voltage Drift 3 Input Offset Voltage ∆VIOS(SA) – ±10 – µV/°C Input Bias Current 1 IBIAS(SA) 0 V < VP < VDD, 0 V < VM < VDD –1 0 +1 µA Current 1 Input Offset IOS(SA) VID = 0 V, VCMin range –1 – +1 µA Input Common-Mode Range (DC) VCM(SA) VID = 0 V –1 – 2 V Differential Input Voltage VID(SA) – – 200 mV Open Loop Gain 3 AVOL(SA) VCM in range 80 100 – dB Closed Loop Gain AVCL(SA) VCM in range Small Signal –3 dB Bandwidth BW(SA) 5 – – V/V Gain = 20, VIND = 10 mVpp , RP = RM = 4 kΩ, CSB bit = 1 500 – – kHz Gain = 20, VIND =10 mVpp , RP = RM = 4 kΩ, CSB bit = 0 150 – – kHz – 1 1.8 µs 0.3 – VDD – 0.3 V VIND = 0 V, VOUT =1.5 V, RP = RM = 4 kΩ, Gain = 20 2 – – mA VIND = 200 mV, VOUT =1.5 V, RP = RM = 4 kΩ, Gain = 20, VOZ = 0 V – – –2 mA DC, VINP = VINM = 0 V, RP = RM = 4 kΩ, Gain = 20 80 – – dB f = 100 kHz, VINP = VINM = 0 V, RP = RM = 4 kΩ, Gain = 20 – 30 – dB DC, VINCM step from 0 V to 2.0 V, RP = RM = 4 kΩ, Gain = 20 60 80 – dB f = 100 kHz, VINCM = 200 mVPP , RP = RM = 4 kΩ, Gain = 20 – 62 – dB f = 1 MHz, VINCM = 200 mVPP , RP = RM = 4 kΩ, Gain = 20 – 43 – dB f = 10 MHz, VINCM = 200 mVPP , RP = RM = 4 kΩ, Gain = 20 – 33 – dB To within 100 mV of steady state, VINCM step from –4 V to +1 V, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF – 1 – µs Output Settling Time tSET(SA) To within 40 mV of steady state, VOUT = 1 Vpp square wave, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF Output Dynamic Range VOUT(SA) –100 µA < IOUT <100 µA Output Current Sink Output Current Source 1 VDD Supply Ripple Rejection Common-Mode Rejection Common-Mode Recovery Time Isink(SA) Isource(SA) PSRR(SA) CMRR(SA) tCMrec(SA) Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4910 Automotive 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VDD = 5 V, VBB = 5.5 to 50 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit CURRENT SENSE AMPLIFIERS 2 (continued) (refer to Figure 1 for definitions) Output Slew Rate (Peak) SR VIND step from 0 V to 175 mV, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF – 10 – V/µs Input Overload Recovery tIDrec(SA) To within 40 mV of steady state, VIND step from 250 mV to 0 V, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF – 1 – µs –10 – +10 mV – ±10 – µV/°C –1 0 +1 µA UNCOMMITTED OPERATIONAL AMPLIFIER 2 (refer to Figure 1 for definitions) Input Offset Voltage Input Offset Voltage VIOS(OA) Drift 3 Input Bias Current 1 Input Offset ∆VIOS(OA) IBIAS(OA) 0 V < VP < VDD , 0 V < VM < VDD Current 1 IOS(OA) VID = 0 V, VCM in range –1 – +1 µA Input Common-Mode Range (DC) VCM(OA) VID = 0 0.3 – VDD – 0.3 V mV Differential Input Voltage VID(OA) – – 200 Open Loop Gain 3 AVOL(OA) VCM in range 80 100 – dB Closed Loop Gain AVCL(OA) VCM in range 1 – – V/V Small Signal –3 dB Bandwidth BW(OA) VIND = 10 mVPP , RP = RM = 4 kΩ, Gain = 20 50 – – kHz Output Settling Time tSET(OA) To within 40 mV of steady state, VOUT = 1 VPP square wave, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF – 10 20 µs Output Dynamic Range VOUT(OA) –100 µA < IOUT < 100 µA 0.3 – VDD – 0.3 V VIND = 0 V, VOUT =1.5 V, RP = RM = 4 kΩ, Gain = 20 150 – – µA VIND = 200 mV, VOUT = 1.5 V, RP = RM = 4 kΩ, Gain = 20, VOZ = 0 V – – –2 mA Output Current Sink Isink(OA) Output Current Source 1 Isource(OA) VDD Supply Ripple Rejection PSRR(OA) Common-Mode Rejection CMRR(OA) DC, VP = 0.5 VDC, voltage follower – 40 – dB f = 100 kHz, VP = 0.5VDC, voltage follower – 40 – dB DC, VINCM step from 0 V to 2.0 V, RP = RM = 4 kΩ, Gain = 20 – 80 – dB f = 100 kHz, VINCM = 200 mVPP , RP = RM = 4 kΩ, Gain = 20 – 60 – dB f = 1 MHz, VINCM = 200 mVPP , RP = RM = 4 kΩ, Gain = 20 – 45 – dB f = 10 MHz, VINCM = 200 mVPP , RP = RM = 4 kΩ, Gain = 20 – 45 – dB Common-Mode Recovery Time tCMrec(OA) To within 100 mV of steady state, VINCM step from –4 V to +1 V, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF – 10 – µs Input Overload Recovery tIDrec(OA) To within 40 mV of steady state, VIND step from 250 mV to 0 V, RP = RM = 4 kΩ, Gain = 20, capacitive load = 200 pF – 10 – µs Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4910 Automotive 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VDD = 5 V, VBB = 5.5 to 50 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit PROTECTION VREG Undervoltage Lockout Bootstrap Undervoltage Bootstrap Undervoltage Hysteresis VDD Undervoltage Turn Off VDD Undervoltage Hysteresis VDS Threshold VREGON VREG rising 7.6 7.95 8.2 V VREGOFF VREG falling 6.9 7.18 7.4 V VBOOTUV Cx with respect to Sx 60 – 74 %VREG – 9 – %VREG 2.45 2.7 2.85 V 50 100 150 mV – 800 – mV 5.5 VBB 50 V – – 250 µA VBOOTUVhys VDDUV VDSTH VBRG Input Voltage VBRG Input Current Short-to-Ground Threshold Offset 4 Short-to-Battery Threshold Offset 5 VDD falling VDDUVhys Default power–up level VBRG IVBRG VDSTH = 2 V, VBB = 12 V, 0 V < VBRG < VBB IVBRGQ RESETn = low, sleep mode, VBB = 12 V – – 5 µA VDSTH ≥ 1 V, VBB > 7 V – ±100 – mV –150 ±50 +150 mV – ±100 – mV –150 ±50 +150 mV 2.8 3.2 3.6 µs VSTGO VSTBO Fault Blanking Time VDSTH < 1 V VDSTH ≥ 1 V, VBB > 7 V VDSTH < 1 V tBL Default power–up state DIAG Output Clock Division Ratio ND DIAG[1..0] = 01 – 409600 – – DIAG Output Temperature Offset 6 VTJD DIAG[1..0] = 11 – 1420 – mV DIAG Output Temperature Slope 6 ATJD DIAG[1..0] = 11 – –3.85 – mV/°C DIAG output VDS Threshold Error VDSE DIAG[1..0] = 10 –10 – 10 mV Hot Temperature Warning Threshold TJWH Temperature increasing 125 135 145 °C Hot Temperature Warning Hysteresis TJWHhys – 15 – °C TJF Temperature increasing 155 170 – °C TJhys Recovery = TJF – TJhys – 15 – °C Overtemperature Flag Overtemperature Hysteresis 1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal. 2V OZ = 0.5 V unless otherwise specified. 3 Confirmed by design and characterization. 4 With high-side on; as VSx decreases, fault occurs if VBAT – VSx > VSTG , given Short-to-Ground Threshold: VSTG = VDSTH + VSTGO . low-side on; as VSx increases, fault occurs if VSx – VLSSx >VSTB , given Short-to-Battery Threshold: VSTB = VDSTH + VSTBO . 6 T ≈ ( V J DIAG – VTJD ) / ATJD where TJ is junction temperature in °C, VDIAG is voltage measured on the DIAG pin in mV, VTJD is temperature offset in mV, and ATJD is temperature slope in mV/°C. 5 With Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4910 Automotive 3-Phase MOSFET Driver Characteristic Definitions VOZ VINCM = (VINP + VINM ) / 2 RG INP RP RS VCM = (VP + VM ) / 2 VIND VID RM VINP VOUT = VOZ + OUT – INM VINM VP RF (VINP – VINM ) RM Where: RP = RM and RG = RF + A4910 RF VOUT VM Figure 1: Operational amplifier voltage definitions Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4910 Automotive 3-Phase MOSFET Driver Timing Diagrams STRn C A B D E SCK J SDI X K D15 F SDO X D14 X X D0 I Z X G D15’ D14’ D0’ Z H X=don’t care, Z=high impedance (tri-state) Figure 2: Serial interface timing xHI xLO tDEAD tP(off) tP(on) tP(off) GHx GLx tP(off) tDEAD Synchronous Rectification High-side PWM tP(on) tP(off) Low-side PWM Figure 3: Gate drive timing, phase inputs COASTn COASTn tP(off) tP(on) tP(off) GHx GHx GLx GLx (A) xHI pin = high, xLO pin = low tP(on) (B) xHI pin = low, xLO pin = high Figure 4: Gate drive timing, COASTn input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4910 Automotive 3-Phase MOSFET Driver Timing Diagrams (continued) xHI, xLO 0.5VDD GHx, GLx 0.5VDD 0.25vout tP(on) vout 0.75vout tP(off) Figure 5: Propagation delay definition Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4910 Automotive 3-Phase MOSFET Driver Logic Truth Tables Table 1: Mapping of Phase Control Inputs to Internal Phase Control States Phase Control Inputs External Control Pins Run Register Control Bits Resultant Control States (Inputs for Table 2) xHI xH HIx 0 0 0 0 1 1 1 0 1 1 1 1 xLO xL LOx 0 0 0 0 1 1 1 0 1 1 1 1 Table 2: Mapping of Internal Phase Control States to Gate Drive Outputs Inputs Output Override Pin Control States (From Table 1) Gate Drive Outputs COASTn HIx LOx GHx GLx Sx Comment 1 0 0 Low Low Z Phase disabled 1 0 1 Low High Low Phase sinking 1 1 0 High Low High Phase sourcing 1 1 1 Low Low Z Phase disabled 0 X X Low Low Z Phase disabled X = don’t care, Z = high impedance All three motor drive phases are controlled independently. Control states (HIx, LOx) are derived by combining the logic states applied to the control input pins (xHI, xLO) with the bit patterns held in the Run register (xH, xL). Normally the input pins or the Run register method is used for control with the other being held inactive (all pins or bits at logic 0). Table 1 details how the two control mechanisms are combined and Table 2 shows the way in which the resultant control states map to the gate drive outputs. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4910 Automotive 3-Phase MOSFET Driver 0 50 -1 40 -2 30 IB (nA) VOS (mV) Characteristic Performance -3 -4 -5 20 10 -50 0 50 100 0 150 50 100 150 TA(°C) Figure 6: Current-Sense Amplifier Input Offset Voltage versus Temperature Figure 7: Current-Sense Amplifier Input Bias Current versus Temperature 8 -1 6 -2 IB (nA) VOS (mV) 0 TA(°C) 0 -3 4 2 -4 -5 -50 -50 0 50 100 150 0 -50 0 50 100 TA(°C) TA(°C) Figure 8: Uncommitted Operational Amplifier Input Offset Voltage versus Temperature Figure 9: Uncommitted Operational Amplifier Input Bias Current versus Temperature 150 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A4910 Automotive 3-Phase MOSFET Driver Functional Description The A4910 provides six high-current gate drives capable of driving a wide range of N-channel power MOSFETs. The gate drives are configured as three high-side drives and three low-side drives. Gate drives can be controlled individually with logic inputs or through the SPI-compatible serial interface. CMOS input thresholds are compatible with 3.3 or 5 V logic outputs. The serial interface also provides configuration control, programmable dead time and programmable VDS threshold for short detection. a minimum 220 nF, typically 470 nF, capacitor between CP1 and CP2. The A4910 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external MOSFETs are above 10 V at supply voltages down to 7 V. For extreme battery voltage drop conditions correct function is maintained down to 5.5 V, but with reduced gate drive. and input references. Connect to PGND (see Layout Recommendations section). The control inputs to the A4910 provide a very flexible solution for many motor control applications. Independent control over each MOSFET allows each driver to be driven with an independent PWM signal for full sinusoidal excitation. capacitance on the MOSFET gates. Connected independently to the source of the low-side MOSFET on the corresponding phase of the power bridge through a low-impedance track. Three current-sense amplifiers allow the current in each leg of the three-phase bridge to be sensed by a low-value sense resistor in the ground connection. With fast settling time, high-transient immunity, and fast overload recovery, the current-sense amplifiers are designed especially for current sensing in switched power systems. An additional uncommitted operational amplifier provides analog signal buffering and amplification. VREG Regulated voltage, nominally 13 V, used to supply the low-side gate drivers and to charge the bootstrap capacitors. A sufficiently large storage capacitor must be connected to this terminal to provide the transient charging current. AGND Analog reference ground. Quiet return for measurement PGND Digital and power ground. Connect to supply ground and AGND (see Layout Recommendations section). LSSA, LSSB, LSSC Low-side return path for discharge of the VBRG Sense input to the top of the external MOSFET bridge. Allows accurate measurement of the voltage at the drain of the high-side MOSFETs. CA, CB, CC High-side connections for the bootstrap capacitors and positive supply for high-side gate drivers. GHA, GHB, GHC High-side, gate-drive outputs for external N-channel MOSFETs. Specific functions are described more fully in the following sections. SA, SB, SC Motor phase connections. These terminals sense the voltages switched across the load. They are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drivers Input and Output Terminal Functions GLA, GLB, GLC Low-side, gate-drive outputs for external VBB Main power supply for internal regulators and charge pump. The main power supply should be connected to VBB through a reverse voltage protection circuit and should be decoupled with ceramic capacitors connected close to the supply and ground terminals. VDD Logic supply. Should be decoupled to ground with a 100 nF capacitor. Inputs have CMOS thresholds making them compatible with 3.3 V and 5 V logic. CP1, CP2 Pump capacitor connection for charge pump. Connect N-channel MOSFETs. AHI, ALO Phase A gate drive controls. Logically ORed with the corresponding bits in the Run register to control the GHA and GLA ouputs. Refer to tables 1 and 2 for detailed logic and safety lockouts. BHI, BLO Phase B gate drive controls. Logically ORed with the corresponding bits in the Run register to control the GHB and GLB ouputs. Refer to tables 1 and 2 for detailed logic and safety lockouts. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A4910 Automotive 3-Phase MOSFET Driver CHI, CLO Phase C gate drive controls. Logically ORed with the corresponding bits in the Run register to control the GHC and GLC ouputs. Refer to tables 1 and 2 for detailed logic and safety lockouts. CSAP, CSAM Phase A current-sense amplifier inputs. allowing the inputs to be driven from a 3.3 or 5 V logic interface. The main power supply should be connected to VBB through a reverse voltage protection circuit. Both supplies should be decoupled with ceramic capacitors connected close to the supply and ground terminals. The A4910 will operate within specified parameters with a VBB supply from 7 to 50 V and will function correctly with a supply down to 5.5 V. This provides a very rugged solution for use in the harsh automotive environment. CSAO Phase A current-sense amplifier output. CP1,CP2, VREG The gate drivers are powered by an internal COASTn Active-low input. Forces all gate drive outputs low and turns all external MOSFETs off. Overrides all gate drive control inputs and registers. CSBP, CSBM Phase B current-sense amplifier inputs. CSBO Phase B current-sense amplifier output. CSCP, CSCM Phase C current-sense amplifier inputs. CSCO Phase C current-sense amplifier output. OPAP, OPAM Uncommitted operational amplifier inputs. OPAO Uncommitted operational amplifier output. RESETn Resets faults when pulsed low. Forces low-power shut- down (sleep) when held low for more than the RESET shutdown time, tRSD . Can be pulled to VBB with a 30 kΩ resistor. regulator that limits the supply to the drivers and therefore the maximum gate voltage. For VBB supply greater than about 16 V the regulator is a simple buck regulator. Below 16 V the regulated supply is maintained by a charge pump boost converter which requires a pump capacitor, typically 470 nF, connected between the CP1 and CP2 terminals. The regulated voltage, nominally 13 V, is available on the VREG terminal. A sufficiently large storage capacitor (see the Applications Information section) must be connected to this terminal to provide the transient charging current to the low-side drivers and the bootstrap capacitors. SDI Serial data input. 16-bit serial word input, MSB first. Gate Drives SDO Serial data output. High impedance when STRn is high. The A4910 is designed to drive external, low on-resistance, power N-channel MOSFETs. It supplies the large transient currents necessary to quickly charge and discharge the external MOSFET gate capacitance in order to reduce dissipation in the external MOSFET during switching. The charge current for the low-side drives is provided by the capacitor on the VREG terminal. The charge current for the high-side drives is provided by the bootstrap capacitors connected between the Cx and Sx terminals, one for each phase. The charge and discharge rate can be controlled using an external resistor in series with the connection to the gate of the MOSFET. Outputs bit 15 of the fault register, the fault flag, as soon as STRn goes low. SCK Serial clock. Data is latched in from SDI on the rising edge of CLK. There must be 16-rising edges per write and SCK must be held high when STRn changes. STRn Serial data strobe and serial access enable. When STRn is high, any activity on SCK or SDI is ignored and SDO is high impedance, allowing multiple SDI slaves to have common SDI, SCK, and SDO connections. DIAG Diagnostic output. Programmable output to provide one of four functions: fault flag, temperature, clock, and VDS threshold. Default is fault flag. Power Supplies Two power supply voltages are required, one for the logic interface and one for the analog and output drive sections. The logic supply, connected to VDD, can be driven from 3 to 5.5 V, Bootstrap Charge Management The A4910 monitors the individual bootstrap capacitor charge voltages to ensure sufficient high-side drive. Before a high-side drive can be turned on, the bootstrap capacitor voltage must be higher than the turn-on voltage limit. If this is not the case, then the A4910 will attempt to charge the bootstrap capacitor by activating the complementary low-side drive. Under normal circumstances this will charge the capacitor above the turn-on voltage in a few microseconds and the high-side drive will then be enabled. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A4910 Automotive 3-Phase MOSFET Driver The bootstrap voltage monitor remains active while the high-side drive is active, and if the voltage drops below the turn-off voltage, a charge cycle is also initiated. The bootstrap charge management circuit may actively charge the bootstrap capacitor regularly when the PWM duty cycle is very high, particularly when the PWM off-time is too short to permit the bootstrap capacitor to become sufficiently charged. If, for any reason, the bootstrap capacitor cannot be sufficiently charged, a bootstrap fault will occur (see the Diagnostics section for further details). In systems where the bootstrap voltage is managed by the controller, the bootstrap management in the A4910 can be disabled. The bootstrap voltage monitor remains active and will still indicate bootstrap faults. Top-Off Charge Pump An additional top-off charge pump is provided for each phase, which allows the high-side drive to maintain the gate voltage on the external MOSFET indefinitely, ensuring so-called 100% PWM if required. This is a low current trickle charge pump and is only operated after a high-side has been signaled to turn on. There is a small amount of bias current drawn from the Cx terminal to operate the floating high-side circuit (<40 µA) and the charge pump simply provides enough drive to ensure the bootstrap voltage, and hence the gate voltage, will not droop due to this bias current. In some applications, a safety resistor is added between the gate and source of each MOSFET in the bridge. When a high-side MOSFET is held in the on-state, the current through the associated high-side gate-source resistor, RGSH , is provided by the high‑side driver and therefore appears as a static resistive load on the top-off charge pump. The minimum value of RGSH for which the top-off charge pump can provide current, without dropping below the bootstrap undervoltage threshold, is defined in the Electrical Characteristics table. In all cases, the charge required for initial turn-on of the high-side gate is always supplied by the bootstrap capacitor. If the bootstrap capacitor becomes discharged the top-off charge pump alone will not provide sufficient current to allow the MOSFET to turn on. High-Side Gate Drives GHA, GHB, GHC High-side, gate drive outputs for external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the MOSFET (as close as possible to the MOSFET) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the voltage at the SA, SB, and SC terminals. GHx set high means that the upper half of the driver is turned on and its drain will source current to the gate of the high-side MOSFET in the external motor-driving bridge, turning it on. GHx set low means that the lower half of the driver is turned on and its drain will sink current from the external MOSFET gate circuit to the respective Sx terminal, turning it off. CA, CB, CC High-side connections for the bootstrap capacitors and positive supply for high-side gate drivers. The bootstrap capacitors are charged to approximately VREG when the associated output Sx terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage required for the high-side N-channel power MOSFETs. SA, SB, SC are directly connected to the motor phase connections. These terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drivers. The discharge current from the high-side MOSFET gate capacitance flows through these connections which should have low-impedance traces to the MOSFET bridge. Low-Side Gate Drives GLA, GLB, GLC The low-side, gate drive outputs are referenced to the corresponding LSSx terminal. These outputs are designed to drive external N-channel power MOSFETs. External resistors between the gate drive output and the gate connection to the MOSFET (as close as possible to the MOSFET) can be used to control the slew rate seen at the gate, thereby providing some control of the di/dt and dv/dt of the voltage at the SA, SB, and SC terminals. GLx set high means that the upper half of the driver is turned on and its drain will source current to the gate of the low-side MOSFET in the external power bridge, turning it on. GLx set low means that the lower half of the driver is turned on and its drain will sink current from the external MOSFET gate circuit to the corresponding LSSx terminal, turning it off. LSSA, LSSB, LSSC Return paths for discharge of the low-side external MOSFET gate-source capacitances. Each LSSx pin to be connected to its associated MOSFET source by a low-impedance PCB trace. If a single sense resistor is used across all three phases, the LSSx pins may be connected together and linked to the sources of all three low-side MOSFETs. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A4910 Automotive 3-Phase MOSFET Driver Gate Drive Passive Pull-Downs Each gate drive output includes a discharge circuit to ensure that any external MOSFET connected to the gate drive output is held off when the power is removed. This discharge circuit appears as a variable resistance pull-down, but is not active when the A4910 is in normal operating mode. At low gate source voltage, less than 100 mV, the resistance is approximately 950 kΩ to ensure that any charge accumulated on the MOSFET gate has a discharge path. This resistance reduces rapidly as the voltage increases such that any MOSFET gate that becomes charged by external means is rapidly discharged to below the turn-on threshold. In some applications, this can eliminate the requirement for a permanent external gate source resistor. Dead Time To prevent cross-conduction (shoot-through) in any phase of the power MOSFET bridge, it is necessary to have a dead-time delay between a high- or low-side turn-off and the next complementary turn-on event. The potential for cross-conduction occurs when any complementary high-side and low-side pair of MOSFETs are switched at the same time—for example, when using synchronous rectification, or after a bootstrap capacitor charging cycle. In the A4910, the dead time for all three phases is set by the contents of the DT[6..0] bits in the Config0 register. These seven bits contain a positive integer that determines the dead time in system clock cycles. The dead time is defined as: tDEAD = n × 50 ns (1) where n is a positive integer defined by DT[6..0] and 50 ns is the typical system clock period. For example, when DT[6..0] contains [0 1 1 0 0 0 0] (48 decimal), then tDEAD is 2.4 µs (typical). If n = 1 or 2, tDEAD = 100 ns, the minimum dead time. The accuracy of tDEAD is determined by the accuracy of the system clock as defined in the Electrical Characteristics table. If the dead time is to be generated externally, for example by the PWM output of a microcontroller, then entering a value of zero in DT[6..0] will disable the dead timer. However, the logic that prevents cross-conduction will still be active. The internally generated dead time will only be present if the on‑command for one MOSFET occurs within one dead-time period after the off‑command for its complementary partner. In the case where one side of a phase drive is permanently off, for example when using diode rectification with slow decay, then the dead time will not occur. In this case, the gate drive will turn on within the specified propagation delay after the corresponding phase input goes high (see Figure 3). Logic Control Inputs All three motor drive phases are controlled independently as detailed in Table 1 and Table 2. Control states (HIx, LOx) are derived by combining the logic states applied to the control input pins (xHI, xLO) with the bit patterns held in the Run register (xH, xL). Normally, either the input pin or the Run register method is used for control, with the other held inactive (all pins or all bits at 0). The control input pins (xHI, xLO) are CMOS and can be driven from 3.3 or 5 V logic. Logic thresholds are ratiometric with respect to VDD and hysteresis is provided to improve noise immunity as detailed in the Electrical Characteristics table. AHI, ALO, BHI, BLO, CHI, and CLO can be used to directly con- trol the gate drives. The xHI inputs correspond to the high‑side drives and the xLO inputs correspond to the low-side drives. These logic inputs are combined, using logical OR, with the corresponding bits, xH, xL, in the serial interface Run register to determine the state of the gate drive. If the result of the OR is a logic high then the corresponding gate drive output will be high and the MOSFET will be active. Internal lockout logic ensures that the high-side output drive and low-side output drive cannot be active simultaneously. COASTn is an active-low input, which overrides any other gate control signals and forces all gate drive outputs, GHx or GLx, low to turn off all external MOSFETs. This can be used to protect the MOSFETs and the motor in the case of a short-circuit. COASTn does not clear any faults so that the fault flags can be decoded or the serial fault word can be read. It may also be used to provide fast decay PWM without synchronous rectification. RESETn is an active-low input which allows the A4910 to enter sleep mode, in which the current consumption from the VBB and VDD supplies is reduced to its minimum level. When RESETn is held low for longer than the reset shutdown time, tRSD , the regulator and all internal circuitry is disabled and the A4910 enters sleep mode. In sleep mode, the latched faults and corresponding fault flags are cleared. When coming out of sleep mode, the protection logic ensures that the gate drive outputs are off until the charge pump reaches its correct operating condition. The charge pump stabilizes in approximately 1 ms under nominal conditions. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 A4910 Automotive 3-Phase MOSFET Driver To allow the A4910 to start up without an external logic input, the RESETn terminal can be pulled to VBB with an external pull-up resistor. The resistor value should be between 20 and 33 kΩ. RESETn can also be used to clear any fault conditions without entering sleep mode by taking it low for the reset pulse width, tRST . Any latched fault conditions such as short detection or bootstrap capacitor undervoltage, which disable the outputs, will be cleared, as will the serial fault register. Current-Sense Amplifiers Three user-configurable differential sense amplifiers are provided to allow the use of low-value sense resistors or current shunts as the current-sensing elements. The input common-mode range of the CSxP and CSxM inputs allows below-ground current sensing typically required for low-side current sense in PWM motor control during switching transients. The output of the sense amplifiers are available at the CSxO outputs and can be used in peak or average current control systems. The gain of each sense amplifier is set using external input and feedback resistors. The gain must be set to be greater than the specified minimum to ensure stability. Typically the gain is set between 5 and 50 V / V. Output offset can also be added using external resistors. Examples of setting the sense amplifier gain and offset are provided in the Applications Information section. If the sense amplifiers are used for average current measurement, or in any system where peak signal full scale might not be directly accommodated, it is possible to reduce amplifier bandwidth by setting the CSB bit to 0 in the Config1 register. This will approximately reduce the bandwidth of the sense amplifier by half and will also reduce the quiescent current. Uncommitted Operational Amplifier One additional uncommitted operational amplifier is provided for general use as an analog buffer. The gain of the operational amplifier is set using external input and feedback resistors. There is sufficient open loop gain to allow closed loop gain up to 50 V / V, and the operational amplifier can be configured as a unity gain buffer. Diagnostics Several diagnostic features are integrated into the A4910 to provide indication of fault conditions. In addition to system-wide faults such as undervoltage and overtemperature, the A4910 integrates individual drain-source monitors for each external MOSFET, to provide short-circuit detection. Detailed diagnostic information can be read from the Diagnostic register through the serial interface any time. DIAG Output A single pin output that may be programmed via the serial interface to carry any one of four diagnostic signals: •a general fault flag •a voltage representing the temperature of the internal silicon •the programmed VDS threshold voltage •a clock signal derived from the internal chip clock The power-on default for the DIAG output is the general fault flag, which is low at any time when a fault is present or when one of the transient faults has been latched. Note that this is not exactly the same signal as the fault flag in the Diagnostic register. System Faults Parameters critical for the safe operation of the A4910 and of the external MOSFETs are monitored. These include chip temperature, logic supply voltage, and the voltages required to drive the external MOSFETs, namely, VREG and each of the bootstrap voltages. Note that the main supply voltage, VBB , is not monitored because the critical voltages are generated by the charge pumps internal to the A4910. VREG Undervoltage VREG powers the low-side gate drivers and provides current to charge the bootstrap capacitors. It is critical that the voltage on VREG (and, for high-side switching, the voltages on the bootstrap capacitors) is high enough prior to attempting to switch any gate drive outputs into the high, external MOSFET on, state. At power-up, all gate drive outputs and the general fault flag on the DIAG pin remain low until VREG exceeds the VREG Undervoltage Lockout threshold, VREGON (approximately 8 V). This value of VREG should be sufficient to turn on standard-threshold Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A4910 Automotive 3-Phase MOSFET Driver external power MOSFETs at a battery voltage as low as 5.5 V, though the resultant MOSFET on-resistance may be higher than its specified maximum. During normal operation, when a VREG undervoltage is detected, the general fault flag and the Diagnostic register will be set and the outputs will be disabled. When the VREG undervoltage condition is removed, the general fault flag will be cleared and the outputs enabled. The VR flag in the Diagnostic register will remain set until cleared by a register reset (see the Diagnostic Register section for serial access information). Bootstrap Undervoltage In addition to a monitor on VREG, the will be reset to their power-on state and all fault states and the general fault flag will be reset. The FF bit and the POR bit in the Diagnostic register will be set to 1 to indicate that a power-on reset has taken place. The same power-on reset sequence occurs at initial start-up or after recovery from a VDD brown-out. (A brown-out is defined as VDD momentarily dropping below the VDDUV threshold during operation.) Overtemperature An internal temperature-to-voltage converter provides a measurement of the surface temperature of the silicon. This voltage is available as an analog output on the DIAG terminal by setting DIAG[1..0] to [1 1]. A4910 also monitors the individual bootstrap capacitor charge voltages to ensure sufficient high-side drive. Two temperature thresholds are provided: a hot warning, and an overtemperature shutdown. Before a high-side drive can be turned on, the bootstrap capacitor voltage must be higher than the turn-on voltage limit. If this is not the case, and bootstrap management is enabled (Config1 register DBM bit set to 0), then the A4910 will attempt to charge the bootstrap capacitor by activating the complementary low-side drive. Under normal circumstances this will charge the capacitor above the turn-on voltage in a few microseconds and the high‑side drive will then be enabled. • If the chip temperature rises above the hot temperature warning threshold, TJWH , the Diagnostic register temperature warning bit, TW, will be set to 1 and the general fault flag will go low. No action will be taken by the A4910. When the temperature drops below TJW by more than the hysteresis value, TJWHhys , the general fault flag goes high but the TW bit remains set to 1 until reset. While the high-side drive is active, the bootstrap voltage monitor remains active. If the voltage drops below the turn-off voltage, a charge cycle is initiated. In either case, if there is a fault that prevents the bootstrap capacitor from charging, then the charge cycle will timeout, the general fault flag will be set, and the outputs will be disabled. The appropriate bit in the Diagnostic register will be set to allow the faulty bootstrap capacitor to be identified by reading the serial interface. The bootstrap undervoltage fault state will be latched until RESETn is low, a serial read is completed, or a power-on reset occurs due to a VDD undervoltage on the logic supply. VDD Undervoltage The logic supply voltage at VDD is moni- tored to ensure correct logical operation. If the voltage on VDD drops below the VDD undervoltage threshold, VDDUV , then the logical function of the A4910 cannot be guaranteed and the outputs will be immediately disabled. The A4910 will enter a powerdown state and all internal activity, other than the VDD voltage monitor, will be suspended. When the voltage at VDD rises above the rising undervoltage threshold, VDDUV + VDDUVhys , the A4910 will perform a power-on reset. All serial control registers • If the chip temperature rises above the overtemperature threshold, TJF , the overtemperature bit, OT in the Diagnostic register, will be set to 1. If the ESF bit in the Config1 register is set to 1, when an overtemperature is detected, all gate drive outputs will be disabled automatically. If ESF is set to 0, then no circuitry will be disabled and action must be taken by the user to limit the power dissipation in some way to prevent overtemperature damage to the chip and unpredictable device operation. When the temperature drops below TJF by more than the hysteresis value, TJFhys , the OT bit remains set to 1 until reset. MOSFET Faults Faults on any external MOSFETs are determined by measuring the drain-source voltage of the MOSFET and comparing it to the drain-source threshold voltage, VDSTH , defined by the VT[6..0] bits in the Config1 register. These bits provide the input to a 7-bit D-to-A converter that has a least significant bit value of 25 mV (typical). For example, when VT[6..0] contains [1 0 1 1 0 1 0] (90 decimal), then VDSTH = 2.25 V (typical). The low-side drain-source voltage for any MOSFET is measured between the LSSx terminal and the corresponding Sx terminal. Using the LSSx terminal rather than the ground connection Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 A4910 Automotive 3-Phase MOSFET Driver avoids adding any low-side current sense voltage to the real low‑side drain-source voltage. The high‑side drain-source voltage for any MOSFET is measured between the VBRG terminal and the appropriate Sx terminal. Using the VBRG terminal rather than the bridge supply avoids adding any high-side current-sense voltage to the real high-side drain-source voltage. VBRG is a low-current input allowing a voltage-sense connection to be made with the top of the external MOSFET bridge. It should be connected directly to the common connection point for the drains of the power bridge MOSFETs at the positive supply connection point. The input current to the VBRG terminal is proportional to the drain-source threshold voltage, VDSTH, and can be approximated by: IVBRG = 72 × VDSTH + 52 (2) where IVBRG is the current into the VBRG terminal in µA and VDSTH is the voltage on the VDSTH terminal in V. Fault Blanking Time To avoid false MOSFET fault detection during switching transients, the VDS to VDSTH comparison is delayed by an internal fault blanking timer. The fault blanking time is defined by the contents of the BT[5..0] bits in the Config0 register. These bits provide the input to a 6-bit counter that is clocked by a divide-by-four clock derived from the system clock (typically 20 MHz). The fault blanking time is defined as: tBL = n × 100 ns (3) where n is a positive integer defined by BT[5..0] and 100 ns is twice the typical system clock period. For example, when BT[5..0] contains [0 1 1 0 1 0] (26 decimal), then tBL is 2.6 µs (typical). Short Fault Operation As the phase switches, the measured drain-source voltage may generate a fault because power MOSFETs take a finite time to reach their rated on-resistance. To overcome this and avoid generating false short faults, the voltages are not sampled until one fault blanking time period after the external MOSFET is turned on. If the drain-source voltage remains above the threshold after the fault blanking time expires, then a short fault will be generated. If the ESF bit in the Config1 register is set to 1, this fault will be latched and the MOSFET disabled until reset. In some applications it may be necessary to increase the switching time of the external MOSFET by increasing the value of the gate resistor. This will mean that the fault blanking time may be insufficient to avoid generating incorrect fault states. In these cases, by setting the ESF bit to 0, the microcontroller driving the A4910 can be used to determine the correct fault condition. This will disable fault flag latching during a short condition and the general fault flag, available on the DIAG terminal, will only remain low while the measured drain-source voltages show a fault. The microcontroller can then monitor the fault flags and use its own timers to validate the fault condition. Note that, regardless of the ESF setting, any fault detected by the A4910 will still be latched in the Diagnostic register and remain there until reset. If a short-circuit fault occurs and ESF is set to 0, the external MOSFETs are not disabled by the A4910. To limit any damage to the external MOSFETs or to the motor, the A4910 can either be fully disabled by the RESETn input or all MOSFETs can be switched off by pulling the COASTn input low. Alternatively, setting ESF to 1 allows the A4910 to disable the MOSFETs as soon as a fault is detected. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 A4910 Automotive 3-Phase MOSFET Driver Fault Actions Actions taken in the event of fault conditions are as detailed in Table 3. Device behavior changes according to the state of the Enable Stop on Fault (ESF) bit in the Config1 register. If ESF is set to 1, any short fault or overtemperature condition disables all gate drive outputs and coasts the motor. Short faults are latched until RESETn goes low, a serial read is completed, or a power-on reset occurs. If ESF is set to 0, all gate drive outputs remain active if a short or overtemperature fault occurs, so as not to disrupt normal system operation. In this latter case (ESF set to 0) it is imperative that the master controller or other external device takes all steps necessary to protect the motor and the drive circuit. For example, COASTn or all gate drive inputs (xHi, xLO) might be taken low to turn off all external MOSFETs. Fault States Short to Supply A short from any of the motor phase connections to the battery or VBB connection is detected by monitoring the voltage across the low-side MOSFETs in each phase using the appropriate Sx and LSSx terminals. This drain-source voltage is then compared to the drain-source threshold voltage, VDSTH , after one fault blanking time period. While the drain-source voltage exceeds VDSTH , the general fault flag will be low, and if ESF is set to 1, the fault will be latched and the outputs will be disabled. Short to Ground A short from any of the motor phase connections to ground is detected by monitoring the voltage across the high-side MOSFETs in each phase using the appropriate Sx terminal and the voltage at VBRG. This drain-source voltage is then compared to the drain-source threshold voltage, VDSTH , after one fault blanking time period. While the drain-source voltage exceeds VDSTH , the general fault flag will be low, and if ESF is set to 1, the fault will be latched and the outputs will be disabled. Note that the distinction between short to ground and short to supply can only be made by reading the Diagnostic register via the serial bus. The general fault flag simply indicates the presence of a probable short-circuit. Table 3: Fault Actions Outputs Disabled Fault Description ESF=0 ESF=1 Fault Latched No fault No No - VDD Undervoltage Yes* Yes* No VREG Undervoltage Yes* Yes* No Bootstrap Undervoltage Yes* Yes* Yes Temperature Warning No No No Overtemperature No Yes* No Short to Ground No Yes* Short to Supply No Yes* Shorted Load No Yes* *All gate drives low, all MOSFETs off. Only when ESF = 1 Shorted Motor Winding The short-to-ground and short-to-supply detection circuits also detect shorts across a motor phase winding. In most cases, a shorted winding is indicated by a high-side and low-side fault latched at the same time in the Diagnostic register. In some cases, the relative impedances may only permit one of the shorts to be detected. In any case, when a short of any type is detected the general fault flag will go low and, if ESF is set to 1, the fault will be latched and the outputs will be disabled. Fault Masking Individual diagnostics, except VDD undervoltage, can be disabled by setting the corresponding bit in the Mask register. A VDD undervoltage fault cannot be disabled because the diagnostics and the output control depend on VDD to operate correctly. If a bit in the Mask register is set to one, then the corresponding diagnostic actions will be completely disabled. No fault states for the disabled diagnostic will be generated and no fault flags or Diagnostic register bits will be set. (For bit allocations, see the Mask register definition in the Serial Interface section.) Note that when diagnostics are disabled, care must be taken to avoid potentially damaging conditions. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 A4910 Automotive 3-Phase MOSFET Driver Serial interface The three-wire synchronous serial interface, compatible with SPI, can be used to control all features of the A4910. A fourth wire can be used to provide diagnostic feedback and readback of the register contents. When 16 data bits have been clocked into the shift register, STRn must be taken high to latch the data into the selected register. When this occurs, the internal control circuits act on the new data and the Diagnostic register is reset. The A4910 can be operated without the serial interface using the default settings and the phase control inputs; however, application specific configurations are only possible by setting the appropriate register bits through the serial interface. In addition to setting the configuration bits, the serial interface can also be used to control the bridge MOSFETs directly. If there are more than 16 rising edges on SCK, or if STRn goes high, and there are fewer than 16 rising edges on SCK, the write will be cancelled without writing data to the registers. In addition, the Diagnostic register will not be reset and the FF bit will be set to indicate a data transfer error. The serial interface timing requirements are specified in the Electrical Characteristics table, and illustrated in the Serial Interface Timing diagram (Figure 2). Data is received on the SDI terminal and clocked through a shift register on the rising edge of the clock signal input on the SCK terminal. STRn is normally held high, and is only brought low to initiate a serial transfer. No data is clocked through the shift register when STRn is high allowing multiple SDI slave units to use common SDI, SCK and SDO connections. Each slave then requires an independent STRn connection. Diagnostic information or the contents of the configuration and control registers is output on the SDO terminal MSB first while STRn is low and changes to the next bit on each falling edge of SCK. The first bit, which is always the FF bit from the Diagnostic register, is output as soon as STRn goes low. Each of the configuration and control registers has a write bit, WR (bit 13), as the first bit after the register address. This bit must be set to 1 to write the subsequent bits into the selected register. If WR is set to 0, then the remaining data bits (bits 12 to 0) are ignored. The state of the WR bit also determines the data output on SDO. If WR is set to 1 then the Diagnostic register is Table 4: Serial Register Definition* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration and Control Registers (Write) Configuration Register 0 (CONFIG0) 0 0 Configuration Register 1 (CONFIG1) 0 1 Mask Register 1 0 Run Register 1 1 WR BT5 BT4 BT3 BT2 BT1 BT0 DT6 DT5 DT4 DT3 DT2 DT1 DT0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 WR CSB ESF DIAG1 DIAG0 DBM – VT6 VT5 VT4 VT3 VT2 VT1 VT0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 WR – TW OT VR VA VB VC AH AL BH BL CH CL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR – – – – – – – AH AL BH BL CH CL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Diagnostic Register (Read) Diagnostic Register FF POR – – TW OT VR VA VB VC AH AL BH BL CH CL 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *Power-on reset value shown below each input register bit. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 A4910 Automotive 3-Phase MOSFET Driver output. If WR is set to 0, then the contents of the register selected by the first two bits is output. In all cases, the first two bits output on SDO will always be the FF bit and the POR bit from the Diagnostic register. Configuration and Control Registers CSB can be used to modify the bandwidth of the sense amplifiers as specified in the Electrical Characteristics table. It also has the effect of reducing the current consumption from VBB. ESF is the Enable Stop On Fault bit that defines the action taken when a short is detected. See Diagnostics section in the Functional Description above for details of fault actions. • The first two registers are used for configuration: one for blanking-time and dead-time programming, and one for system and diagnostic parameters. The DIAG[1..0] bits are set to select the output seen on the DIAG terminal. The default output is the general fault flag which is a low true signal that is active anytime a fault is present or a fault state has been latched. The other three outputs provide any external controller with the ability to read back the silicon temperature or the drain-source threshold voltage, or to measure the system clock frequency for calibration. • The third register is the fault mask register, providing the ability to disable individual diagnostics. DBM is the Disable Bootstrap Management bit and should be set to 1 if bootstrap management is not required. • The fourth register is the Run register, containing MOSFET control inputs. The Mask register contains a fault mask bit for each fault bit in the Diagnostic register. If a bit is set to 1 in the Mask register, then the corresponding diagnostic will be completely disabled. No fault states for the disabled diagnostic will be generated and no fault flags or Diagnostic register bits will be set. The serial data word is 16 bits, input MSB first. The first two bits are defined as the register address. This provides four writeable registers: Writing to any register when the WR bit is set to 1 will allow the Diagnostic register to be read at the SDO output. Configuration Register 0 (Config0) contains a 7-bit number, DT[6..0], to set the dead time and a 6-bit number, BT[5..0], to set the fault blanking time. DT[6..0] is a positive integer, n, which determines the dead time, tDEAD, in system clock cycles, defined as: tDEAD = n × 50 ns BT[5..0] is a positive integer, n, which determines the blank time, tBL, in system clock cycles, defined as: tBL = n × 100 (ns) The accuracy of tDEAD and tBL is defined by the system clock period as defined in the Electrical Characteristics table. Configuration Register 1 (Config1) contains a 7-bit number, VT[6..0], to set the drain-source threshold voltage, VDSTH, and six configuration bits, ESF, DIAG[1..0], and DBM. VT[6..0] is a positive integer, n, which determines the drainsource threshold voltage, VDSTH, in 25 mV increments, approximately defined as: VDSTH = n × 25 mV (4) The Run register contains 1 bit for each gate drive output. The first letter of the bit defines is the phase output (A, B, or C). The second letter defines high-side (H) or low-side (L) gate drive for each phase. Diagnostic Register There is one diagnostic register in addition to the three writeable registers. Each time a register is written with the WR bit set to 1, the Diagnostic register can be read, MSB first, on the serial output terminal, SDO (see Serial Timing Diagram, figure 2). The Diagnostic register contains fault flags for each fault condition, a general fault flag, and an overcurrent indicator. Whenever a fault occurs, the corresponding flag bit in the Diagnostic register will be set and latched. The fault flags in the Diagnostic register are only reset on the completion of a serial access or when the RESETn input is low for the reset pulse width, tRST. Resetting the Diagnostic register only affects latched faults that are no longer present. For any static faults that are still present, for example overtemperature, the fault flag will remain set after the register reset. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 A4910 Automotive 3-Phase MOSFET Driver At power-up or after a power-on reset, the FF bit and the POR bit are set and all other bits are reset. This indicates to the external controller that a power-on reset has taken place and all registers have been reset. Note that a power-on reset only occurs when the VDD supply rises above its undervoltage threshold. Power-on reset is not affected by the state of the VBB supply or VREG. The first bit in the register is the Diagnostic register flag. This is high if any bits in the Diagnostic register are set or if a serial write error or parity error has occurred. When STRn goes low, to start a serial write, SDO comes out of its high-impedance state and outputs the serial register fault flag irrespective of the register address or state of the WR bits. This allows the main controller to poll the A4910 through the serial interface to determine if a fault has been detected. If no faults have been detected, then the serial transfer may be terminated without generating a serial read fault by ensuring that SCK remains high while STRn is low. When STRn goes high, the transfer will be terminated and SDO will go into its high-impedance state. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 A4910 Automotive 3-Phase MOSFET Driver Serial Register Definition CONFIG0 CONFIG1 15 14 0 0 0 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WR BT5 BT4 BT3 BT2 BT1 BT0 DT6 DT5 DT4 DT3 DT2 DT1 DT0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 WR CSB ESF DIAG1 DIAG0 DBM – VT6 VT5 VT4 VT3 VT2 VT1 VT0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Configuration Register 0 (Config0) BT[5..0] DT[6..0] Fault blanking time Assumes 20 MHz clock tBL = n × 100 ns where n is a positive integer defined by BT[5..0]; for example, for the power-onreset condition, BT[5..0] = [1 0 0 0 0 0], then tBL = 3.2 µs. tBL can be between 0 ns and 6.3 µs. The accuracy of tBL is defined by the system clock period as defined in the Electrical Characteristics table. Dead time Assumes 20 MHz clock tDEAD = n × 50 ns where where n is a positive integer defined by DT[6..0] and tDEAD has a minimum value of 100 ns. For example, for the power-on reset condition, DT[6..0] = [0 1 0 0 0 0 0], tDEAD = 1.6 µs. tDEAD can be between 100 ns and 6.35µs. The accuracy of tDEAD is defined by the system clock period as defined in the Electrical Characteristics table. A value of 1 or 2 in DT[6..0] sets the minimum dead time of 100 ns. A value of all 0s disables dead time. Configuration Register 1 (Config1) Current sense bandwith CSB CSB Current sense bandwith 0 Reduced bandwidth 1 Full bandwidth Default D Enable stop on fault ESF ESF Enable stop on fault 0 Stop on fault disabled 1 Stop on fault enabled DIAG[0..1] Default D Selects signal routed to DIAG output DIAG1 DIAG0 Signal on DIAG terminal Default 0 0 D 0 1 1 1 0 1 General Fault– low true Clock / 409,600 (48.828 Hz Nominal) VDS Threshold voltage Temperature Disable bootstrap management DBM DBM 0 1 VT[6..0] Disable Bootstrap Management Bootstrap management active Bootstrap management disabled Default D VDS Threshold Typically: VDSTH = n × 25 mV where n is a positive integer defined by VT[6..0]. For example, for the power-on reset condition, VT[6..0] = [0 1 0 0 0 0 0], VDSTH = 800 mV. VDSTH can be between 0 and 3.175 V. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 A4910 Automotive 3-Phase MOSFET Driver Mask Diagnostic 15 14 1 0 FF POR 1 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WR – TW OT VR VA VB VC AH AL BH BL CH CL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 – – TW 0 OT 0 VR 0 VA 0 VB 0 VC 0 AH 0 AL 0 BH 0 BL 0 CH 0 CL 0 0 0 Mask Register — — Diagnostic Register FF Diagnostic register flag POR Power-On Reset — — TW Temperature Warning TW Temperature Warning OT Overtemperature OT Overtemperature VR VREG Undervoltage VR Undervoltage on VREG VA Phase A boot capacitor fault VA Phase A boot capacitor fault VB Phase B boot capacitor fault VB Phase B boot capacitor fault VC Phase C boot capacitor fault VC Phase C boot capacitor fault AH Phase A high-side VDS AL Phase A low-side VDS AH VDS fault detected on phase A high-side AL VDS fault detected on phase A low-side BH Phase B high-side VDS BH VDS fault detected on phase B high-side BL Phase B low-side VDS CH Phase C high-side VDS BL VDS fault detected on phase B low-side CH VDS fault detected on phase C high-side CL Phase C low-side VDS CL VDS fault detected on phase C low-side xx Fault mask 0 Fault detection permitted 1 Fault detection disabled Default xx Fault mask Default D 0 Fault detection permitted 1 Fault detection disabled D FF and POR are always output as the first two bits at the start of any serial transfer. The remaining diagnostic bits are only output if the WR bit in the incoming write is set to 1. If WR is set to 0, then the remaining bits will be the contents of the register selected by the first two bits on the SDI input. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 A4910 Automotive 3-Phase MOSFET Driver Run 15 14 1 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WR – – – – – – – AH AL BH BL CH CL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Run Register Phase A high-side control Phase A low-side control Phase B high-side control Phase B low-side control Phase C high-side control Phase C low-side control AH AL BH BL CH CL xH/L MOSFET Control 0 Corresponding gate drive controlled by external logic input 1 Corresponding gate drive high Default D ORed with corresponding logic input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 A4910 Automotive 3-Phase MOSFET Driver Application Information Dead-Time Selection A factor of 20 is a reasonable value, so The choice of power MOSFET and external series gate resistance determines the selection of the dead time. The dead time should be made long enough to ensure that one MOSFET has stopped conducting before the complementary MOSFET starts conducting. This should also account for the tolerances and variations of the MOSFET gate capacitance, the series gate resistance, and the on-resistance of the driver in the A4910. Fault Blanking Time Selection The fault blanking time should be set to avoid false short fault detection that is possible immediately after a MOSFET has been switched on. The length of time required will depend on the switching time of the MOSFET and the capacitance of the load attached to the bridge. The MOSFET switching time is dependent on the size of the MOSFET, the on-resistance of the gate drive, and the resistance between the gate drive output of the A4910 and the gate of the MOSFET. Other factors such as the load impedance, back EMF, and any switching transients also affect the settling time of the MOSFET drain-source voltage. The blanking time should be set so that it is just long enough to avoid these effects under all conditions. For highly dynamic systems, where there is a large load variation, improved short fault detection is possible by changing the blanking time between phase commutations, by using the serial interface. The new blanking time will take effect on the first off-to-on transition following the end of the serial transfer. Bootstrap Capacitor Selection CBOOT must be correctly sized to ensure that adequate gate drive is applied to high-side MOSFETs. If the selected value is too large, excessive time will be spent charging the capacitor and the maximum achievable duty cycle and PWM frequency will be reduced. If the selected value is too small, an unacceptably large voltage drop may be experienced when charge is transferred from CBOOT to the MOSFET gate. To keep the voltage drop due to charge-sharing small, the charge in the bootstrap capacitor, QBOOT , should be much larger than QGATE , the charge required by the gate: QBOOT >> QGATE(5) QBOOT = CBOOT × VBOOT = QGATE × 20 or CBOOT = QGATE × 20 VBOOT (6) where VBOOT is the voltage across the bootstrap capacitor. The voltage drop, ∆V, across the bootstrap capacitor as the MOSFET is being turned on, can be approximated by: ∆V = QGATE CBOOT (7) so for a factor of 20, ∆V will be 5% of VBOOT. The maximum voltage across the bootstrap capacitor under normal operating conditions is VREG(max). However, in some circumstances, the voltage may transiently reach 18 V—the clamp voltage of the Zener diode between the Cx terminal and the Sx terminal. In most applications with a good ceramic capacitor, the working voltage can be limited to 16 V. Bootstrap Charging It is good practice to ensure the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is requested. The time required to charge the capacitor, tCHARGE , in µs, is approximated by: tCHARGE = CBOOT × ∆V 500 (8) where CBOOT is the value of the bootstrap capacitor in nF and ∆V is the required voltage of the bootstrap capacitor. At power‑up, and when the drivers have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case, ∆V can be considered to be the full high-side drive voltage, 12 V. Otherwise, ∆V is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx terminal is pulled low and current flows from VREG through the internal bootstrap diode circuit to CBOOT . Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 A4910 Automotive 3-Phase MOSFET Driver Bootstrap Charge Management The A4910 provides automatic bootstrap capacitor charge management. The bootstrap capacitor voltage for each phase is continuously checked to ensure that it is above the bootstrap undervoltage threshold, VBOOTUV . If the bootstrap capacitor voltage drops below this threshold, the A4910 will turn on the necessary low-side MOSFET until the bootstrap capacitor exceeds the undervoltage threshold plus the hysteresis, VBOOTUV + VBOOTUVhys . The minimum charge time is typically 7 µs, but may be longer for very large values of bootstrap capacitor (>1000 nF). If bootstrap capacitor voltage does not reach the threshold within approximately 200 µs, an undervoltage fault will be flagged. In systems where the bootstrap voltage is managed by the controller, the bootstrap management in the A4910 can be disabled. The bootstrap voltage monitor remains active and will still indicate bootstrap faults. VREG Capacitor Selection The internal reference, VREG, supplies current for the low-side gate drive circuits and the charging current for the bootstrap capacitors. When a low-side MOSFET is turned on, the gate drive circuit will provide the high transient current to the gate that is necessary to turn on the MOSFET quickly. This current, which can be several hundred milliamperes, cannot be provided directly by the limited output of the VREG regulator, but instead must be supplied by an external capacitor connected to VREG. The turn-on current for the high-side MOSFET is similar in value to that of the low-side MOSFET, but is mainly supplied by the bootstrap capacitor. However the bootstrap capacitor must then be recharged from the VREG regulator output. Unfortunately, the bootstrap recharge can occur a very short time after the low‑side turn on occurs. This means that the value of the capacitor connected between VREG and AGND should be high enough to minimize the transient voltage drop on VREG for the combination of a low-side MOSFET turn-on and a bootstrap capacitor recharge. For block commutation control (trapezoidal drive), where only one high-side and one low-side are switching during each PWM period, a minimum value of 20 × CBOOT is reasonable. For sinusoidal control schemes, a minimum value of 40 × CBOOT is recommended. The maximum working voltage of the VREG capacitor will never exceed VREG, so it can be as low as 15 V. This capacitor should be placed as close as possible to the VREG terminal. Supply Decoupling Current spikes are likely to be present on all supplies because of the switching action of the circuit. As with all such circuits, the power supply connections should be decoupled with a ceramic capacitor, typically 100 nF, between the supply terminal and ground. These capacitors should be connected as close as possible to the device supply terminals VBB and VDD and the power ground terminal, PGND. Power Dissipation In applications where a high ambient temperature is expected, on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A4910 to remain in a safe range of junction temperature. The power consumed by the A4910, PD , can be estimated by: PD = PBIAS + PCPUMP + PSWITCHING(9) where PBIAS = VBB × IBB (10) PCPUMP = [( 2 × VBB) – VREG] × IAV , for VBB < 15 V (11) PCPUMP = ( VBB – VREG) × IAV , (12) for VBB > 15 V where IAV = QGATE × n × fPWM (13) and n is the number of MOSFETs switching during a PWM cycle PSWITCHING = QGATE × VREG × n × fPWM × Ratio (14) where: Ratio = 10 RGATE + 10 (15) Braking The A4910 can be used to perform dynamic braking by switching all low-side MOSFETs on and all high-side MOSFETs off or, conversely, all low-side MOSFETs off and all high-side Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31 A4910 Automotive 3-Phase MOSFET Driver MOSFETs on (COASTn high in either case). This will effectively short-circuit the back EMF of the motor, creating a braking torque. During braking, the load current can be approximated by: IBRAKE = VBEMF RL (16) where VBEMF is the voltage generated by the motor and RL is the resistance of the phase winding. Care must be taken during braking to ensure that the power MOSFET maximum ratings are not exceeded. Dynamic braking is equivalent to slow decay with synchronous rectification and all phases enabled. The A4910 can also be used to perform regenerative braking. This is equivalent to reversing the motor commutation sequence or using fast decay with synchronous rectification. Note that phase commutation must continue for regenerative braking to operate and the supply must be capable of managing the reverse current—for example, by connecting a resistive load or dumping the current to a battery or capacitor. G = RF / RM RG = RF RP = RM RG + RP CSxP CSxO RS – RM CSxM A4910 RF Figure 10: Basic current-sense amplifier configuration Current-Sense Amplifier The gain of the current-sense amplifier is set using external input and feedback resistors. Output offset zero point (output voltage corresponding to zero differential input voltage) can be adjusted by the connection of a suitable resistor network. Care must be taken to ensure that the input impedances seen from either end of the sense resistor are matched. For the basic configuration shown in Figure 10, the two input resistors (RM and RP) have the same value, as do the feedback resistor (RF) between CSxM and CSxO and the ground reference resistor (RG) between CSxP and AGND. The gain of the sense amplifier, G, is determined by the values of RF and RM, and will be approximately: G= RF RM 4.22 kΩ 78.7 kΩ 5V G = 20 VCSxO = 250 mV 76.8 kΩ 4.02 kΩ CSxP + CSxO RS – 4.02 kΩ CSxM A4910 80.6 kΩ VCSxO (17) If it is necessary to set the output offset zero point to a positive value (for example, to allow sensing of reverse currents) RG may be replaced by a three-resistor network of the type detailed in Figure 11. The values shown give a gain of 20 with the output offset zero point lifted to 250 mV. Figure 11: Typical current-sense amplifier configuration Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 32 A4910 Automotive 3-Phase MOSFET Driver Input/Output Structures Cx VBRG 18V 20V VBB GHx 20V 14V CP1 Sx VDD CP2 VREG 8V 18V 18V GLx 18V VREG 7.5V 20V 20V 20V 20V 18V 14V 6V 18V LSSx Figure 12a: Gate Drive Outputs Figure 12b: Supplies VDD VDD VDD VDD 50 kΩ PWM SDI SCK COASTn 2 kΩ 2 kΩ STRn 2 kΩ RESETn 50 kΩ 6V 50 kΩ 6V 6V 6V 7.5V Figure 12c: xHI, xLO, SDI, SCK, COASTn Inputs Figure 12d: STRn Input VDD VDD 25 Ω Figure 12e: RESETn Input 150 kΩ 7.5V 6V CSxP CSxM Figure 12f: Logic Outputs 4 kΩ OPAP OPAM SDO DIAG 6V 7.5V Figure 12g: Current Sense Amplifier Inputs 6V 6V Figure 12h: Operational Amplifier Inputs VDD 25 Ω CSxO OPAO 6V Figure 12i: Operational Amplifier and Current Sense Amplifier Outputs Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 33 A4910 Automotive 3-Phase MOSFET Driver Layout Recommendations Careful consideration must be given to PCB layout when designing high-frequency, fast-switching, high-current circuits: • The A4910 analog ground, AGND, and power ground, PGND, should be connected together at the package terminals. This common point should return separately to the negative side of the motor supply filtering capacitor. This will minimize the effect of switching noise on the device logic and analog reference. • The exposed thermal pad should be connected to the common point of AGND and PGND. • Minimize stray inductance by using short, wide copper traces at the drain and source terminals of all power MOSFETs. This includes motor lead connections, the input power bus, and the common source of the low-side power MOSFETs. This will minimize voltages induced by fast switching of large load currents. • Consider the addition of small (100 nF) ceramic decoupling capacitors across the source and drain of the power MOSFETs to limit fast transient voltage spikes caused by PCB trace inductance. • Keep the gate discharge return connections Sx and LSSx as short as possible. Any inductance on these traces will cause negative transitions on the corresponding A4910 terminals, which may exceed the absolute maximum ratings. If this is likely, consider the use of clamping diodes to limit the negative excursion on these terminals with respect to AGND. • Supply decoupling for VBB, VREG and VDD should be connected independently, close to the PGND terminal. The decou- pling capacitors should also be connected as close as possible to the relevant supply terminal. • Check the peak voltage excursion of the transients on the LSSx terminals with reference to the AGND terminal using a close-grounded (tip and barrel) probe. If the voltage at any LSSx terminal exceeds the absolute maximum in the datasheet, add additional clamping and/or capacitance between the LSSx terminal and the AGND terminal. • Gate charge drive paths and gate discharge return paths may carry a large transient current pulse. Therefore the traces from GHx, GLx, Sx and LSSx (x = A, B or C) should be as short as possible to reduce inductance in the traces. • Provide an independent connection from each LSSx terminal to the source of the corresponding low-side MOSFET in the power bridge. Connection of the LSSx terminals directly to the PGND terminal is not recommended as this may inject noise into sensitive functions such as the various voltage monitors. • The inputs to the sense amplifiers, CSxP and CSxM, should take the form of independent traces and for best results should be matched in length and route. • A low-cost diode can be placed in the connection to VBB to provide reverse-battery protection. In reverse-battery conditions, it is possible to use the body diodes of the power MOSFETs to clamp the reverse voltage to approximately 4 V. In this case, the additional diode in the VBB connection will prevent damage to the A4910 and the VBRG input will survive the reverse voltage. Optional reverse battery protection VBB VBRG VREG VDD SA SB SC A4910 GLA GLB GLC LSSA LSSB LSSC AGND + Supply GHC GHB GHA PGND Controller Supply Ground Motor RS RS RS Power Ground Supply Common Figure 13. Supply Routing Suggestions Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 34 A4910 Automotive 3-Phase MOSFET Driver Package JP, 48-Pin LQFP with Exposed Thermal Pad 0.30 9.00 ±0.20 7.00 ±0.20 0.50 1.70 7º 4° ±4 0º 0.20 0.09 C 9.00 ±0.20 7.00 ±0.20 5.00 5.00±0.04 48 1.00 REF A 1 8.60 0.60 ±0.15 48 2 0.25 BSC 5.00±0.04 1 2 SEATING PLANE 5.00 GUAGE PLANE 8.60 Branded Face 48X SEATING PLANE 0.08 C 0.50 BSC 0.22 ±0.05 C 1.60 MAX 1.40 ±0.05 0.15 0.05 PCB Layout Reference View Reference land pattern layout (reference IPC7351 QFP50P900X900X160-48M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) NNNNNNNNN YYWW LLLLLLLLL For Reference Only; not for tooling use (reference MS-026 BBCHD) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 1 B Branding scale and appearance at supplier discretion C Exposed thermal pad (bottom surface) ; exact dimensions may vary with device B Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Lot number Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 35 A4910 Automotive 3-Phase MOSFET Driver Revision History Number Date – January 24, 2013 Initial release Description 1 October 7, 2015 Change in tBL 2 May 18, 2016 Updated VBB, VREG, Short-to-Battery, and Short-to-Ground test conditions, updated VBRG Input Voltage min value, and removed footnote 1 from Electrical Characteristics table; corrected Figure 12c. Copyright ©2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 36