Si1869DH Datasheet

Si1869DH
Vishay Siliconix
Load Switch with Level-Shift
FEATURES
PRODUCT SUMMARY
VDS2 (V)
1.8 to 20
RDS(on) (Ω)
ID (A)
0.165 at VIN = 4.5 V
± 1.2
0.222 at VIN = 2.5 V
± 1.0
0.303 at VIN = 1.8 V
± 0.7
DESCRIPTION
The Si1869DH includes a p- and n-channel MOSFET in a
single SC70-6 package. The low on-resistance p-channel
TrenchFET is tailored for use as a load switch. The
n-channel, with an external resistor, can be used as a levelshift to drive the p-channel load-switch. The n-channel
MOSFET has internal ESD protection and can be driven by
logic signals as low as 1.5 V. The Si1869DH operates on
supply lines from 1.8 V to 20 V, and can drive loads up to
1.2 A.
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFETs: 1.8 V Rated
• ESD Protected: 2000 V On Input Switch,
VON/OFF
• 165 mΩ Low RDS(on)
• 1.8 to 20 V Input
• 1.5 to 8 V Logic Level Control
• Low Profile, Small Footprint SC70-6 Package
• Adjustable Slew-Rate
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Level Shift for Portable Devices
APPLICATION CIRCUITS
40
Si1869DH
tf
35
2, 3
4
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
30
VOUT
VIN
Q2
25
C1
6
Time (µs)
R1
6
20
td(off)
15
5
ON/OFF
Co
LOAD
10
Q1
5
tr
td(on)
0
Ci
0
1
2
4
6
8
10
R2 (kΩ)
R2
GND
R2
Note: For R2 switching variations with other VIN/R1
combinations see Typical Characteristics
Switching Variation
R2 at VIN = 2.5 V, R1 = 20 kΩ
COMPONENTS
R1
Pull-Up Resistor
Typical 10 kΩ to 1 MΩ*
R2
Optional Slew-Rate Control
Typical 0 to 100 kΩ*
C1
Optional Slew-Rate Control
Typical 1000 pF
The Si1869DH is ideally suited for high-side load switching in
portable applications. The integrated n-channel level-shift
device saves space by reducing external components. The
slew rate is set externally so that rise-times can be tailored to
different load types.
* Minimum R1 value should be at least 10 x R2 to ensure Q1 turn-on.
Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
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1
Si1869DH
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
SC70-6
Si1869DH
Top View
4
2, 3
D2
S2
R2
1
6
Q2
R1, C1
6
2
5
ON/OFF
VC
D2
3
4
R1,
C1
XX
YY
D2
Marking Code
5
Lot Traceability
and Date Code
S2
Q1
ON/OFF
Part # Code
Ordering Information: Si1869DH-T1-E3 (Lead (Pb)-free)
Si1869DH-T1-GE3 (Lead (Pb)-free and Halogen-free)
R2
1
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage (D2-S2)
VDS
- 20
Input Voltage
VIN
20
ON/OFF Voltage
Load Current
± 1.2
IL
Pulsedb, c
V
8
VON/OFF
Continuousa, b
Unit
±3
A
Continuous Intrinsic Diode Conductiona
IS
- 0.4
Maximum Power Dissipationa
PD
1.0
TJ, Tstg
- 55 to 150
°C
ESD
2
kV
Operating Junction and Storage Temperature Range
ESD Rating, MIL-STD-883D Human Body Model (100 pF, 1500 Ω)
W
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Maximum Junction-to-Ambient (Continuous Current)a
RthJA
100
125
Maximum Junction-to-Foot (Q2)
RthJF
44
55
Unit
°C/W
SPECIFICATIONS TJ = 25 °C unless otherwise noted
Parameter
Symbol
Test Conditions
Reverse Leakage Current
IFL
VIN = 8 V, VON/OFF = 0 V
Diode Forward Voltage
VSD
IS = - 0.4 A
Min.
Typ.
Max.
Unit
1
µA
0.4
0.6
1.1
V
OFF Characteristics
ON Characteristics
1.8
20
Input Voltage Range
VIN
Drain to Source Breakdown Voltage
VDS
VGS = 0 V, ID = - 250 µA
VON/OFF = 1.5 V, VIN = 4.5 V, ID = 1.2 A
0.132
0.165
RDS(on)
VON/OFF = 1.5 V, VIN = 2.5 V, ID = 1.0 A
0.177
0.222
0.242
0.303
On-Resistance (P-Channel) at 1 A
- 20
VON/OFF = 1.5 V, VIN = 1.8 V, ID = 0.7 A
On-State (P-Channel) Drain-Current
ID(on)
VIN-OUT ≤ 0.2 V, VIN = 5 V, VON/OFF = 1.5 V
1
VIN-OUT ≤ 0.3 V, VIN = 3 V, VON/OFF = 1.5 V
1
V
Ω
A
Notes:
a. Surface mounted on FR4 board.
b. VIN = 20 V, VON/OFF = 8 V, TA = 25 °C.
c. Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
Si1869DH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.6
0.6
0.5
0.5
0.4
0.4
VDROP (V)
V DROP (V)
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
0.3
TJ = 25 °C
0.2
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
0.3
0.2
TJ = 25 °C
0.1
0.1
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.0
3.0
0.5
1.0
1.5
2.0
IL (A)
IL (A)
VDROP vs. IL at VIN = 4.5 V
VDROP vs. IL at VIN = 2.5 V
2.5
0.5
0.6
VON/OFF = 1.5 V to 8 V
VON/OFF = 1.5 V to 8 V
0.5
0.4
V DROP (V)
VDROP (V)
0.4
TJ = 125 °C
0.3
TJ = 25 °C
0.3
0.2
TJ = 125 °C
0.2
0.1
0.1
TJ = 25 °C
0.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
1.6
1
2
3
5
IL (A)
VIN (V)
VDROP vs. IL at VIN = 1.8 V
VDROP vs. VIN at IL = 0.7 A
6
0.5
0.10
IL = 0.7 A
VON/OFF = 1.5 V to 8 V
IL = 0.7 A
VON/OFF = 1.5 V to 8 V
R SS(on) - On-Resistance (Ω)
0.06
VIN = 1.8 V
V DROP Variance (V)
4
VIN = 4.5 V
0.02
- 0.02
0.4
0.3
TJ = 125 °C
0.2
TJ = 25 °C
0.1
- 0.06
- 0.10
- 50
0.0
- 25
0
25
50
75
100
125
TJ - Junction Temperature (°C)
VDROP Variance vs. Junction Temperature
Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
150
0
1
2
3
4
5
6
VIN (V)
On-Resistance vs. Input Voltage
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Si1869DH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1.6
20
IL = 0.7 A
VON/OFF = 1.5 V to 8 V
VIN = 4.5 V
tf
VIN = 1.8 V
1.2
td(off)
16
Time ( µs)
R DS(on) - On-Resistance
(Normalized)
1.4
1.0
0.8
12
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
8
4
tr
0.6
- 50
td(on)
0
- 25
0
25
50
75
100
125
0
150
2
4
TJ - Junction Temperature (°C)
6
8
10
R2 (kΩ)
Switching Variation
R2 at VIN = 4.5 V, R1 = 20 kΩ
Normalized On-Resistance
vs. Junction Temperature
100
40
tf
35
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
25
80
Time ( µs)
Time ( µs)
30
20
td(off)
15
tf
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
60
40
10
td(off)
20
5
tr
td(on)
tr
0
0
0
2
4
6
8
0
10
td(on)
2
4
R2 (kΩ)
6
8
10
R2 (kΩ)
Switching Variation
R2 at VIN = 2.5 V, R1 = 20 kΩ
Switching Variation
R2 at VIN = 1.8 V, R1 = 20 kΩ
250
200
td(off)
td(off)
200
150
Time ( µs)
Time ( µs)
150
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
100
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
100
tf
tf
50
50
tr
td(on)
td(on)
tr
0
0
0
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4
20
40
60
80
100
0
20
40
60
80
R2 (kΩ)
R2 (kΩ)
Switching Variation
R2 at VIN = 4.5 V, R1 = 300 kΩ
Switching Variation
R2 at VIN = 2.5 V, R1 = 300 kΩ
100
Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
Si1869DH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
200
td(off)
IL = 1 A
VON/OFF = 3 V
Ci = 10 µF
Co = 1 µF
Time ( µs)
150
100
tf
50
td(on)
tr
0
0
20
40
60
80
100
R2 (kΩ)
Switching Variation
R2 at VIN = 1.8 V, R1 = 300 kΩ
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 100 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
0.01
10-4
4. Surface Mounted
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73449.
Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
www.vishay.com
5
Package Information
Vishay Siliconix
SCĆ70:
6ĆLEADS
MILLIMETERS
6
5
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
4
E1 E
1
2
3
-B-
e
b
e1
D
-Ac
A2 A
L
A1
Document Number: 71154
06-Jul-01
INCHES
Min
Nom
Max
Min
Nom
Max
0.90
–
1.10
0.035
–
0.043
–
–
0.10
–
–
0.004
0.80
–
1.00
0.031
–
0.039
0.15
–
0.30
0.006
–
0.012
0.10
–
0.25
0.004
–
0.010
1.80
2.00
2.20
0.071
0.079
0.087
1.80
2.10
2.40
0.071
0.083
0.094
1.15
1.25
1.35
0.045
0.049
0.053
0.65BSC
0.026BSC
1.20
1.30
1.40
0.047
0.051
0.055
0.10
0.20
0.30
0.004
0.008
0.012
7_Nom
7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
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AN816
Vishay Siliconix
Dual-Channel LITTLE FOOTR 6-Pin SC-70 MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
87 (mil)
26 (mil)
The new dual 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the dual-channel version.
6
5
96 (mil)
71 (mil)
48 (mil)
23 (mil)
61 (mil)
1
PIN-OUT
4
2
3
0.0 (mil)
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
Both n-and p-channel devices are available in this package –
the drawing example below illustrates the p-channel device.
26 (mil)
16 (mil)
FIGURE 2.
SOT-363
SC-70 (6-LEADS)
S1
1
6
D1
G1
2
5
G2
D2
3
4
S2
Top View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the SC-70
6-pin basic pad layout and dimensions. This pad pattern is
sufficient for the low-power applications for which this package
is intended. Increasing the drain pad pattern (Figure 2) yields
a reduction in thermal resistance and is a preferred footprint.
Document Number: 71405
12-Dec-03
8 (mil)
SC-70 (6 leads) Dual
EVALUATION BOARD FOR THE DUALCHANNEL SC70-6
The 6-pin SC-70 evaluation board (EVB) shown in Figure 3
measures 0.6 in. by 0.5 in. The copper pad traces are the same
as described in the previous section, Basic Pad Patterns. The
board allows for examination from the outer pins to the 6-pin
DIP connections, permitting test sockets to be used in
evaluation testing.
The thermal performance of the dual 6-pin SC-70 has been
measured on the EVB, comparing both the copper and Alloy
42 leadframes. This test was then repeated using the 1-inch2
PCB with dual-side copper coating.
A helpful way of displaying the thermal performance of the
6-pin SC-70 dual copper leadframe is to compare it to the
traditional Alloy 42 version.
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1
AN816
Vishay Siliconix
Front of Board SC70-6
Back of Board SC70-6
S1
D1
G1
G2
D2
S2
vishay.com
SC70−6 DUAL
FIGURE 3.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
COOPER LEADFRAME
Room Ambient 25 _C
Thermal performance for the dual SC-70 6-pin package is
measured as junction-to-foot thermal resistance, in which the
“foot” is the drain lead of the device as it connects with the
body. The junction-to-foot thermal resistance for this device is
typically 80_C/W, with a maximum thermal resistance of
approximately 100_C/W. This data compares favorably with
another compact, dual-channel package – the dual TSOP-6 –
which features a typical thermal resistance of 75_C/W and a
maximum of 90_C/W.
PD +
Elevated Ambient 60 _C
T J(max) * T A
Rq JA
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
224 CńW
o
o
P D + 150 Co* 60 C
224 CńW
P D + 558 mW
P D + 402 mW
Although they are intended for low-power applications,
devices in the 6-pin SC-70 dual-channel configuration will
handle power dissipation in excess of 0.5 W.
TESTING
Power Dissipation
The typical RθJA for the dual-channel 6-pin SC-70 with a
copper leadframe is 224_C/W steady-state, compared to
413_C/W for the Alloy 42 version. All figures are based on the
1-inch2 FR4 test board. The following example shows how the
thermal resistance impacts power dissipation for the dual 6-pin
SC-70 package at varying ambient temperatures.
To further aid the comparison of copper and Alloy 42
leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin
SC-70 thermal performance on two different board sizes and
pad patterns. The measured steady-state values of RθJA for
the dual 6-pin SC-70 with varying leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
1) Minimum recommended pad pattern on
the EVB board (see Figure 3).
Alloy 42 Leadframe
1-inch2
2) Industry standard
PCB with
maximum copper both sides.
ALLOY 42 LEADFRAME
Room Ambient 25 _C
PD +
T J(max) * T A
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
413 CńW
o
o
P D + 150 Co* 60 C
413 CńW
P D + 303 mW
P D + 218 mW
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2
Rq JA
Elevated Ambient 60 _C
Alloy 42
Copper
518_C/W
344_C/W
413_C/W
224_C/W
The results indicate that designers can reduce thermal
resistance (θJA) by 34% simply by using the copper leadframe
device as opposed to the Alloy 42 version. In this example, a
174_C/W reduction was achieved without an increase in board
area. If an increase in board size is feasible, a further 120_C/W
reduction can be obtained by utilizing a 1-inch2. PCB area.
The Dual copper leadframe versions have the following suffix:
Dual:
Compl.:
Si19xxEDH
Si15xxEDH
Document Number: 71405
12-Dec-03
AN816
500
500
400
400
Thermal Resistance (C/W)
Thermal Resistance (C/W)
Vishay Siliconix
300
Alloy 42
200
Copper
100
300
Alloy
42
200
100
Copper
0
0
10-5
10-4
10-3
10-2
10-1
1
10
100
1000
10-5
Dual SC70-6 Thermal Performance on EVB
Document Number: 71405
12-Dec-03
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
Time (Secs)
FIGURE 4.
10-4
FIGURE 5.
Dual SC70-6 Comparison on 1-inch2 PCB
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3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.067
0.026
(0.648)
0.045
(1.143)
0.096
(2.438)
(1.702)
0.016
0.026
0.010
(0.406)
(0.648)
(0.241)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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18
Document Number: 72602
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000