Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices

Designing for Migration from
MachXO2-1200-R1 to
Standard (Non-R1) Devices
April 2012
Application Note AN8086
Introduction
The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts
except as listed below:
1. The EFB UFM cannot be programmed through the WISHBONE interface.
2. The on-chip differential input termination resistor value is higher than intended.
3. The SRAM CRC Error Detection Circuit may not produce the correct result when it is run for the first time
after configuration.
4. Under certain conditions, IIH exceeds data sheet specifications.
5. The user SPI interface does not operate correctly in some situations.
6. In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch.
7. When using the hard I2C IP core, the I2C status registers I2C_1_SR and I2C_2_SR may not update correctly.
8. PLL Lock signal will glitch high when coming out of standby.
The Standard MachXO2-1200 devices have no specification exceptions and will be available in September 2011.
Along with the ordering part numbers the devices can be physically identified with the top side marking, as shown
in Figure 1.
Figure 1. MachXO2-1200 Top Side Marking for R1 and Standard MachXO2-1200 Devices
MachXO2
LCMXO2-1200HC
6TG144CR1
Datecode
LCMXO2-1200HC
6TG144C
Datecode
To ensure JED file compatibility when migrating between the R1 and Standard devices, the exceptions must be
designed for. The following table and flow chart can be used to determine the migration requirements between the
R1 and Standard devices.
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an8086_01.2
Designing for Migration from
MachXO2-1200-R1 to Standard (Non-R1) Devices
Table 1. Summary of the R1 and Standard Device Differences1, 2, 3
Item
Migration Requirement
Summary of the R1 to Standard Device Differences
1
Optional Redesign
EFB UFM cannot be programmed through the WISHBONE interface
2
JED File Compatible
The on-chip differential input termination resistor value is higher than intended
3
Optional Redesign
SRAM CRC Error Detection Circuit may not produce the correct result when it is run for
the first time after configuration
4
JED File Compatible
Under certain conditions, IIH exceeds data sheet specifications
5
Redesign Required
The user SPI interface does not operate correctly in some situations
6
JED File Compatible
In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch
7
Optional Redesign
When using the hard I2C IP core, the I2C status registers I2C_1_SR and I2C_2_SR may
not update correctly
8
Optional Redesign
PLL Lock signal will glitch high when coming out of standby
1. “JED File Compatible” is defined as equivalent functionality and performance in either the R1 or the Standard device
2. “Optional Redesign” is defined as “JED File Compatible” but the design could be optimized to improve performance in the Standard device.
3. “Redesign Required” is defined as the design must be redesigned to ensure Standard device functionality.
Figure 2. Logical Flow Chart for Design Migration
Start
Design uses EFB
Design uses
SPI via WB
Y
N
Y
Item
#5
Y
Item
#1
Y
Item
#7
N
Design uses UFM
N
Design uses I2C
N
Design uses PLL
Y
Item
#8
Y
Item
#3
N
Design uses
SRAM CRC
N
Design uses
I/O
Y
Design uses on-chip
termination
Y
Item
#2
Design requires
low IIH
Y
Item
#4
Design uses
DDRX2/4, GDDR71
Y
Item
#6
N
N
Stop
Redesign Required
Optional Redesign
JED File Compatible
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Designing for Migration from
MachXO2-1200-R1 to Standard (Non-R1) Devices
Details of Design Migration Considerations
1. When using the R1 device, the User Flash Memory (UFM) cannot be programmed through the internal
WISHBONE interface.
– R1 UFM can still be programmed through the JTAG/SPI/I2C ports
– R1 UFM can be accessed via WISHBONE with certain requirements and limitations:
- The hard SPI port or primary I2C port must be instantiated in the user design.
- If instantiating the SPI port for this purpose, the four SPI signals must be routed to the dedicated SPI pins of the device and the SN pulled to VCCIO either internally or externally.
- If using the I2C port, the two I2C signals must be routed to the dedicated I2C pins of the
device, and both pulled to VCCIO internally or externally.
2. The on-chip differential input termination resistor value is higher than intended. It is approximately 200 as
opposed to the intended 100.
– When using R1 devices external termination resistors should be used for differential inputs.
– Internal on-chip termination resistors can be disabled through Lattice Diamond® Spreadsheet View.
3. SRAM CRC Error Detection Circuit may not produce the correct result when it is run for the first time after
configuration.
– To use this feature, discard the result from the first operation, subsequent operations will produce
the correct result.
– This has been documented in TN1206, MachXO2 SRAM CRC Error Detection Usage Guide.
4. Under certain conditions, IIH exceeds data sheet specifications.
– The IIH limits from the data sheet are summarized below.
Condition
Clamp
Pad Rising
IIH Max.
Pad Falling
IIH Min.
Steady State Pad
High IIH
Steady State Pad
Low IIL
VPAD > VCCIO
OFF
1 mA
-1 mA
1 mA
10 A
VPAD = VCCIO
ON
10 A
-10 A
10 A
10 A
VPAD = VCCIO
OFF
1 mA
-1 mA
1 mA
10 A
VPAD < VCCIO
ON
10 A
-10 A
10 A
10 A
5. R1 user SPI interface does not operate correctly in some situations.
– During master read access and slave write access, the last byte received does not generate the
RRDY interrupt in User mode SPI access through the WISHBONE.
– Production devices requiring User mode SPI access through the WISHBONE should only use the
Standard device to ensure bitstream compatibility.
– For detailed information on the R1 workaround, refer to the Hardened SPI IP Cores section of
TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
- The R1 device does support User mode SPI access but the design must be modified to ignore
a bye of data.
- Diamond 1.2 (and later versions) only include simulation libraries for the Standard device.
Contact Lattice Technical Support for instructions on download and installation for the R1 EFB
simulation model.
6. In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain
conditions, leading to possible loss of synchronization.
– ECLKSYNC block uses rising edge flip-flops instead of falling edge flip-flops. As a result, there may
be a timing violation which appears as a glitch.
– Production designs using GDDRX2, GDDRX4 and GDDR71 interfaces should only use the Standard devices.
7. When using the hard I2C IP core, the I2C status registers I2C_1_SR and I2C_2_SR may not update correctly.
– The I2C status registers I2C_1_SR and I2C_2_SR may not update correctly because there is a sev3
Designing for Migration from
MachXO2-1200-R1 to Standard (Non-R1) Devices
eral microseconds of latency before the I2C status register reflects the proper status of BUSY/TIP.
– To ensure compatibility with the Standard device these status bits should not be used. As an alternate TRRDY can be monitored.
– For detailed information on the instructions, refer to the Hardened I2C IP Cores section of TN1205,
Using User Flash Memory and Hardened Control Functions in MachXO2 Devices.
– R1 to Standard device migration can be verified through simulation. Diamond 1.2 (and later versions) only include simulation libraries for the Standard device. Contact Lattice Technical Support for
instructions on download installation for the R1 EFB simulation model.
8. The PLL Lock signal will glitch high when coming out of standby.
– The lock glitch lasts for about 10 µsec before returning low.
– To ensure bitstream compatibility the PLL lock signal can be ignored or the PLL lock monitoring circuit should implement a delay when coming out of standby.
– For more information, refer to TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide.
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e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
Change Summary
July 2011
01.0
Initial release.
August 2011
01.1
Clarified UFM access requirements and limitations.
April 2012
01.2
Updated document with new corporate logo.
Figure 1, topside marks updated.
Update to remove dummy page restriction in UFM algorithm.
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