A1360, A1361, A1362 Datasheet

A1360, A1361, and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: December 1, 2015
Deadline for receipt of LAST TIME BUY orders: May 31, 2016
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A1360, A1361, and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Features and Benefits
Description
•
1 mm case thickness provides greater coupling for current
sensing applications
•
Customer programmable offset and sensitivity
•
Factory programmed 0% / °C sensitivity temperature coefficient
•
Programmability at end-of-line
•
Selectable unipolar or bipolar quiescent voltage levels
•
Selectable sensitivity ranges between 0.7 and 1.4 mV/G (A1360),
1.4 to 4.5 mV/G (A1361) and 4.5 to 16 mV/G (A1362)
•
Device bandwidth selectable under 50 kHz, via capacitor on
FILTER pin
•
Ratiometric sensitivity, quiescent voltage output, and clamps for
interfacing with application DAC
•
Temperature-stable quiescent voltage output and sensitivity
•
Precise recoverability after temperature cycling
•
Output voltage clamps provide short circuit diagnostic capabilities
•
Wide ambient temperature range: – 40°C to 150°C
•
Resistant to mechanical stress
New applications for linear output Hall effect sensing, such
as current measurement, require both high accuracy and
increased sensor bandwidth. The Allegro™ A1360, A1361,
and A1362 programmable linear Hall effect sensor ICs are
designed specifically to achieve both goals. Available in a
through-hole SIP (single in-line package), the A136x Hall
effect sensor ICs are sensitive and temperature-stable. The
accuracy of these devices is enhanced via programmability on
the device VOUT pin. A capacitor to ground on the FILTER
pin on the A136x can be used to tune the device bandwidth in
a range less than 50 kHz.
These ratiometric Hall effect sensor ICs provide a voltage
output that is proportional to the applied magnetic field. The
quiescent output voltage is user-adjustable around either
50% (bidirectional configuration) or 10% (unidirectional
configuration) of the supply voltage, VCC. The device sensitivity
is adjustable within three guaranteed ranges: 0.7 to 1.4 mV/G
(A1360), 1.4 to 4.5 mV/G (A1361), and 4.5 to 16 mV/G
(A1362).
Package: 4 pin SIP (suffix KT)
1 mm case thickness
Each BiCMOS monolithic circuit integrates a Hall element,
temperature-compensation circuitry to reduce the intrinsic
sensitivity drift of the Hall element, a small-signal high-gain
amplifier, a clamped low-impedance output stage, and a
proprietary dynamic offset cancellation technique.
Continued on the next page…
Not to scale
Functional Block Diagram
V+
VCC
To subcircuits
Ratiometric
Hall Drive
Program/Lock
Trim Control
Sensitivity
Sensitivity
Temperature
Coefficient
Offset
FILTER
Dynamic Offset
Cancellation
C.BYPASS
+
Signal Recovery
GND
A1360-DS, Rev. 5
–
+
–
VOUT
(Programming)
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Description (continued)
The features of these linear Hall effect sensor ICs make them ideal
for meeting high accuracy requirements in automotive and industrial
applications. Device specifications guaranteed over an extended
ambient temperature range: –40°C to 150°C.
The A136x sensor ICs are provided in an extremely thin case (1
mm thick), 4-pin SIP (single in-line package, suffix KT) that is lead
(Pb) free, with 100% matte tin leadframe plating.
Selection Guide1
Part Number
Sensitivity Range
(mV/G)
Packing2
A1360LKTTN-T
4000 pieces per 13-in. reel
0.7 to 1.4
A1361LKTTN-T
4000 pieces per 13-in. reel
1.4 to 4.5
A1362LKTTN-T
4000 pieces per 13-in. reel
4.5 to 16
1All
variants are programmable for unidirectional or bidirectional use.
2Contact Allegro for additional packing options.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
Forward Supply Voltage
VCC
8
V
Reverse Supply Voltage
VRCC
–0.1
V
Forward Output Voltage
VOUT
28
V
Reverse Output Voltage
VROUT
–0.1
V
Forward Filter Voltage
VFILTER
8
V
Reverse Filter Voltage
VRFILTER
Output Source Current
IOUT(SOURCE)
VOUT to GND
IOUT(SINK)
VCC to VOUT
Output Sink Current
Ambient Operating Temperature
TA
Range L
–0.1
V
3
mA
10
mA
–40 to 150
°C
Storage Temperature
Tstg
–65 to 165
°C
Junction Temperature
TJ(max)
165
°C
Pin-out Diagram
Terminal List Table
Number
1
2
3
Name
1
VCC
2
VOUT
3
FILTER
4
GND
Description
Input power supply; use bypass capacitor to connect to ground
Output signal; also used for programming
Terminal for external filter capacitor for bandwidth setting
Ground
4
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
OPERATING CHARACTERISTICS valid over full operating temperature range, TA; CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise specified
Characteristic
Electrical Characteristics
Supply Voltage
Supply Current
Symbol
VCC
ICC
Power-On Time1
tPO
Supply Zener Clamp Voltage
VZ
Internal Bandwidth
BWi
Filtered Bandwidth
BWf
Chopping Frequency2
Output Characteristics
fC
Propagation Delay Time1
tpd
Rise Time1
tr
Response
Delay to
Time1
Clamp1
tRESPONSE
tCLP
VCLP(HIGH)
Output Voltage Clamp3
VCLP(LOW)
Noise (peak-to-peak)4
DC Output Resistance
Output Load Resistance
Output Load Capacitance
Phase Shift5
Output Slew Rate6
VN(p-p)
Test Conditions
No load on VOUT
TA = 25°C, CL (of test probe) = 10 pF, CBYPASS =
open; Sens = 4.5 mV/G
TA = 25°C, ICC = 13 mA
Small signal –3 dB, 100 G(P-P) magnetic input
signal, CFILTER = open, CL = 10 nF
Small signal –3 dB, 100 G(P-P) magnetic input
signal, CFILTER = 1 nF, CL = 10 nF
TA = 25°C
TA = 25°C, impulse magnetic field of 400 G,
CFILTER = open, CL = 10 nF
TA = 25°C, impulse magnetic field of 400 G,
CFILTER = open, CL = 10 nF
TA = 25°C, CL = 10 nF
TA = 25°C, impulse magnetic field of 400 G,
CFILTER = open, CL = 10 nF
A1360
TA = 25°C, B = 600 G, Sens = 5.0 mV/G,
A1361
RL(PULLDWN) = 10 kΩ
A1362
A1360
TA = 25°C, B = 600 G, Sens = 5.0 mV/G,
A1361
RL(PULLUP) = 10 kΩ
A1362
TA = 25°C, CL = 10 nF, Sens = 1.5 mV/G,
CFILTER = 1 nF (BWf = 50 kHz)
TA = 25°C, CL = 10 nF, Sens = 6.6 mV/G,
CFILTER = 47 nF (BWf = 2 kHz)
TA = 25°C, CL = 10 nF, Sens = 6.6 mV/G,
CFILTER = 1 nF (BWf = 50 kHz)
ROUT
RL(PULLUP) VOUT to VCC
RL (PULLDWN) VOUT to GND
CL
VOUT to GND
CL = 10 nF, CFLITER = 1 nF (BW = 50 kHz),
ΔΦ
magnetic input signal frequency = 1 kHz with
1 V(p-p) output signal
SR
Sens = 4.5 mV/G, CL = 10 nF
Min.
Typ.
Max.
Units
4.5
–
5.0
9.2
5.5
12
V
mA
–
30
–
μs
6
7.6
–
V
50
–
–
kHz
–
–
50
kHz
–
210
–
kHz
–
1.6
–
μs
–
5.5
–
μs
–
7.0
–
μs
–
30
–
μs
4.65
4.65
4.65
0.25
0.25
0.25
4.73
4.73
4.78
0.32
0.32
0.32
4.80
4.80
4.91
0.4
0.4
0.4
V
V
V
V
V
V
–
8
–
mV
–
8.5
–
mV
–
38
–
mV
–
4.7
4.7
–
<1
–
–
–
–
–
–
10
Ω
kΩ
kΩ
nF
–
2.5
–
deg.
–
210
–
V/ms
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
OPERATING CHARACTERISTICS (continued) valid over full operating temperature range, TA; CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise specified
Characteristic
Pre-Programming Target7
Pre-Programming Quiescent
Voltage Output
Pre-Programming Sensitivity
Symbol
Min.
Typ.
Max.
Units
–
2.0
–
V
–
–
–
0.5
1.1
2.7
–
–
–
mV/G
mV/G
mV/G
–
–
VCLP(LOW)
VOUT(Q)PRE
–
–
V
V
–
1
–
bit
0.40
2.15
–
–
1.15
2.85
V
V
–
8
–
bit
TA = 25°C
3.4
3.85
4.4
mV
TA = 25°C
–
StepVOUT(Q) ×
±0.5
–
mV
SensPRE
–
–
–
8
5.3
16
79
StepSENS ×
±0.5
–
1.4
4.5
16
–
6.2
21
90
mV/G
mV/G
mV/G
mV/G
bit
µV/G
µV/G
µV/G
–
µV/G
–
1
–
bit
–0.025
0
0.025
%/°C
–3.0
–2.5
–2.0
–3.5
–3.0
–3.0
–
–
–
–
–
–
3.0
2.5
2.0
3.5
3.0
3.0
%
%
%
%
%
%
–
< ±1.5
–
%
–
–
< ±1.5
< ±1.5
–
–
%
%
VOUT(Q)PRE B = 0 G, TA = 25°C
SensPRE
Quiescent Voltage Output Programming
VOUT(Q)UNIinit
Initial Quiescent Voltage Output8
VOUT(Q)BIinit
Coarse Quiescent Voltage Output
Programming Bits9
VOUT(Q)UNI
Guaranteed Quiescent Voltage
Output Range10,11
VOUT(Q)BI
Quiescent Voltage Output
Programming Bits
Average Quiescent Voltage
StepVOUT(Q)
Output Step Size12,13
Quiescent Output Voltage
ErrPGVOUT(Q)
Programming Resolution14
Sensitivity Programming
Initial Sensitivity
Sensinit
Guaranteed Sensitivity
Range15,16
Test Conditions
Sens
A1360
A1361
A1362
TA = 25°C
B = 0 G, TA = 25°C
B = 0 G, TA = 25°C
TA = 25°C
A1360
A1361 TA = 25°C
A1362
Sensitivity Programming Bits
Average Sensitivity Step Size12.13
StepSENS
A1360
A1361 TA = 25°C
A1362
Sensitivity Programming
ErrPGSENS TA = 25°C
Resolution14
Lock Bit Programming
Overall Programming Lock Bit
LOCK
Factory-Programmed Sensitivity Temperature Coefficient
Sensitivity Temperature
TCSENS
Coefficient17
Error Components
A1360
Linearity Sensitivity Error18
A1361
LinERR
A1362
A1360
Symmetry Sensitivity Error19
A1361
SymERR
A1362
Ratiometry Quiescent Voltage
RatERRVOUT(Q)
Output Error20
Ratiometry Sensitivity Error20
RatERRSENS
Ratiometry Clamp Error21
RatSENSCLP TA = 25°C
–
0.7
1.4
4.5
–
4.2
15
65
–
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
OPERATING CHARACTERISTICS (continued) valid over full operating temperature range, TA; CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise specified
Characteristic
Drift Characteristics
Symbol
Quiescent Voltage Output Drift
Through Temperature Range1
∆VOUT(Q)
Sensitivity Drift Due to Package
Hysteresis1
∆SensPKG
Test Conditions
Min.
Typ.
Max.
Units
A1360
–20
–
20
mV
A1361 VOUT(Q) = 2.5 V; Sens = Sens(min)
–20
–
20
mV
A1362
–60
–
60
mV
A1360
A1361 VOUT(Q) = 2.5 V; Sens = Sens(max)
A1362
– 35
–50
–160
–
–
–
35
50
160
mV
mV
mV
–
< ±1
–
%
TA = 25°C, after temperature cycling
See Characteristic Definitions section.
fC varies up to approximately ±20% over the full operating ambient temperature range, TA, and process.
3V
CLP voltages are production-tested, with the sole exception of the A1360 VCLP(HIGH), which is guaranteed by design (the low sensitivity and corresponding high
gauss levels required for testing A1360 VCLP(HIGH) make production testing impractical).
4 Noise is dependent on the sensitivity of the device and the filter capacitance. An 8 mV peak-to-peak noise floor exists that is independent of device sensitivity. This noise
floor attenuates proportionate to the filter capacitance (and device bandwidth).
5 Unit of measure (phase degrees) in reference to the magnetic input signal.
6 High-to-low transition of output voltage is a function of external load components and device sensitivity.
7 Raw device characteristic values before any programming.
8V
OUT(Q)UNIinit typically starts below the lower clamp voltage, VCLP(LOW). When programming the fine quiescent duty cycle for this parameter, several codes may need to be
addressed before VOUT(Q)UNI can be measured above VCLP(LOW).
9 Bits for selecting between V
OUT(Q)UNI and VOUT(Q)BI programming ranges.
10 V
OUT(Q) guaranteed by design.
11 V
OUT(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The VOUT(Q) range is the total range from VOUT(Q)init up to and
including VOUT(Q)(max). See Characteristic Definitions section. Quiescent Voltage Output may drift by an additional ±10 mV over the lifetime of this product.
12 Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
13 Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum specified value of
StepVOUT(Q) or StepSENS.
14 Overall programming value accuracy. See Characteristic Definitions section.
15 Sens guaranteed by design.
16 Sens(max) is the value available with all programming fuses blown (maximum programming code set). Sens range is the total range from Sens
init up to and including
Sens(max). See Characteristic Definitions section. Sensitivity may drift by an additional ±2% over the lifetime of this product.
17 Programmed at 150°C and calculated relative to 25°C.
18 Linearity is only guaranteed for output voltage ranges of ±2 V from the quiescent output for bidirectional devices and +2 V from the quiescent output for unidirectional
devices. These linearity ranges are only valid within the operating output range of the device. The operating output range is confined to the region between the output clamps.
Linearity may shift by up to +/- 1 % over the lifetime of this product.
19 Symmetry error is only valid for bidirectional devices. Symmetry may shift by up to ±1% over the lifetime of this product.
20 Percent change from actual value at V
CC = 5 V, for a given temperature, over the guaranteed supply voltage operating range.
21 Percent change from actual value at V
CC = 5 V, TA = 25°C, over the guaranteed supply voltage operating range.
1
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Thermal Characteristics may require derating at maximum conditions
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
1-layer PCB with copper limited to solder pads
Value
Units
174
ºC/W
*Additional thermal information available on Allegro website.
Power Dissipation versus Ambient Temperature
900
800
600
(R
500
θJ
A
=
17
4
ºC
400
/W
)
Power Dissipation, PD (mW)
700
300
200
100
0
20
40
60
80
100
120
140
Temperature, TA (°C)
160
180
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Characteristic Data
Bandwidth Range
100
Bandwidth, BW (kHz)
BW(max)
10
Guaranteed
Range
1
0.1
0.01
0.1
BW(min)
1
10
100
1000
Capacitance External Capacitor on FILTER Pin, CF (nF)
10,000
Step Response
Sens = 2.2 mV/G
Output (mV)
350 G
Excitation Signal
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
7
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
NoiseNoise
versus
Capacitance
versusFilter
Filter Capacitance
Sens = 6.6 mV/G
50
45
40
Vn(p-p) (mV)
35
30
25
20
15
10
5
0
0
100
200
300
400
500
CF (nF)
Power
On Time
versus Filter
Capacitance
Power On
Time
versus
Filter
Capacitance
Unidirectional Device
Unidirectional Device
180
160
140
120
tPO (µs)
100
B = 300 G
80
60
40
20
0
0
10
20
30
40
50
CF (nF)
Power
On Time
versus Filter
Capacitance
Power On
Time
versus
Filter
Capacitance
Bidirectional Device
Bidirectional
Device
250
200
B = 300 G
150
tPO (µs)
A1360, A1361,
and A1362
B=0G
100
50
0
0
10
20
30
40
50
CF (nF)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Characteristic Definitions
Power-On Time When the supply is ramped to its operating volt-
age, the device requires a finite time to power its internal components before responding to an input magnetic field. Power-On
Time, tPO , is defined as: the time it takes for the output voltage
to settle within ±10% of its steady state value under an applied
magnetic field, after the power supply has reached its minimum
specified operating voltage, VCC(min), as shown in the following
chart.
Rise Time (tr) The time interval between a) when the device
reaches 10% of its full scale value, and b) when it reaches 90%
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the linear device, in which ƒ(–3 dB) =
0.35 / tr. Both tr and tRESPONSE are detrimentally affected by eddy
current losses observed in the conductive IC ground plane.
V
VCC
VCC(typ.)
VOUT
90% VOUT
Applied Magnetic Field
(%)
90
VCC(min.)
t1
t2
tPO
Transducer Output
t1= time at which power supply reaches
minimum specified operating voltage
10
0
Rise Time, tr
t2= time at which output voltage settles
within ±10% of its steady state value
under an applied magnetic field
0
+t
Propagation Delay Time (tpd) The time required for the device
output to reflect a change in the applied magnetic field. Propagation delay can be considered as a fixed time offset and may be
compensated.
Applied Magnetic Field
(%)
t
Response Time (tRESPONSE) The time interval between a) when
the applied magnetic field reaches 90% of its final value, and b)
when the device reaches 90% of its output corresponding to the
applied magnetic field.
Applied Magnetic Field
(%)
90
90
Transducer Output
0
Propagation Delay Time, tpd
Transducer Output
t
0
Response Time, tRESPONSE
t
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115 Northeast Cutoff
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9
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Delay to Clamp A large magnetic input step may cause the clamp
to overshoot its steady state value. The Delay to Clamp, tCLP , is
defined as: the time it takes for the output voltage to settle within
±1% of its steady state value, after initially passing through its
steady state voltage, as shown in the following chart.
Magnetic Input
V
VCLP(HIGH)
VOUT
tCLP
t1
t2
Average Quiescent Voltage Output Step Size The average qui-
escent voltage output step size for a single device is determined
using the following calculation:
VOUT(Q)maxcode –VOUT(Q)init
.
StepVOUT(Q) =
(1)
n–1
2
where:
n is the number of available programming bits in the trim range,
2n–1 is the value of the maximum programming code in the
range, and
VOUT(Q)maxcode is the quiescent voltage output at code 2n–1.
Quiescent Voltage Output Programming Resolution The
programming resolution for any device is half of its programming
step size. Therefore, the typical programming resolution will be:
t1= time at which output voltage initially
reaches steady state clamp voltage
ErrPGVOUT(Q)(typ) = 0.5 × Step
VOUT(Q)(typ)
.
(2)
t2= time at which output voltage settles to
within 1% of steady state clamp voltage
Note: Times apply to both high clamp
(shown) and low clamp.
Due to internal component tolerances and thermal considerations,
the quiescent voltage output, VOUT(Q), may drift from its nominal
value over the operating ambient temperature, TA. For purposes
of specification, the Quiescent Voltage Output Drift Through
Temperature Range, ∆VOUT(Q) (mV), is defined as:
0
t
Quiescent Voltage Output In the quiescent state (no significant
magnetic field: B = 0 G), the output, VOUT(Q), has a constant ratio
to the supply voltage, VCC, throughout the entire operating ranges
of VCC and ambient temperature, TA.
Guaranteed Quiescent Voltage Output Range The quiescent
voltage output, VOUT(Q), can be programmed around its nominal
value of 2.5 V, within the guaranteed quiescent voltage range
limits: VOUT(Q)(min) and VOUT(Q)(max). The available guaranteed
programming range for VOUT(Q) falls within the distributions of
the initial, VOUT(Q)init, and the maximum programming code for
setting VOUT(Q), as shown in the following diagram.
VOUT(Q)init(typ)
Guaranteed Output
Programming
Range, VOUT(Q)
Distribution for
VOUT(Q)init
∆VOUT(Q) = VOUT(Q)(TA) –VOUT(Q)(25°C)
VOUT(Q)(max)
.
(3)
VOUT(Q), should be calculated using the actual measured values
of VOUT(Q)(TA) and VOUT(Q)(25°C) , rather than programming target
values.
Sensitivity The presence of a south polarity magnetic field, perpendicular to the branded surface of the package face, increases
the output voltage from its quiescent value toward the supply
voltage rail. The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely,
the application of a north polarity field decreases the output
voltage from its quiescent value. This proportionality is specified
as the magnetic sensitivity, Sens (mV/G), of the device, and it is
defined for bipolar devices as:
Sens =
Distribution for
Max Code VOUT(Q)
VOUT(Q)(min)
Quiescent Voltage Output Drift Through Temperature Range
VOUT(BPOS) – VOUT(BNEG)
BPOS – BNEG
and for unipolar devices as:
,
(4)
VOUT(BPOS) – VOUT(Q)
,
(5)
BPOS
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Sens =
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A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Guaranteed Sensitivity Range The magnetic sensitivity, Sens,
can be programmed around its nominal value, 0.7 to 16 mV/G
depending on device type, within the sensitivity range limits:
Sens(min) and Sens(max). Refer to the Guaranteed Quiescent
Voltage Output Range section for a conceptual explanation of
how value distributions and ranges are related.
Average Sensitivity Step Size Refer to the Average Quiescent
Voltage Output Step Size section for a conceptual explanation.
Sensitivity Programming Resolution Refer to the Quiescent
where Sens(25°C)1 is the programmed value of sensitivity at TA = 25°C, and Sens(25°C)2 is the value of sensitivity at
TA = 25°C, after temperature cycling TA up to 150°C, down to
–40°C, and back to up 25°C.
Linearity Sensitivity Error The 136x family is designed to
provide a linear output in response to a ramping applied magnetic
field. Consider two magnetic fields, B1 and B2. Ideally, the sen-
Voltage Output Programming Resolution section for a conceptual
explanation.
sitivity of a device is the same for both fields, for a given supply
Sensitivity Temperature Coefficient Device sensitivity changes
difference between the sensitivities measured at B1 and B2.
as temperature changes, with respect to its programmed sensitivity temperature coefficient, TCSENS. TCSENS is programmed at
150°C, and calculated relative to the nominal sensitivity programming temperature of 25°C. TCSENS (%/°C) is defined as:
SensT2 – SensT1
 1 
 ,
TCSens = 
100% 
(6)
×
SensT1

 T2–T1
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
ideal value of Sens over the full ambient temperature range,
SensEXPECTED(TA), is defined as:
SensEXPECTED(TA) = SensT1 [1 + TCSENS (TA –T1) / 100%] (7)
.
SensEXPECTED(TA) should be calculated using the actual measured
values of SensT1 and TCSENS rather than programming target
values.
Sensitivity Drift Due to Package Hysteresis Package stress and
relaxation can cause the device sensitivity at TA = 25°C to change
during and after temperature cycling.
For purposes of specification, the sensitivity drift due to package
hysteresis, ∆SensPKG, is defined as:
∆SensPKG =
Sens(25°C)2 – Sens(25°C)1
× 100%
Sens(25°C)1
,
(8)
voltage and temperature. Linearity error is present when there is a
Linearity Error is calculated separately for the positive
(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
Linearity error (%) is measured and defined as:
 SensBPOS2 
 × 100%
LinERRPOS = 1–
 SensBPOS1 
,
 SensBNEG2
 × 100%
LinERRNEG = 1–
 SensBNEG1
,
(9)
where:
SensBx =
|VOUT(Bx) – VOUT(Q)|
Bx
,
(10)
and BPOSx and BNEGx are positive and negative magnetic fields,
with respect to the quiescent voltage output such that
|BPOS2| = 2 ×|BPOS1| and |BNEG2| = 2 ×|BNEG1|. Then:
LinERR = max( LinERRPOS , LinERRNEG)
.
(11)
Note that unipolar devices only have positive linearity error,
LinERRPOS.
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A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Symmetry Sensitivity Error The magnetic sensitivity of an
A136x device is constant for any two applied magnetic fields of
equal magnitude and opposite polarities.
Symmetry error, SymERR (%), is measured and defined as:
 SensBPOS
SymERR = 1–
 SensBNEG

 × 100%

,
(12)
where SensBx is as defined in equation 4, and BPOS and BNEG are
positive and negative magnetic fields such that |BPOS| = |BNEG|.
Note that the symmetry error specification is only valid for bipolar
devices.
Ratiometry Error The A136x devices feature ratiometric output.
This means that the quiescent voltage output, VOUT(Q) , magnetic
sensitivity, Sens, and clamp voltage, VCLP(HIGH) and VCLP(LOW),
are proportional to the supply voltage, VCC. In other words, when
the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same
percentage. Error is the difference between the measured change
in the supply voltage relative to 5 V, and the measured change in
each characteristic.
The ratiometric error in quiescent voltage output, RatERRVOUT(Q)
(%), for a given supply voltage, VCC, is defined as:
 VOUT(Q)(VCC) / VOUT(Q)(5V) 
 × 100% . (13)
RatERRVOUT(Q) = 1–
VCC / 5 V


The ratiometric error in magnetic sensitivity, RatERRSENS (%), for
a given supply voltage, VCC, is defined as:
 Sens(VCC) / Sens(5V) 
 × 100%
RatERRSENS = 1–
VCC / 5 V


. (14)
The ratiometric error in the clamp voltages, RatERRCLP (%), for a
given supply voltage, VCC, is defined as:
 VCLP(VCC) / VCLP(5V) 
 × 100%
RatERRCLP = 1–
VCC / 5 V


,
where VCLP is either VCLP(HIGH) or VCLP(LOW).
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(15)
12
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Typical Application Drawing
V+
VCC
VOUT
A136x
FILTER
CBYPASS
0.1 µF
CL
GND
CFILTER
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall device. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified operating temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of the output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulationdemodulation process.
The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the dc offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated dc offset is
suppressed. The chopper stabilization technique uses a 210 kHz
high frequency clock.
For demodulation process, a sample and hold technique is used,
where the sampling is performed at twice the chopper frequency
(420 kHz). This high-frequency operation allows a greater
sampling rate, which results in higher accuracy and faster signalprocessing capability. This approach desensitizes the chip to the
effects of thermal and mechanical stresses, and produces devices
that have extremely stable quiescent Hall output voltages and
precise recoverability after temperature cycling. This technique
is made possible through the use of a BiCMOS process, which
allows the use of low-offset, low-noise amplifiers in combination
with high-density logic integration and sample-and-hold circuits.
Regulator
Hall Element
Amp
Sample and
Hold
Clock/Logic
Low-Pass
Filter
Concept of Chopper Stabilization Technique
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A1360, A1361,
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Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Programming Guidelines
Overview
for that kit is available for download free of charge, and provides
additional information on programming these devices.
Programming is accomplished by sending a series of input voltage pulses serially through the VOUT pin of the device. A unique Definition of Terms
combination of different voltage level pulses controls the internal
programming logic of the device to select a desired programmable Register One of several sections of the programming logic that
control the bit fields storing the code choices for setting programparameter and change its value.
ming modes and programmable parameters.
There are three voltage levels that must be taken into account
Bit Field The set of internal fuses controlled by a single register.
when programming. These levels are referred to as high,
Each fuse in a bit field represents a binary digit in the code setting
VP(HIGH), mid, VP(MID), and low, VP(LOW). There are two programfor that register. The internal logic of the device interprets that
ming pulse levels. A high voltage pulse, VPH, refers to a VP(LOW)
code and applies the result to a programmable parameter of the
–VP(HIGH) –VP(LOW) sequence. A mid voltage pulse, VPM, refers
device. Individual fuses can be temporarily activated for testing of
to a VP(LOW) –VP(MID) –VP(LOW) sequence.
the result, or permanently blown.
The 136x features four modes used during programming: Hold
mode, Try mode, Blow mode, and Lock mode:
•In Hold mode, the value of two programmable parameters may
be set and measured simultaneously. The parameter values are
stored temporarily, and reset after cycling the supply voltage.
•In Try mode, the value of a single programmable parameter may
be set and measured. The parameter value is stored temporarily,
and resets after cycling the supply voltage. (Note that other
parameters cannot be accessed simultaneously in this mode.)
•In Blow mode, the value of a single programmable parameter
may be set permanently by blowing solid-state fuses internal to
the device. Additional parameters may be blown sequentially.
•In Lock mode, a device-level fuse is blown, blocking the further
programming of all parameters.
The programming sequence is designed to help prevent the device
from being programmed accidentally; for example, as a result of
noise on the supply line. Any programmable variable power supply can be used to generate the pulse waveforms, although Allegro
highly recommends using the Allegro Sensor IC Evaluation Kit,
available on the Allegro Web site On-line Store. The manual
Key A series of one or more consecutive mid voltage pulses that
indicate by their quantity the register being addressed. The quantity of mid voltage pulses corresponds to the decimal equivalent
of the binary value of the register being addressed. For example,
the LSB of a zone is bit 0 (binary 0), corresponding to register 1,
and indicated by key 1 (decimal 1), a single mid voltage pulse.
Code A series of one or more consecutive mid voltage pulses that
indicate by their quantity the combination of fuses to be activated
or blown in the currently-selected register. The quantity of pulses
in the code corresponds to the decimal equivalent of the binary
value of the bits (links) to be activated or blown. The LSB of a bit
field is bit 0, activated by code 1 (decimal 1), a single mid voltage
pulse.
Addressing Indicating the target register or bit field setting by
incrementing the key or code by means of pulse trains of consecutive mid voltage pulses transmitted through the VOUT pin of the
device. During the addressing process, each parameter can be
measured, before either blowing the fuses to permanently set the
programming code (and parameter value), or cycling the power to
reset the unblown bits.
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14
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Zone The 136x programming logic is designed to accept up to
two different key-code combinations sequentially without cycling
the supply. The first key-code combination is interpreted as
addressing a register in the first zone, and the second key-code
combination is interpreted as addressing a register in the second
zone. All of the parameter registers are located in either the first
or second zone. The first zone must be entered and exited before
the parameter registers available in the second zone may be
accessed.
internal to the device. After a bit (fuse) has been blown, it cannot
be reset.
Blow Pulse A high voltage pulse of sufficient duration to blow the
addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Fuse Blowing Applying a high voltage pulse of sufficient duration to permanently set an addressed bit by blowing a fuse
Programming Pulse Requirements, protocol at TA = 25°C
Characteristic
Symbol
Notes
Min.
Typ.
Max.
Units
–
–
5.5
V
14
15
16
V
26
27
28
V
IP
Minimum supply current required to ensure proper
fuse blowing. In addition, a minimum capacitance,
CBLOW = 0.1 µF, must be connected between the
VOUT and GND pins during programming, to provide
the current necessary for fuse blowing.
300
–
–
mA
tLOW
Duration of VP(LOW) voltage level for separating
VP(MID) and VP(HIGH) pulses, and delay time after the
final VBLOW pulse.
40
–
–
µs
tACTIVE
Duration of VP(MID) and VP(HIGH) pulses for register
selection or bit field addressing.
40
–
–
µs
tBLOW
Duration of VP(HIGH) pulses for fuse blowing.
40
–
–
µs
5
–
100
µs
5
–
100
µs
VP(LOW)
Programming Voltage
VP(MID)
Measured at the VOUT pin.
VP(HIGH)
Programming Current
Pulse Width
Pulse Rise Time
tPr
Rise time required for transitions from VP(LOW) to
either VP(MID) or VP(HIGH).
Pulse Fall Time
tPf
Fall time required for transitions from VP(HIGH) or
VP(MID) to VP(LOW).
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A1360, A1361,
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Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Programming Procedures
VP(MID)
VP(HIGH)
VP(LOW)
VP(MID)
0
VP(LOW)
tLOW
0
tACTIVE
Figure 1. Voltage pulse sequence required to select the first
programmable register in the first zone.
After the falling edge of the second VPH pulse, the bit field of the
selected register may be addressed with the appropriate code (see
Bit Field Addressing section, below).
The first zone must be traversed before the second zone can be
accessed. After completing any bit field addressing in the first
zone, to enter the second zone, apply a third VPH pulse. As in
the first zone, this must be followed by the key for the parameter
register, then a VPH pulse and the bit field code (with no VCC
supply interruptions).
Bit Field Addressing
After the register of a programmable parameter has been selected
as described above, the code pulses must be applied serially to
tACTIVE
Code 2n
V+
Code 2n –1
V+
Code 2n –2
To select the register in the first zone, a sequence of one VPH
pulse, the key for the register, and a second VPH pulse (with no
VCC supply interruptions) must be applied serially to the VOUT
pin. The pulse train used for selection of the first register, key 1,
is shown in figure 1.
Addressing activates the corresponding fuse locations in the
given bit field by incrementing the binary value of an internal
DAC. Measurements can be taken after each pulse to determine
if the desired result for the programmable parameter has been
reached. Cycling the supply voltage resets all the locations in the
bit field that have unblown fuses to their initial states.
Code 3
Zone 1, Register 1:
•Fine sensitivity, Sens
Zone 2, Register 1:
•Fine quiescent voltage output, VOUT(Q)
Zone 2, Register 2:
•Coarse quiescent voltage output, VOUT(Q)
•Overall device locking, LOCK
the VOUT pin with no VCC supply interruptions. As each additional pulse in the code is transmitted, the overall setting of the
bit field increments by 1, up to the maximum possible code for
that register (see the Programming Logic table). The A136x logic
interprets the overall setting (the binary sum of all of the activated or blown fuses) and applies it to the value of the parameter,
according to the step size for the parameter (shown in the Electrical Characteristics table).
Code 2
Each of the four programmable parameters can be accessed
through its corresponding parameter register. These registers are
located in two distinct zones in the A136x devices:
Code 1
Parameter Selection
tLOW
Figure 2. Bit field addressing pulse train. Addressing the bit field by incrementing the code causes the programmable parameter value to change.
The number of bits available for a given programming code, n, varies
among parameters; for example, the bit field for Sensitivity has 8 bits available, which allows 255 separate codes to be used.
Fuse Blowing
After the required code is found for a given parameter, its value
can be set permanently by blowing individual fuses in the appropriate register bit field. Blowing is accomplished by applying a
high voltage pulse, called a blow pulse, of sufficient duration to
permanently set an addressed bit by blowing a fuse internal to the
device. Due to power requirements, the fuse for each bit in the
bit field must be blown individually. To accomplish this, the code
representing the desired parameter value must be translated to a
binary number. For example, as shown in figure 3, decimal code
5 is equivalent to the binary number 101. Therefore bit 2 (code
4) must be addressed and blown, the device power supply cycled,
and then bit 0 (code 1) addressed and blown. The order of blowing bits, however, is not important. Blowing bit 0 first, and then
bit 2, is acceptable.
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A1360, A1361,
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Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
Code in Binary
(Binary)
1 0 1
Fuse Blowing
Target Bits
Fuse Blowing
Address Code Format
Bit 2
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
Bit 0
Code 4
Code 1
(Decimal Equivalents)
Figure 3. Example of code 5 broken into its binary components,
equaling code 4 and code 1.
•A 0.1 μF blowing capacitor, CBLOW, must be mounted between
the VOUT pin and the GND pin during programming, to ensure
enough current is available to blow fuses.
•The CBLOW blowing capacitor must be replaced in the final
application with a suitable CL. (The maximum load capacitance
is 10 nF for proper operation.) The power supply used for
Note: After blowing, the programming is not reversible, even
programming must be capable of delivering at least 26 V and
after cycling the supply power. Although a register bit field fuse
300 mA. Be careful to observe the tLOW delay time before
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
powering down the device after blowing each bit.
•The following programming order is recommended:
1.Coarse VOUT(Q)
2.Sens
Locking the Device
3.VOUT(Q)
After the desired code for each parameter is programmed, the
4.LOCK (only after all other parameters have been
device can be locked to prevent further programming of any
programmed and validated, because this prevents any further
parameters. See the Lock Mode section for lock pulse sequence.
programming of the device)
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A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Programming Modes
Hold Mode
Hold mode allows multiple programmable parameters to be
tested simultaneously without permanently setting any values.
With the 136x programming logic, only two parameters located
in different zones can be addressed together. For example, only
the sensitivity and fine quiescent voltage offset parameters can be
temporarily set and tested simultaneously without permanently
setting their values. For unidirectional devices, the unidirectional
bit must be permanently blown before using the Hold Mode to
temporarily set and test the sensitivity and fine quiescent voltage
offset.
Powering the VCC supply automatically causes the device to
enter the first zone. Applying a high pulse, mid pulse, high pulse
sequence selects the Sensitivity register. The sensitivity can be set
to the desired value by applying the appropriate code pulses.
The next high-level pulse transitions the programming logic into
the second zone. Applying one mid level pulse causes the logic
to enter the Fine Quiescent Voltage Output register, and another
high-level pulse causes the logic to enter the Fine Quiescent
Voltage Output bit field. The fine quiescent voltage output can
be set to the desired level by applying the appropriate number of
mid-level pulses to the VOUT pin. (See figure 4.)
The addressed parameter values will be stored in the device logic
even after the programming drive voltage is removed from the
VOUT pin, allowing the output to be measured at any time during the programming process.
Figure 4. Hold sequence for testing Sens and VOUT(Q) parameters
together.
After addressing and measuring the device output, cycle the supply to reset all of the register values. Registers can be addressed
and re-addressed an indefinite number of times. Once the final
desired code is found for each register, cycle the supply and blow
the bit field using Blow mode.
Note: For accurate time measurements, the blow capacitor,
CBLOW, should be removed during output voltage measurement.
Also note that both the Sensitivity and Fine Quiescent Voltage
Output registers should not be blown simultaneously. See the
Blow Mode section for additional information.
Try Mode
Try mode allows a single programmable parameter to be tested
without permanently setting its value. Try mode is a required step
of parameter blowing. (See the Blow Mode section for additional
information.) To select a parameter register in the first zone,
power the supply and enter the appropriate key-code pulse combination (see figure 5). To select a parameter register in the second zone, power the supply and apply two high voltage pulses,
followed by the appropriate key-code pulse combination (see
Figure 6). When addressing the bit field, each VPM pulse increments the value of the parameter register, up to the maximum
possible code (see the Programming Logic table). The addressed
parameter value is stored in the device even after the programming drive voltage is removed from the VOUT pin, allowing its
value to be measured.
Note: For accurate time measurements, the blow capacitor,
CBLOW, should be removed during output voltage measurement.
To reset the bit field, and thus the value of the programmable
parameter, cycle the VCC supply voltage.
Figure 5. Pulses to enter Try mode, zone 1. Example shown is for
addressing the Sensitivity register. After addressing desired code,
cycle the supply to reset the bit field or apply a blow pulse to make the
parameter value permanent.
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A1360, A1361,
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Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
zone, enter the appropriate key-code combination and then apply
a single blow pulse on the VOUT pin. This is diagrammed as
follows:
Zone 1: VPH → Key → VPH → Code for Single Bit → VPH →
VPH → VPH
Zone 2: VPH → VPH → VPH → Key → VPH → Code for
Single Bit → VPH
Figure 6. Pulses to enter Try mode, zone 2. Example shown is
for addressing the Fine Quiescent Voltage Output register. After
addressing desired code, cycle the supply to reset the bit field or apply
a blow pulse to make the parameter value permanent.
Note: During a single blowing sequence, only one programmable
parameter in a single zone should be set at a time. After each
blow sequence the supply should be cycled before attempting to
blow additional bits.
Blow Mode
Lock Mode
After the required value of the programmable parameter is
addressed using Try mode, its corresponding code can be blown
to make its value permanent. To do this, select the required
parameter register and the appropriate code. (See the Fuse Blowing section. Recall that each bit of a desired code must be blown
individually before cycling the supply.) If the desired parameter
is in the first zone, enter the appropriate key-code combination
and then apply two high-level voltage pulses followed by an
additional blow pulse. If the desired parameter is in the second
To lock the device, address the LOCK bit and apply a blow pulse
with CBLOW in place. The LOCK bit is located in zone 2, register
2, code 4. After locking the device, no future programming of any
parameter is possible.
The lock sequence is:
VPH → VPH → VPH → VPM → VPM →VPH → VPM → VPM
→ VPM → VPM → VPH
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A1360, A1361,
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Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Programming State Machine
Initial State
After system power-up, the programming logic is reset to a
known state. This is referred to as the Initial state. All the bit field
locations that have intact fuses are set to logic 0. While in the Initial state, any VPM pulses on the VOUT pin are ignored. To enter
the zone 1 Parameter Selection state, apply a single VPH pulse on
VOUT pin. To enter the zone 2 Parameter Selection state, apply a
sequence of three VPH pulses on the VOUT pin.
Parameter Selection State
This state allows the selection of the parameter register containing the bit fields to be programmed. To select a parameter register
within the chosen zone, increment through the keys by sending
VPM pulses on the VOUT pin. Register keys select among the following programming parameters in zone 1:
1 pulse – Sens,
and the following programming parameters in zone 2:
1 pulse – VOUT(Q)
2 pulses – Coarse VOUT(Q) and LOCK
To enter the Bit Field Addressing state, send one VPH pulse on the
VOUT pin.
Note: When parameter selection for zone 1 is bypassed (by sending a second VPH pulse) no register is selected, and VPM pulses
are ignored until after the VPH pulse is sent to enter zone 2.
Bit Field Addressing State
This state allows the selection of the individual bit fields to be
programmed in the selected parameter register (see the Programming Logic table). To leave this state, either cycle device power
or blow the fuses for the selected code.
Note: Merely addressing the bit field does not permanently set
the value of the selected programming parameter; fuses must be
blown to do so.
Fuse Blowing State
To blow an addressed bit field, apply a VPH pulse on the VOUT
pin. Power to the device should then be cycled before additional
programming is attempted.
Note: Each bit representing a decimal code must be blown individually (see the Fuse Blowing section).
VPM = VP(LOW) → VP(MID) → VP(LOW)
Power-up
Initial
VPH = VP(LOW) → VP(HIGH) → VP(LOW)
VPM
VPH
Parameter Selection
(Zone 1)
[Key sequence] VPM
VPH
VPM
VPH
Sens
VPM
VPM
VPH
VPH
2
or Lock
VPH
VPH
Bit Field Addressing
VPH
[Code sequence]
1
VPM [Key sequence]
V
Coarse VPM
VOUT(Q) PM V
OUT(Q)
(Fine)
VPH
Bit Field Addressing
User Power-down
Required
Parameter Selection
(Zone 2)
VPM
2n
–1
n= bits in
register
VPH
VPH
VPM
VPM
1
VPM
[Code sequence]
VPM
2n – 1 VPM
n= bits in
2
register
VPH
VPH
VPH
Fuse Blowing
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Programming Logic Table
Programmable Parameter
Bit Field Address
Zone
Register Selection
(Key)
Binary Format
(MSB → LSB)
Decimal
Equivalent Code
1
Sens
(1)
00000000
0
Initial value (Sensinit)
11111111
255
00000000
0
11111111
255
Maximum value of fine VOUT(Q) in range for selected
bidirectional or unidirectional device
Coarse VOUT(Q)
(2)
00000001
1
Switch from default bidirectional (VOUT(Q)BI) device to
(VOUT(Q)UNI) device
LOCK
(2)
00000100
4
LOCK bit, enables permanent locking of all programming
bit fields in the device
VOUT(Q)
(1)
2
Description
Maximum value of sensitivity (Sens) in range
Initial value for selected programming region (VOUT(Q)init)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Constructing a Current Sensor Using the A136x
To construct a current sensor using the A136x, first consider a
current carrying wire that we want to observe. As dictated by
Ampere’s Law, a magnetic field is produced around the wire
that is proportional to the amount of current flowing through
the wire. By passing this wire through a soft magnetic core, the
magnetic flux produced by the wire can be concentrated and
directed through a gap in the core. The magnetic flux density can
be measured by inserting the A136x SIP into the gap in the core.
As a result, the output of the A136x device will be proportional
to the amount of current flowing through the wire.
The example feedthrough current sensing setup shown below
(figure 7) has a core made of “mu metal” that is 2 mm thick
and 4 mm wide. The inner radius of the core is 14.5 mm and
the outer radius is 18.5 mm. The wire going through the center
of the core has a radius of 9 mm. Using this setup with a gap of
1.7 mm, a field strength results that is on the order of 7 G / A at
the Hall element in the A136x.
The recommended core material for construction of the concentrator depends on the specific application. If high flux saturation
is desired, then an alloy such as HyPerm49 is recommended.
For lower-current level sensing applications, a material such as
HyMu80 may be desired. (HyMu80 has lower magnetic flux
saturation than HyPerm49, therefore more HyMu80 material is required to carry the same amount of flux compared
to Hyperm49.) If frequency response is a concern, then eddy
currents can be reduced by either laminating the HyPerm49 or
HyMu80 alloys, or by using a ferrite core.
Application-specific housing
Ø18 mm
Ring concentrator
4 mm
Current-conducting wire
1.7 mm
2 mm
Ø37 mm
A136x
Center Hall element in gap
Figure 7. The example current sensor setup used to generate the data in this section was
constructed with a split-ring concentrator and an A136x device. A copper wire was fed
through the concentrator, and the A136x placed in its gap. This approximates a typical
ammeter application on a thick wire, such as shown in the left view. Note that such
applications usually have a protective housing, which should be taken into consideration
when designing the final application. The housing is beyond the scope of this example.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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22
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
The flux density measured by the A136x SIP is related to the
Flux Density per Ampere vs. Gap for a Feedthrough Sensor
size of the gap cut into the core. The larger the gap in the core,
G/A at the Gap Center
14
the smaller the flux density per ampere of applied current (see
12
figure 8).
10
8
Figure 9 depicts the magnetic flux density through the center of
6
the SIP as a function of SIP to core alignment. Note that a core
4
with a larger cross-sectional area would reduce the attenuation
2
in flux density that results from any SIP misalignment. The flat
0
0.5
1
1.5
2
2.5
3
3.5
Gap (mm)
portion of the curve in figure 9 would span a larger distance in
millimeters if the cross-sectional area of the core were increased.
Figure 8. The flux density per ampere measured by the A136x Hall sensor IC is related to the core gap, as shown. This figure assumes that the
current sensing application is constructed using the example setup.
7.0
Interior side of
Concentrator
6.5
Ring concentrator
Exterior side of
Concentrator
Wire
Measurement plane
(midplane of gap)
Magnetic Flux Intensity, B (G)
6.0
Magnetic flux in gap
5.5
5.0
4.5
4.0
3.5
3.0
+B
–2.0
–2
0
mm
2
–1.0
0
1.0
2.0
Radial Displacement from Concentrator Centerline (mm)
Figure 9. Side view of example current-conducting wire and split ring concentrator (left), and
magnetic profile (right) through the midplane of the gap in the split ring concentrator. The flux
denisty through the center of the gap varies between the inside and the outside of the gap.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Improving Sensing System Accuracy Using the FILTER Pin
In low-frequency sensing applications, it is often advantageous
to add a simple RC filter to the output of the sensor IC. Such a
low-pass filter improves the signal-to-noise ratio, and therefore
the resolution, of the device output signal. However, the addition
of an RC filter to the output of a sensor IC can result in undesirable device output attenuation — even for DC signals.
Signal attenuation, ∆VATT , is a result of the resistive divider
effect between the resistance of the external filter, REXT (see figure 10), and the input impedance and resistance of the customer
interface circuit, RINTFC. The transfer function of this resistive
divider is given by:
∆VATT = VOUT
 RINTFC 


 REXT + RINTFC 
.
(16)
Even if REXT and RINTFC are designed to match, the two individual resistance values will most likely drift by different amounts
over temperature. Therefore, signal attenuation will vary as a
function of temperature. Note that the input impedance, RINTFC ,
of commonly available analog-to-digital converters (ADC) can
be as low as 10 kΩ.
The A136x contains an internal resistor with buffer amplifier that
can be connected via the FILTER pin to the PCB. With this circuit architecture, users can implement a simple RC filter via the
addition of a capacitor, CFILTER (see figure 11) from the FILTER
pin to ground. The buffer amplifier inside of the A136x (located
after the internal resistor and FILTER pin connection) eliminates
the attenuation caused by the resistive divider effect described in
equation 16. Therefore, the A136x device is ideal for use in highaccuracy applications that require a large signal-to-noise ratio
and cannot afford the signal attenuation associated with the use
of an external RC low-pass filter.
V+
VCC
Amp
CBYPASS
0.01 µF
Filter
Low Pass Filter
Dynamic Offset
Cancellation
Figure 10. When a low pass filter is constructed externally
to a standard Hall effect device, a resistive divider may
exist between the filter resistor, REXT, and the application
load resistance, RINTFC. This resistive divider (shaded
area) will cause excessive attenuation, as given by the
transfer function shown in equation 16.
Standard Hall Effect Device
Out
VOUT
Resistive Divider
REXT
Gain
CEXT
Offset
Application
Interface
Circuit
RINTFC
Trim
Control
GND
V+
Allegro A136x
VCC
Ratiometric
Hall Drive
CBYPASS
0.01 µF
Programming
Logic
Sens TC Trim
Sensitivity Trim
8 Bits
(Factory
Programmed)
(Customer
Programmed)
Dynamic Offset
Cancellation
Figure 11. The FILTER pin provided
on the A136x device allows separate
control of SNR, avoiding the attenuation effects from the standard resistor
divider solution, shown in figure 10.
FILTER
Program/Lock
CFILTER
VOUT(Q)
8 Fine Bits
1 Coarse Bit
(Customer
Programmed)
+
Signal Recovery
–
Buffer Amplifier
and Resistor
+
–
VOUT
Application
Interface
Circuit
RINTFC
GND
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
24
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Package KT, 4-Pin SIP
+0.08
5.21 –0.05
B
10°
E
F
2.60
+0.08
1.00 –0.05
1.08 F
+0.08
3.43 –0.05
Mold Ejector
Pin Indent
F
NNNN
Branded
Face
A
0.89
MAX
YYWW
0.54
REF
1
C
Standard Branding Reference View
N = Device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
12.14±0.05
+0.08
0.41 –0.05
For Reference Only; not for tooling use (reference DWG-9202)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.08
0.20 –0.05
0.89
MAX
1
2
3
0.54
REF
4
+0.08
1.50 –0.05
Dambar removal protrusion (16X)
B
Gate and tie bar burr area
C
Branding scale and appearance at supplier discretion
D Thermoplastic Molded Lead Bar for alignment during shipment
D
1.27 NOM
A
E
Active Area Depth 0.37 mm REF
F
Hall element, not to scale
+0.08
1.00 –0.05
+0.08
5.21 –0.05
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
25
A1360, A1361,
and A1362
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Revision History
Revision
Revision Date
Description of Revision
4
December 3, 2013
Update product availability
5
December 1, 2015
Updated status of product to “Last Time Buy”
Copyright ©2008-2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
26
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