Data Sheet

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK9516-55A
BUK9616-55A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
VGS = 10 V
MAX.
UNIT
55
66
138
175
V
A
W
˚C
16
15
mΩ
mΩ
PINNING
TO220AB & SOT404
PIN
PIN CONFIGURATION
SYMBOL
DESCRIPTION
1
gate
2
drain
3
source
d
tab
mb
g
2
1
tab/mb drain
3
SOT404
BUK9616-55A
1 2 3
TO220AB
BUK9516-55A
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
RGS = 20 kΩ
tp≤50µS
-
55
55
10
15
V
V
V
V
ID
ID
IDM
Ptot
Tstg, Tj
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
66
46
263
138
175
A
A
A
W
˚C
TYP.
MAX.
UNIT
-
1.1
K/W
in free air
60
-
K/W
Minimum footprint, FR4
board
50
-
K/W
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
-
Rth j-a
Rth j-a
May 2000
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 55 V; VGS = 0 V;
IGSS
RDS(ON)
Gate source leakage current
Drain-source on-state
resistance
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A
Tj = 175˚C
Tj = 175˚C
VGS = 10 V; ID = 25 A
VGS = 4.5 V; ID = 25 A
MIN.
TYP.
MAX.
UNIT
55
50
1
0.5
-
1.5
0.05
2
12.5
10
-
2.0
2.3
10
500
100
16
32
15
17
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
2314
347
243
3085
416
333
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; Rload =1.2Ω;
VGS = 5 V; RG = 10 Ω
-
45
130
400
130
68
195
560
182
ns
ns
ns
ns
Ld
Internal drain inductance
-
4.5
-
nH
Ld
Internal drain inductance
-
3.5
-
nH
Ld
Internal drain inductance
-
2.5
-
nH
Ls
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from contact screw on
tab to centre of die(TO220AB)
Measured from upper edge of drain
tab to centre of die(SOT404)
Measured from source lead to
source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
-
-
66
A
IF = 25 A; VGS = 0 V
IF = 66 A; VGS = 0 V
-
0.85
1.1
263
1.2
-
A
V
V
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
51
102
164
126
ns
nC
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
May 2000
CONDITIONS
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 49 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
120
Normalised Power Derating
PD%
MIN.
TYP.
MAX.
UNIT
-
-
120
mJ
ID / A
1000
110
RDS(on) = VDS/ID
100
tp =
90
10 us
80
100
70
100 us
60
50
1 ms
D.C.
40
10
30
10 ms
20
100 ms
10
0
0
20
40
60
80
100
Tmb / C
120
140
160
1
180
1
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
VDS / V
100
1000
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
10
10
Zth / (K/W)
110
D=
100
1
90
0.5
80
0.2
70
0.1
0.1
60
0.05
D=
PD
50
tp
T
tp
0.02
40
0.01
30
0
20
T
t
10
0.001
0.000001
0
0
20
40
60
80
100
Tmb / C
120
140
160
180
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
May 2000
0.0001
0.01
VDS / V
1
100
10000
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
ID/A
100
ID/A
100
10.0
6.0
5.0
4.0
VGS / V =
3.6
80
80
3.4
3.2
60
60
3.0
40
40
2.8
2.6
20
25
20
2.4
Tj / C= 175
2.2
0
0
0
2
4
VDS/V
6
8
10
0
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
22
1
2
VGS / V 3
4
5
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
gfs / S
RDS(ON) / mOhm
60
3.4
VGS / V =
3.6
20
50
4.0
18
40
4.2
16
4.6
14
5.0
30
20
12
10
10
20
30
40
50
60
ID / A
70
80
90
0
100
0
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
20
40
ID / A
60
80
100
Fig.9. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
RDS(ON) / mOhm
2.5
35
30
Rds(on) normlised to 25degC
2
25
1.5
20
1
15
10
2
3
4
5
6
7
8
9
0.5
-100
10
VGS / V
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VGS); conditions ID = 25 A;
May 2000
-50
0
50
Tmb / degC
100
150
200
Fig.10. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
5
VGS(TO) / V
BUK9516-55A
BUK9616-55A
BUK759-60
6
max.
VGS / V
5
4
VDS= 14V
typ.
4
3
3
min.
VDS= 44V
2
2
1
1
0
0
-100
-50
0
50
Tj / C
100
150
0
200
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
20
30
QG / nC
40
50
60
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
Sub-Threshold Conduction
1E-01
10
120
IF / A
100
1E-02
80
2%
1E-03
typ
98%
60
Tj / ˚C =
175
40
1E-04
20
25
1E-05
0
1E-06
0.0
0
1
2
3
4
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
0.4
0.6
0.8
VSDS/V
1.0
1.2
1.4
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
120
6.0
0.2
5
Thousands / pF
WDSS%
110
100
90
5.0
80
4.0
70
60
Ciss
3.0
50
40
2.0
Coss
30
1.0
20
Crss
0.0
0.01
10
0
0.1
1
VDS/V
10
100
20
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
May 2000
40
60
80
100
120
Tmb / C
140
160
180
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
+
VDD
+
VDD
RD
L
VDS
VDS
-
VGS
-
VGS
-ID/100
T.U.T.
0
RGS
0
T.U.T.
R 01
shunt
Fig.17. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
May 2000
RG
Fig.18. Switching test circuit.
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
E
SOT78
A
A1
P
q
D1
D
L1
L2(1)
Q
b1
L
1
2
e
e
3
b
c
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
c
D
D1
E
e
L
L1
L2
max.
P
q
Q
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
TO-220
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-06-11
Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
May 2000
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
OUTLINE
VERSION
D
max.
D1
E
11
1.60
1.20
10.30
9.70
e
Lp
HD
Q
2.54
2.90
2.10
15.40
14.80
2.60
2.20
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT404
Fig.20. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
May 2000
8
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9516-55A
BUK9616-55A
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.21. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
May 2000
9
Rev 1.000
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