Data Sheet

D2
PA
K
BUK961R6-40E
N-channel TrenchMOS logic level FET
Rev. 2 — 16 May 2012
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in a SOT404 package using TrenchMOS technology. This
product has been designed and qualified to AEC Q101 standard for use in high
performance automotive applications.
1.2 Features and benefits
 AEC Q101 compliant
 Repetitive avalanche rated
 Suitable for thermally demanding
environments due to 175 °C rating
 True logic level gate with Vgst(th)
rating of greater than 0.5V at 175 °C
1.3 Applications
 12 V Automotive systems
 Transmission control
 Motors, lamps and solenoid control
 Ultra high performance power
switching
 Start-Stop micro-hybrid applications
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
ID
drain current
VGS = 5 V; Tmb = 25 °C; see Figure 1
Ptot
total power dissipation
Conditions
Min
Typ
Max
Unit
-
-
40
V
-
-
120
A
Tmb = 25 °C; see Figure 2
-
-
357
W
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 11
-
1.35
1.6
mΩ
VGS = 5 V; ID = 25 A; VDS = 32 V;
see Figure 13; see Figure 14
-
40.9
-
nC
[1]
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD
[1]
gate-drain charge
Continuous current is limited by package.
BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base;
connected to drain
Simplified outline
Graphic symbol
mb
D
G
mbb076
S
2
1
3
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Type number
BUK961R6-40E
Package
Name
Description
Version
D2PAK
plastic single-ended surface-mounted package (D2PAK);
3 leads (one lead cropped)
SOT404
4. Marking
Table 4.
Marking codes
Type number
Marking code
BUK961R6-40E
BUK961R6-40E
BUK961R6-40E
Product data sheet
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© NXP B.V. 2012. All rights reserved.
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BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
40
V
VDGR
drain-gate voltage
RGS = 20 kΩ
-
40
V
VGS
gate-source voltage
DC
-10
10
V
Pulsed
-15
15
V
drain current
ID
Tmb = 25 °C; VGS = 5 V; see Figure 1
[1]
-
120
A
Tmb = 100 °C; VGS = 5 V; see Figure 1
[1]
-
120
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
see Figure 4
-
1363
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
357
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
-
120
A
-
1363
A
-
1008
mJ
Source-drain diode
IS
source current
Tmb = 25 °C
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
[1]
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
ID = 120 A; Vsup ≤ 40 V; RGS = 50 Ω;
VGS = 5 V; Tj(init) = 25 °C; unclamped;
see Figure 3
[1]
Continuous current is limited by package.
[2]
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[3]
Refer to application note AN10273 for further information.
BUK961R6-40E
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 May 2012
[2][3]
© NXP B.V. 2012. All rights reserved.
3 of 14
BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aag332
400
03aa16
120
ID
(A)
Pder
(%)
300
80
200
(1)
40
100
0
0
0
Fig 1.
50
100
150
Tmb (°C)
200
0
50
100
150
200
Tmb (°C)
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aag343
103
IAL
(A)
102
(1)
10
(2)
(3)
1
10-1
10-3
Fig 3.
10-2
10-1
1
tAL (ms)
10
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time
BUK961R6-40E
Product data sheet
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Rev. 2 — 16 May 2012
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BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aag333
104
ID
(A)
Limit RDSon = V DS / ID
103
tp =10 μ s
100 μ s
102
10
1 ms
DC
10 ms
100 ms
1
10-1
10-1
Fig 4.
1
102
10
103
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from
junction to mounting base
see Figure 5
-
-
0.42
K/W
Rth(j-a)
thermal resistance from
junction to ambient
minimum footprint; mounted on
a printed-circuit board
-
50
-
K/W
003aaf570
1
Zth(j-mb)
(K/W)
10-1
= 0.5
0.2
0.1
0.05
tp
T
P
10-2
0.02
t
tp
single shot
T
10-3
10-6
Fig 5.
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration.
BUK961R6-40E
Product data sheet
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Rev. 2 — 16 May 2012
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BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
40
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
36
-
-
V
VGS(th)
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 9; see Figure 10
1.4
1.7
2.1
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 9
-
-
2.45
V
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 9
0.5
-
-
V
IDSS
drain leakage current
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
0.13
1
µA
VDS = 40 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
IGSS
gate leakage current
VGS = 10 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = -10 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 11
-
1.35
1.6
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 11
-
1.17
1.4
mΩ
VGS = 5 V; ID = 25 A; Tj = 175 °C;
see Figure 12; see Figure 11
-
-
3.1
mΩ
ID = 25 A; VDS = 32 V; VGS = 5 V;
see Figure 13; see Figure 14
-
120
-
nC
-
26.9
-
nC
-
40.9
-
nC
-
12300 16400 pF
-
1530
1840
pF
-
740
1020
pF
-
95
-
ns
-
118
-
ns
-
195
-
ns
RDSon
drain-source on-state
resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
tf
fall time
-
119
-
ns
LD
internal drain
inductance
from upper edge of drain mounting base
to center of die
-
2.5
-
nH
LS
internal source
inductance
from source lead to source bonding
pad
-
7.5
-
nH
-
0.77
1.2
V
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Tj = 25 °C; see Figure 15
VDS = 30 V; RL = 1.2 Ω; VGS = 5 V;
RG(ext) = 5 Ω
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 16
trr
reverse recovery time
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 25 V
BUK961R6-40E
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 May 2012
-
57
-
ns
-
97
-
nC
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BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aag334
300
VGS (V) = 10
ID
(A)
5.0 3.5
003aag339
8
3.0
RDSon
(mΩ)
240
6
2.8
180
4
120
2.6
2
60
2.4
0
0
0
0.4
0.8
VDS (V)
1.2
0
2
4
6
8
VGS (V)
10
Tj = 25 °C; tp = 300 μs
Fig 6.
Output characteristics: drain current as a
function of drain-source voltage; typical values
003aag335
400
Fig 7.
Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aah025
3
VGS(th)
(V)
2.5
ID
(A)
max
300
2
typ
1.5
200
min
1
100
Tj = 175 °C
Tj = 25 °C
2
4
0.5
0
-60
0
0
Fig 8.
VGS (V)
6
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
BUK961R6-40E
Product data sheet
Fig 9.
0
60
120
Tj (°C)
180
Gate-source threshold voltage as a function of
junction temperature
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BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aah026
10-1
003aag340
6
VGS (V) = 2.6
ID
(A)
2.8
3.0
RDSon
(mΩ)
10-2
min
10-3
typ
4
max
10-4
2
3.5
10-5
5.0
10.0
10-6
0
0
1
2
VGS (V)
0
3
100
200
ID (A)
300
Tj = 25 °C; tp = 300 µs
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
Fig 11. Drain-source on-state resistance as a function
of drain current; typical values
003aag820
2
a
VDS
1.5
ID
VGS(pl)
1
VGS(th)
VGS
0.5
QGS1
QGS2
QGS
0
-60
0
60
120
Tj (°C)
BUK961R6-40E
Product data sheet
003aaa508
180
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
QGD
QG(tot)
Fig 13. Gate charge waveform definitions
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Rev. 2 — 16 May 2012
© NXP B.V. 2012. All rights reserved.
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BUK961R6-40E
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aag341
10
003aag337
105
VGS
(V)
C
(pF)
8
Ciss
104
14 V
6
4
VDS = 32 V
Coss
103
Crss
2
102
10-1
0
0
60
120
180
QG (nC)
240
Tj = 25 °C; ID = 25 A
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 14. Gate-source voltage as a function of gate
charge; typical values
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aag342
300
IS
(A)
240
180
120
Tj = 175 °C
Tj = 25 °C
60
0
0
0.5
1
VSD (V)
1.5
VGS = 0 V
Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
BUK961R6-40E
Product data sheet
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Rev. 2 — 16 May 2012
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N-channel TrenchMOS logic level FET
8. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 17. Package outline SOT404 (D2PAK)
BUK961R6-40E
Product data sheet
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Rev. 2 — 16 May 2012
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N-channel TrenchMOS logic level FET
9. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK961R6-40E v.2
20120516
Product data sheet
-
BUK961R6-40E v.1
-
-
Modifications:
BUK961R6-40E v.1
BUK961R6-40E
Product data sheet
•
•
Status changed from objective to product.
Various changes to content.
20120404
Objective data sheet
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N-channel TrenchMOS logic level FET
10. Legal information
10.1 Data sheet status
Document status[1] [2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
10.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
10.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial sale of NXP Semiconductors.
BUK961R6-40E
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
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N-channel TrenchMOS logic level FET
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G
reenChip,HiPerSmart,HITAG,I²C-bus
logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE
Ultralight,MoReUse,QLPAK,Silicon
Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia
andUCODE — are trademarks of NXP B.V.
HD Radio andHD Radio logo — are trademarks of iBiquity Digital
Corporation.
11. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:salesaddresses@nxp.com
BUK961R6-40E
Product data sheet
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N-channel TrenchMOS logic level FET
12. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
10.1
10.2
10.3
10.4
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 May 2012
Document identifier: BUK961R6-40E