Data Sheet

BUK9620-100B
N-channel TrenchMOS logic level FET
Rev. 02 — 6 May 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
„ AEC-Q101 compliant
„ Low conduction losses due to low
on-state resistance
„ Suitable for logic level gate drive
sources
„ Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
„ 12 V, 24 V and 42 V loads
„ Motors, lamps and solenoids
„ Automotive and general purpose
power switching
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
100
V
ID
drain current
VGS = 5 V; Tmb = 25 °C;
see Figure 1; see Figure 3
-
-
63
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
203
W
VGS = 4.5 V; ID = 25 A;
Tj = 25 °C; see Figure 11;
see Figure 12
-
16.4
22.3
mΩ
VGS = 5 V; ID = 25 A;
Tj = 25 °C; see Figure 12;
see Figure 11
-
16.2
20
mΩ
ID = 63 A; Vsup ≤ 100 V;
RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
-
-
222
mJ
Static characteristics
RDSon
drain-source
on-state resistance
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
Simplified outline
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
2
1
3
SOT404
(D2PAK)
3. Ordering information
Table 3.
Ordering information
Type number
BUK9620-100B
Package
Name
Description
Version
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one
lead cropped)
SOT404
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
100
V
VDGR
drain-gate voltage
RGS = 20 kΩ
VGS
gate-source voltage
ID
drain current
-
100
V
-15
15
V
Tmb = 25 °C; VGS = 5 V; see Figure 1; see Figure 3
-
63
A
Tmb = 100 °C; VGS = 5 V; see Figure 1
-
45
A
IDM
peak drain current
Tmb = 25 °C; tp ≤ 10 µs; pulsed; see Figure 3
-
253
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
203
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
63
A
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
253
A
-
222
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive
ID = 63 A; Vsup ≤ 100 V; RGS = 50 Ω; VGS = 5 V;
drain-source avalanche Tj(init) = 25 °C; unclamped
energy
BUK9620-100B_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
2 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa24
120
03na19
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
Tmb (°C)
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aac769
103
ID
(A)
Limit RDSon = VDS / ID
2
10
200
Tmb (°C)
tp =10 μs
100 μs
10
DC
1ms
10 ms
1
100 ms
10-1
1
Fig 3.
102
10
VDS (V)
103
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
BUK9620-100B_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
3 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Rth(j-mb)
Rth(j-a)
Conditions
Min
Typ
Max
Unit
thermal resistance from see Figure 4
junction to mounting
base
-
-
0.75
K/W
thermal resistance from mounted on printed circuit board;
junction to ambient
minimum footprint; SOT404 package
-
50
-
K/W
003a a c770
1
Zth (j-mb)
(K/W)
δ = 0.5
0.2
10-1
0.1
0.05
0.02
δ=
P
10-2
tp
T
s ingle s hot
t
tp
T
10-3
1e -6
Fig 4.
10-5
10-4
10-3
10-2
10-1
tp (s )
1
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9620-100B_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
4 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 0.25 mA; VGS = 0 V; Tj = 25 °C
100
-
-
V
ID = 0.25 mA; VGS = 0 V; Tj = -55 °C
90
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10
1
1.58
2
V
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
0.5
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
-
-
2.3
V
Static characteristics
V(BR)DSS
VGS(th)
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 100 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
VDS = 100 V; VGS = 0 V; Tj = 25 °C
-
0.05
1
µA
VDS = 0 V; VGS = 10 V; Tj = 25 °C
-
2
100
nA
VDS = 0 V; VGS = -10 V; Tj = 25 °C
-
2
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 11; see Figure 12
-
16.4
22.3
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 11; see Figure 12
-
15.6
18.5
mΩ
VGS = 5 V; ID = 25 A; Tj = 175 °C;
see Figure 12; see Figure 11
-
-
50
mΩ
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 12; see Figure 11
-
16.2
20
mΩ
ID = 25 A; VDS = 80 V; VGS = 5 V;
Tj = 25 °C; see Figure 14; see Figure 15
-
53.4
-
nC
-
9.5
-
nC
-
21.2
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
VDS = 30 V; RL = 1.2 Ω; VGS = 5 V;
RG(ext) = 10 Ω; Tj = 25 °C
-
4300
5657
pF
-
340
411
pF
-
150
201
pF
-
45
-
ns
-
116
-
ns
turn-off delay time
-
173
-
ns
tf
fall time
-
77
-
ns
LD
internal drain
inductance
from drain lead 6 mm from package to
centre of die; Tj = 25 °C
-
4.5
-
nH
from upper edge of drain mounting base to
centre of die; Tj = 25 °C
-
2.5
-
nH
from source lead to source bond pad;
Tj = 25 °C
-
7.5
-
nH
LS
internal source
inductance
BUK9620-100B_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
5 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 13
-
0.86
1.2
V
trr
reverse recovery time
-
80
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 30 V; Tj = 25 °C
-
272
-
nC
03aa36
10-1
ID
(A)
003a a c771
150
ID
(A)
10-2
VGS (V) =10
4.5
120
3.4
10-3
90
min
typ
3.2
max
10-4
60
3
10-5
30
2.7
10-6
0
2.5
0
Fig 5.
1
2
VGS (V)
3
0
Sub-threshold drain current as a function of
gate-source voltage
003a a c772
28
RDS on
(mΩ)
Fig 6.
2
3
4 VDS (V) 5
Output characteristics: drain current as a
function of drain-source voltage; typical values
003a a c774
160
gfs (S )
24
120
20
80
16
40
0
12
2
Fig 7.
1
4
6
8
VGS (V)
0
10
Drain-source on-state resistance as a function
of gate-source voltage; typical values.
Fig 8.
60
90
I D (A)
120
Forward transconductance as a function of
drain current; typical values.
BUK9620-100B_2
Product data sheet
30
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
6 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003a a c776
120
ID
(A)
03aa33
2.5
VGS(th)
(V)
2
max
90
1.5
typ
1
min
60
Tj = 150 °C
30
25 °C
0.5
0
-60
0
0
Fig 9.
1
2
3
VGS (V)
4
Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
2.5 2.7
RDS on
(mΩ)
3
3.2
60
120
Tj (°C)
180
Fig 10. Gate-source threshold voltage as a function of
junction temperature
003a a c773
50
0
03aa29
3
3.4
a
40
VGS (V) = 4.5
2
10
30
1
20
10
0
30
60
90
120 I D (A) 150
Fig 11. Drain-source on-state resistance as a function
of drain current; typical values.
0
-60
60
120
Tj (°C)
180
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
BUK9620-100B_2
Product data sheet
0
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
7 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003a a c778
120
VDS
IS
(A)
ID
90
VGS(pl)
VGS(th)
60
VGS
150 °C
QGS1
Tj = 25 °C
30
QGS2
QGS
QGD
QG(tot)
003aaa508
0
Fig 14. Gate charge waveform definitions
0
0.5
1
1.5 V (V) 2
SD
Fig 13. Source current as a function of source drain
voltage; typical values.
003a a c777
5
003a a c775
104
Tj = 25 °C
VGS
(V)
C
(pF)
4
Cis s
VDS = 14V
3
VDS = 80V
103
2
Cos s
1
Crs s
0
10
0
20
40
QG (nC) 60
Fig 15. Gate-source voltage as a function of turn-on
gate charge; typical values.
2
10-1
10
2
VDS (V) 10
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
BUK9620-100B_2
Product data sheet
1
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
8 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 17. Package outline SOT404 (D2PAK)
BUK9620-100B_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
9 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK9620-100B_2
20090506
Product data sheet
-
BUK9620-100B_1
Modifications:
BUK9620-100B_1
•
Data sheet status changed from 'Objective' to 'Product'.
20090323
Objective data sheet
-
BUK9620-100B_2
Product data sheet
-
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
10 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BUK9620-100B_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 6 May 2009
11 of 12
BUK9620-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 6 May 2009
Document identifier: BUK9620-100B_2
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