ACS761 Datasheet

ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Features and Benefits
Description
▪ Hall-effect current monitor—no external sense resistor required
▪ PGOOD and P̄¯¯Ḡ¯¯Ō¯Ō¯¯D̄¯ indication
▪ Analog output voltage (factory trimmed for gain and offset)
proportional to applied current
▪ External high-side FET gate drive
▪ 240V*A power fault protection with user-selectable delay
▪ Overcurrent fault protection with user-selectable delay
▪ Fault protection isolates failed supply from output in < 2 μs
▪ 1.5 mΩ internal conductor resistance
▪ Active low latched Fault indicator output signal
▪ User controlled soft start / hot-swap function
▪ Logic enable input pin
▪ 10.8 to 13.2 V, single-supply operation
▪ 2 kV ESD protection for all pins
The ACS761 combines Allegro™ Hall-effect current sense
technology with a hot-swap controller resulting in a more
efficient integrated controller for 12 V applications. By
eliminating the need for a shunt resistor, the I2R losses in the
power path are reduced.
When the ACS761 is externally enabled, and the voltage rail is
above the internal UVLO threshold, the internal charge pump
drives the gate of the external FET. When the load voltage
reaches its target value PGOOD is asserted high. When a fault
is detected, the gate is disabled while simultaneously alerting
the application that a fault has occurred.
The integrated protection in the ACS761 incorporates three
levels of fault protection, which includes a Power Fault with
user-selectable delay, an Overcurrent Fault threshold with userselectable delay, and Short Circuit protection, which disables
the gate in less than 2 μs. These faults are indicated to the
host system via the Fault pin and are cleared upon reasserting
enable high.
Package: 24 pin QSOP (suffix LF)
Approximate Scale
Typical Application
1
2
IP
3
4
CIN
5
RV1
6
Enable
7
REN
CEN
8
VOUT
11
CG
COCD
COPD
761ELF20B-DS, Rev. 5
9
10
12
IP+
IP–
IP+
IP–
IP+
IP–
IP+
IP–
IP+
ACS761
IP–
IP+
IP–
EN
GATE
VIOUT
GND
NC
PGOOD
CG
FB+
OCDLY
PGOOD
OPDLY
FAULT
24
23
22
S1
VLOAD
21
CLOAD
20
19
18
17
16
15
14
13
RG
RFB
3.3 V
100
kΩ
RS1
100 kΩ
RFAULT
100 kΩ
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Selection Guide
Part Number
Package
Packing*
ACS761ELFTR-20B-T
QSOP24 surface mount
*Contact Allegro for additional packing options
2500 pieces/reel
Absolute Maximum Ratings
Characteristic
Rating
Units
VCC
24
V
GATE Drive Output Voltage*
VGATE
32
V
FB+ Forward Voltage*
VFB+
24
V
EN Forward Voltage*
VEN
32
V
All Other Pins Forward Voltage
VIN
8
V
Reverse DC Voltage, All Pins*
VR
–0.5
V
Forward Voltage, IPx pins*
Reverse Transient DC Voltage, All Pins*
Current Sense Output Current Source
Current Sense Output Current Sink
Symbol
Vr
VIOUT to GND
IVIOUT(Source)
IVIOUT(Sink)
V
1
mA
1
mA
ºC
TJ(max)
165
ºC
Tstg
–65 to 165
ºC
TA
Maximum Junction Temperature
VCC to VIOUT
–5
–40 to 85
Operating Ambient Temperature
Storage Temperature
Notes
Range E
* With respect to GND.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Pin-out Diagram
IP+ 1
24 IP–
IP+ 2
23 IP–
IP+ 3
22 IP–
IP+ 4
21 IP–
IP+ 5
20 IP–
IP+ 6
19 IP–
EN 7
18 GATE
VIOUT 8
17 GND
NC 9
16 PGOOD
CG 10
15 FB+
OCDLY 11
14 PGOOD
OPDLY 12
13 FAULT
Terminal List Table
Number
1-6
7
8
9
Name
IP+
EN
VIOUT
NC
10
CG
11
OCDLY
12
OPDLY
13
¯ĀŪ¯L̄¯T̄
¯
F̄
14
¯Ḡ
¯Ō
¯Ō
¯D̄¯
P̄
15
FB+
16
17
PGOOD
GND
18
GATE
19-24
IP–
Function
Primary sampled current conduction path input; power input pins: connected to VCC.
Enable pin. The falling edge on the EN pin clears an overpower, overcurrent, or short circuit fault.
Analog output. Output voltage on this pin is proportional to the current flowing from the IP+ pins to the IP– pins.
No connect. Connection to ground is recommended.
Terminal for CG capacitor. May be used to adjust the turn-on time and soft start control of an external MOSFET,
S1. Voltage on this pin limits inrush current through MOSFET S1. Set via external capacitance, CG, connected
between this pin and GND. This capacitor is charged by an internal 20 μA current source.
Terminal for external capacitor, COCD, Used to adjust delay for overcurrent shutdown, set via the external
capacitor, COCD, connected between this pin and GND.
Terminal for external capacitor, COPD, Used to adjust delay for overpower shutdown, set via the external capacitor,
COPD, connected between this pin and GND.
Active low; output signal for device short circuit and overpower faults. Connect a pull-up resistor between this pin
and the 3.3 V rail.
Active low; output signal indicating load voltage has risen to the proper level.
Input of positive feedback on output voltage. Used to determine overpower fault threshold by difference between
FB+ and GND pins.
Active high; output signal indicating load voltage has risen to the proper level.
Terminal for ground connection.
Terminal for external MOSFET, S1. Provides output voltage to drive S1. Current through S1 is controlled at startup by external capacitance connected between the CG pin and GND.
Primary sampled current conduction path output; power output pins.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Functional Block Diagram
+12 V Load
S1
EN
CG
GATE
100 kΩ
Bias and
VREG
IP–
PGOOD
Charge
Pump
UVLO
FB+
+
VREF
Power
Calculator
Hall Current
Drive
PGOOD
–
OPDLY
Dynamic Offset
Cancellation
+
–
Signal
Recovery
Short Circuit
Detection
–
OCDLY
VIOUT
+
Zero Current Output
Voltage Adjustment
IP+
+12 VIN
OPDLY
OCDLY
PGOOD / Fault
Logic
FAULT
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
OPERATING CHARACTERISTICS valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
General Electrical Characteristics
Source Current
Linear Sensing Range
Primary Conductor Resistance
Supply Voltage
Supply Current
Undervoltage Lockout (UVLO)
Symbol
ISOURCE
IP
RPRIMARY
VCC
ICC
VUVLOH
VUVLOL
tUVLOE
UVLO Delay to Chip Enable/ Disable
tUVLOD
FB+ Input Resistance
RFB
Current Sense Performance Characteristics
VIOUT Analog Output Propagation
tPROP
Time
VIOUT Analog Output 10-90% Rise
tr
Time
VIOUT Load Capacitance
CLOAD
VIOUT Load Resistance
RLOAD
VIOUT Analog Signal Bandwidth1
f3dB
VIOUT Analog Signal Sensitivity
Sens
Sensitivity Slope Over Temperature
∆SensTA
VIOUT Analog Noise Level2
VNOISE(PP)
VIOUT Analog Nonlinearity
ELIN
Zero Current Output Voltage
Zero Current Output Slope Over
Temperature
VIOUT(Q)
∆IOUT(Q)TA
Output Voltage Saturation3
VOL
VOH
VIOUT Total Error % of IP
ETOT
Test Conditions
Min.
Typ.
Max.
Units
–
0
–
10.8
–
–
7.0
250
–
1.5
12
8
–
–
–
55
–
13.2
10.5
10.5
–
μA
A
mΩ
V
mA
V
V
–
700
1100
μs
–
1
2.5
μs
–
240
–
kΩ
–
2
–
μs
–
5
–
μs
–
20
–
–
1
–
nF
kΩ
–
50
–
kHz
TA = 25°C
–
65
–
mV/A
Over full ambient operating temperature range
TA = 0°C to 25°C
TA = 25°C to 85°C
Mean peak-to-peak, TA = 25°C, 50 kHz external device filter
Over full ambient operating temperature range and linear
sensing range
63
–
–
–
–
0.042
0.027
20
69
–
–
–
mV/A
mV/A/°C
mV/A/°C
mV
–
±0.5
±1
%
0.18
–
–
–
–
–
–4
0.2
–0.148
–0.057
0.15
3.71
<±1.0
–
0.22
–
–
–
–
–
4
V
mV/°C
mV/°C
V
V
%
%
TA = 25°C, VIOUT connected to GND
Current flows from IP+ to IP- pins
TA = 25°C
Voltage applied to IP+ pins
VCC rising and CG pin current source turns on, EN pin = high
VCC falling and CG pin current source turns off, EN pin = high
Enabling, measured from rising VCC > VUVLOH to
VGATE > 1 V, EN pin = high
Disabling, measured from falling VCC < VUVLOL to
VGATE < 1 V, EN pin = high
TA = 25°C
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
= 100 pF
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
= 100 pF
–3 dB, Ip = 10 A peak-to-peak, TA = 25°C, no external device
filter, capacitance from VIOUT to GND = 100 pF
TA = 0°C to 85°C
TA = 0°C to 25°C
TA = 25°C to 85°C
TA = 25°C
TA = 25°C
TA = 25°C, IP = 20 A
TA = 0°C to 85°C, IP = 20 A
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
OPERATING CHARACTERISTICS (continued) valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Operational Supply Indicator Performance Characteristics
Test Conditions
Min.
Typ.
Max.
Units
PGOOD Output Voltage
VPGOODOL
IPGOOD = 3 mA sink current
–
–
0.4
V
PGOOD Output Leakage Current
IPGOODOH
VPGOOD = 3.3 V
–
–
1
μA
–
VPGOODHIGH TA = 25°C; FB+ = 0 V → 12 V
PGOOD Activation Threshold
10.2
10.8
V
9.6
V
PGOOD Deactivation Threshold
VPGOODLOW
TA = 25°C; FB+ = 12 V → 0 V
9.8
–
¯Ō
¯Ō
¯D̄¯ Output Voltage
P̄¯Ḡ
V P̄¯Ḡ¯Ō¯Ō¯D̄¯ OL
I P̄¯Ḡ¯Ō¯Ō¯D̄¯ = 3 mA sink current
–
–
0.4
V
¯Ō
¯Ō
¯D̄¯ Output Leakage Current
P̄¯Ḡ
I P̄¯Ḡ¯Ō¯Ō¯D̄¯ OH
V P̄¯Ḡ¯Ō¯Ō¯D̄¯ = 3.3 V
–
–
1
μA
V P̄¯Ḡ¯Ō¯Ō¯D̄¯ HIGH TA = 25°C; FB+ = 0 V → 12 V
–
10.2
10.8
V
V P̄¯Ḡ¯Ō¯Ō¯D̄¯ LOW TA = 25°C; FB+ = 12 V → 0 V
9.6
9.8
–
V
¯Ō
¯Ō
¯D̄¯ Deactivation Threshold
P̄¯Ḡ
¯Ō
¯Ō
¯D̄¯ Activation Threshold
P̄¯Ḡ
Current Fault Performance Characteristics
Overpower Fault Threshold
PF(th)
Overpower Fault Signal Delay4
Internal –3 dB Filter Frequency for
FB+ Pin
Overcurrent Fault Signal Delay4
Device IP Short Circuit Fault
Threshold5
Device IP Overcurrent Fault
Threshold
Short Circuit/Overcurrent Fault Gate
Delay
Fault Related Signal Characteristics
Internal Pull Down Resistance
Between EN and GND
tPFL
fFBFILT
tCFL
TA = 0°C to 85°C
221
230
238
W
¯ĀŪ¯L̄¯T̄
¯ signal to VGATE < 1 V,
TA = 25°C, measured from F̄
OPDLY pin open, load step from 17 to 23 A in 100 ns
–
11
18
μs
TA = 25°C
–
50
–
kHz
¯ĀŪ¯L̄¯T̄
¯ signal to VGATE < 1 V, OCDLY pin
Measured from F̄
open, OPDLY = 0 V, load step from 17 to 55 A in 1 μs
–
8
12
μs
60
130
160
A
IPF
IOC
TA = 0°C to 85°C
35
40
45
A
tSC
¯ĀŪ¯L̄¯T̄
¯ signal to VGATE < 1 V, includes tGF
Measured from F̄
–
2
3
μs
REN
TA = 25°C
–
100
–
kΩ
EN Voltage Threshold6
VENH
VENL
2
–
–
–
–
0.55
V
V
Enable Signal Duration
tEN
IC enabled when VEN > VENH
IC disabled when VEN < VENL
CX in μF, where Cx is the largest capacitance among: CG,
COCD, and COPD
8 × CX
–
–
ms
FAULT Output Voltage
VFAULTOL
IFAULT = 3 mA sink current
–
–
0.4
V
FAULT Output Leakage Current
IFAULTIH
VFAULT = 3.3 V
–
–
1
μA
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
OPERATING CHARACTERISTICS (continued) valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Gate Drive Performance Characteristics
Nominal Gate Voltage
VGATE
Gate Voltage Tolerance
ΔVGATE
Average GATE Drive Current
IGD
Charge Pump Switching Frequency
fCP
GATE Rise Time
GATE Sink Resistance7
GATE Sink Steady State
Resistance7
GATE Shutdown Delay
tGR
RGsink
RGsink(ss)
Test Conditions
Min.
Typ.
Max.
Units
TA = 25°C
TA = 25°C
VCC = 12 V, TA = 25°C
TA = 25°C
TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF,
measured from VGATE = 0 to 15 V, CG pin open, no output
load capacitance
< 5 μs after gate voltage falls low
–
–
30
–
VCC + 10
–
50
1
–
±2
70
–
V
V
μA
MHz
–
1
–
ms
–
20
30
Ω
> 80 μs after gate voltage falls low
–
100
–
kΩ
Measured from fault event to start of GATE pull down
–
200
–
ns
Measured from VGATE = 90% of maximum to VGATE < 1 V,
GATE Maximum Fall Time
tGF
while EN pin switched from high to low, assuming external
–
800
–
ns
MOSFET S1 gate capacitance = 5.8 nF
CG Output Current
ISLEW
TA = 25°C
18
20
22
μA
1 The small signal, ac bandwidth of this device is approximately 90 kHz.
2 This is the 6 σ noise voltage.
3 This test requires currents sufficient to swing the output driver between the fully off state and the saturated state. Assumes that the VIOUT pin is connected to an analog-to-digital converter that saturates at 2.5 V. The VIOUT signal is linear above 2.5 V, however, this test is NOT intended to indicate a
range of linear operation.
4 This is the minimum delay time achievable without C
OPD or COCD. Longer delay time can be achieved by using COPD or COCD. See Functional
Description section for details. Voltage trip point for both the OPDLY and the OCDLY pins is 3.85 V.
5 This parameter is internally programmed and cannot be controlled by the end user.
6 The FAULT output signal is latched. After a latched fault event, the device will be reset only when either: (a) V
EN drops below VENL, or (b) the power to
the device (applied to the IP+ pins) is toggled off and then back on.
7 The gate resistance switches to high impedance approximately 15 to 45 μs after the gate voltage falls low after a fault.
tGSD
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Functional Description
Soft Start and Fault Characteristics
Gate turn on rise time, tGR. Set by external capacitance, CG, on
the CG pin, such that CG = 7.5 × tGR , where CG is in F and tGR
is rise time in seconds. For example, a 3.9 F capacitor connected
from the CG pin to GND (without an output load) will yield a
rise time of approximately 500 ms: CG  7.5 × 0.5 s = 3.75 F,
 3.9 F (a common capacitor value). When the CG pin is kept
open, the ACS761 has a minimum tGR of 1 ms typical.
It is important to select values for CG and the FET load resistance
(RLOADFET) that ensure safe power consumption during FET
activation. The combination of a large FET current consumption
caused by RLOADFET, and a long gate voltage slew caused by CG,
could cause the overall FET power consumption to be outside of
its safe operating area during FET activation.
IPF fault signal delay, tIPF . This is the delay from high current
level fault sense to the start of turn-off of the external MOSFET
S1 turn-off. Set by external capacitance, COCD, on the OCDLY
pin, such that COCD = 5.17 × trOCD ; where COCD is in F and
trOCD is rise time in seconds. When the OCDLY pin is kept open,
the IC has a minimum fault delay, tIPFLmax, of 8 s maximum.
Load power fault signal delay, tPFL. This is the delay from
maximum power level fault, PF(th), sense to the start of external
MOSFET S1 turn-off. Set by external capacitance, COPD, on the
OPDLY pin, such that COPD = 5.17 × trOPD ; where COPD is in F
and trOPD is rise time in seconds. The IC has a minimum fault
delay when the OPDLY pin kept open of 10 s typical.
Accuracy Characteristics
Sensitivity, Sens. The change in device output in response to a
1 A change through the primary conductor. Sens is the product of
the magnetic circuit sensitivity (G/A) and the linear IC amplifier
gain (mV/G). The linear IC amplifier gain is trimmed at Allegro
final test to optimize the sensitivity (mV/A) for the full-scale
current range of the device.
Noise, VNOISE(PP). The product of the linear IC amplifier gain
(mV/G) and the noise floor for the Allegro Hall effect linear IC.
Dividing the noise (mV) by the sensitivity (mV/A) provides the
smallest current that the device is able to resolve.
Nonlinearity, ELIN. The linearity of the VIOUT signal is the
degree to which the voltage output from the device varies in
direct proportion to the primary sampled current, up to 20 A.
Nonlinearity reveals the maximum deviation in the slope of the
device transfer function compared to the slope of the ideal transfer curve for this transducer. The following equation is used to
derive the linearity:
{ [
100 1–
(VIOUT_full-scale amperes – VIOUT(Q))
2 (VIOUT_half-scale amperes – VIOUT(Q))
[{ ,
where full-scale current is 20 A, and half-scale current is 10 A.
Zero Current Output Voltage, VIOUT(Q). The output of the
device when the primary current, IP , is 0 A. Variation in VIOUT(Q)
can be attributed to the resolution of the Allegro linear IC quiescent voltage trim and thermal drift.
VIOUT Total Error, ETOT. The maximum percentage deviation of
the actual output from its ideal value, based on an ideal sensitivity of 65 mV/A over the operating ambient temperature range.
PGood Indication. The PGood indication is active high when
valid power is applied to the device. PGood activates approximately 500 ms after the FB+ voltage reaches its VPGOODON
threshold. PGood will not release until 500 ms after the FB+
voltage drops below its VPGOODOFF threshold.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Overpower Fault Operation
The timing diagram in figure 1 shows characteristic operation of
the ACS761 when the power consumed from the 12 V system bus
exceeds Overpower Fault Threshold, PF(th). The system power
supply bus reaches the nominal steady state level of 12 V before
the EN pin (Enable pin, active high) of the ACS761 transitions
to the high state at time tEN1. Note that, when the EN pin is in
the low state, the GATE pin is actively pulled low. However,
as shown in the timing diagram, the voltage on the GATE pin
increases with a positive slope after the EN pin transitions to
the high state. The ramp rate of the GATE pin is controlled by
the value of the capacitor connected to the CG pin. At a certain GATE voltage, current begins to flow through the external
protection MOSFET, S1, and this current increases as the GATE
voltage increases. The voltage at the VIOUT pin, which is the
current device output voltage of the ACS761, proportionally
tracks the current that flows through the MOSFET.
In the timing diagram, the system is in normal, steady state operation up until the time tINIT_F. At tINIT_F , the current load on the
12 V power supply increases from 19.2 to 22 A and the ACS761
internally registers an overpower fault condition. At this time, the
voltage on the OPDLY pin increases with a constant slope. (This
slope is controlled by the value of the capacitor connected to the
OPDLY pin). This voltage continues to increase with a constant
slope until either:
• The OPDLY pin voltage reaches a threshold of 3.85 V (if this
¯T̄
¯ signal is latched in the low state), or
occurs, the F̄¯Ā¯Ū¯L̄
• The power consumption of the system falls below PF(th) (at
which time the OPDLY pin voltage is pulled to ground)
An overpower fault event is detected at tOP_F. At this time,
¯T̄
¯ signal transitions to the low state and the GATE
the F̄¯Ā¯Ū¯L̄
¯T̄
¯ signal is latched and the
pin is pulled to ground. The F̄¯Ā¯Ū¯L̄
chip will pull down the GATE voltage until the EN pin of the
1.83 V
0.2 V
1.648 V
VIOUT Voltage
22 A
19.2 V
Load Current /IP
0A
22 V
GATE Voltage
0V
3.3 V
FAULT
0.4 V
EN
3.3 V
≈0V
5.5 V
CG Pin Voltage
0V
12 V
VLOAD to Load
0V
3.85 V
Threshold
OPDLY Pin Voltage
5.5 V
0V
OCDLY Pin Voltage
0V
12 V
tEN1
Voltage on IP+ Pins
tINIT_F
t0P_F
tRESET
Time
Figure 1. Timing Diagram for Overpower Fault
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
ACS761 transitions to the low state and then back to the high
state. As shown in the timing diagram, certain ACS761 signals
¯T̄
¯ signal and the OPDLY pin voltage) are reset when
(the F̄¯Ā¯Ū¯L̄
the EN pin transitions to the low state. These signals are reset in
order to guarantee normal device operation (soft start and fault
monitoring) when the EN signal transitions back to the high state.
Soft Short Circuit Fault Operation
The timing diagram in figure 2 shows the characteristic operation of the ACS761 when the current load on the 12 V system bus
jumps from the 19-to-20 A level to the 40 A level. The 40 A load
is typically indicative of a soft short circuit on the ILOAD side of
the external MOSFET. In figure 2, the system power supply bus
reaches the nominal steady state level of 12 V before the EN pin
(Enable pin, active high) of the ACS761 transitions to the high
state at time tEN1. Note that when the EN pin is in the low state,
the GATE pin is actively pulled low. However, as shown in the
timing diagram, the voltage on the GATE pin increases with a
positive slope after the EN pin transitions to the high state.
The ramp rate of the GATE pin is controlled by the value of the
capacitor connected to the CG pin.
At a certain GATE voltage, current begins to flow through the
external protection MOSFET, S1, and this current increases as the
GATE voltage increases. The voltage at the VIOUT pin, which is
the current device output voltage of the ACS761, proportionally
tracks the current that flows through the MOSFET. In the figure 2, the system is in normal, steady state operation up until the
time tINIT_F. At tINIT_F the current load on the 12 V power supply
increases from 19.2 A to 40 A , reached at t40A_F at which the
ACS761 internally registers both an overpower fault and an overcurrent fault. At tINIT_F, the voltage on the OPDLY and OCDLY
pins increases with a constant slope. The slope of the voltage on
the two delay pins is controlled by the value of the capacitor connected to each pin. In this case the capacitor on the OCDLY pin
is smaller than the capacitor on the OPDLY pin and the voltage
on the OCDLY pin ramps much faster than the voltage on the
OPDLY pin (both pins are connected to separate 20 μA current
3V
1.648 V
VIOUT Voltage
0.2 V
40 A
19.2 V
Load Current /IP
0A
22 V
GATE Voltage
0V
3.3 V
0.4 V
FAULT
EN
3.3 V
≈0V
0V
0V
CG Pin Voltage
5.5 V
VLOAD to Load
12 V
OPDLY Pin Voltage
0V
0V
12 V
tEN1
3.85 V
Threshold
OCDLY Pin Voltage
5.5 V
Voltage on IP+ Pins
tINIT_F
t40A_F
tRESET
Time
Figure 2. Timing Diagram for 30 to 40 A Load Fault
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10
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
sources). The voltages on each delay pin continues to increase
with a constant slope until:
• either the OPDLY or the OCDLY pin voltage reaches a thresh¯T̄
¯ signal is latched in the
old of 3.85 V (if this occurs, the F̄¯Ā¯Ū¯L̄
low state), or
• the current load of the system falls below 20 A for the OPDLY
pin and 40 A for the OCDLY pin.
In figure 2 a short circuit fault event is detected at t40A_F . At
¯T̄
¯ signal transitions to the low state and the
this time, the F̄¯Ā¯Ū¯L̄
¯T̄
¯ state is latched and
GATE pin is pulled to ground. The F̄¯Ā¯Ū¯L̄
the chip will pull down the GATE voltage until the EN pin of the
ACS761 transitions to the low state and then back to the high
state. As shown in the timing diagram, certain ACS761 signals
¯T̄
¯ signal and the OCDLY pin voltage) are reset when
(the F̄¯Ā¯Ū¯L̄
the EN pin transitions to the low state. These signals are reset in
order to guarantee normal device operation (soft start and fault
monitoring) when the EN signal transitions back to the high state.
5.25 V
VIOUT Voltage
0.2 V
1.648 V
Hard Short Circuit Fault Operation
The timing diagram in figure 3 specifically shows characteristic
operation of the ACS761 when the device is powered on (via
the EN pin) and a 50 m short circuit is present from load side
of the external MOSFET, S1, to ground. In figure 3 the system
power supply bus reaches the nominal steady state level of 12 V
before the EN pin of the ACS761 transitions to the high state at
time tEN1. The voltage on the GATE pin increases with a positive slope after the EN pin transitions to the high state. The ramp
rate of the GATE pin is controlled by the value of the capacitor
connected to the CG pin. In the example shown below a small
capacitor is connected to the CG pin and the pin ramps to 5.5 V
in < 10 s.
In panel A of figure 3, the device is enabled into a 50 m short
circuit. Therefore, as the GATE voltage increases the current through the external MOSFET increases at a rapid rate.
In this example, it is assumed that there is no capacitor on the
OCDLY pin. When the current through the MOSFET exceeds
Load Current /IP
40 A
0A
GATE Voltage
22 V
0V
FAULT
3.3 V
VIOUT Voltage
0.2 V
130 A
40 A
1.648 V
Load Current /IP
19.2 A
GATE Voltage
22 V
0V
FAULT
3.3 V
0.4 V
EN
0.4 V
≈0V
5.5 V
CG Pin Voltage
12 V
VLOAD to Load
0V
0V
3.85 V
Threshold
OCDLY Pin Voltage
0V
5.5 V
Voltage on IP+ Pins
t40A_F
tGATE_LOW
tRESET
12 V
3.85 V
Threshold
OPDLY Pin Voltage
3.85 V
Threshold
OCDLY Pin Voltage
Voltage on IP+ Pins
tEN1
t40A_F
t130A_F
tGATE_LOW
Time
(A)
12 V
VLOAD to Load
0V
tEN1
5.5 V
CG Pin Voltage
0V
OPDLY Pin Voltage
0V
12 V
3.3 V
≈0V
0V
0V
EN
3.3 V
tRESET
<2 μs
Time
(B)
Figure 3. (A) Timing Diagram for a 50 mΩ Short Circuit from VLOAD to GND; (B) Timing Diagram for a 50 mΩ Short Circuit
from VLOAD to GND, capacitor COCD with high rating connected.
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
11
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
the overcurrent threshold, the voltage on the OCDLY pin rises
quickly beginning at t40A_F . As the voltage on the OCDLY pin
rises, so does the voltage on the CG pin and the current through
the external MOSFET. If there is no capacitor on the OCDLY pin,
and if the ACS761 Short Circuit Fault Threshold, ISC , is greater
than 100 A, then the OCDLY pin will reach the 3.85 V threshold before the current through the external MOSFET exceeds
ISC. This is the case depicted in the panel A. The fault event is
¯T̄
¯ signal transidetected at tGATE_LOW. At this time. the F̄¯Ā¯Ū¯L̄
tions to the low state and the GATE pin is pulled to ground.
In the event that a large capacitor is connected to the OCDLY
pin, the ACS761 will not pull down the gate of the external
MOSFET until the current flowing through the MOSFET exceeds
ISC (shown in panel B, under the assumption that ISC equals 130
A). The device pulls down the MOSFET GATE approximately
2 s after the load current exceeds this threshold. In this case, a
significant current (> 40 A but < 130 A) may flow through the
MOSFET for tens of microseconds before the Short Circuit Fault
Threshold trips.
¯T̄
¯ signal is latched and the chip will pull
When tripped, the F̄¯Ā¯Ū¯L̄
down the GATE voltage until the EN pin of the ACS761 transitions to the low state and then back to the high state. Certain
ACS761 signals (soft start and fault monitoring related) are reset
when the EN pin transitions to the low state. These signals are
reset in order to guarantee normal device operation when the EN
signal transitions to the high state.
Determining the Root Cause of an ACS761 Fault Event
The Fault Condition Truth Table provides system debugging information in the event of a fault event during use of the
ACS761. Note that for all of the fault conditions listed, it is possible to monitor the voltages of various ACS761 output pins and
¯T̄
¯ event.
determine the cause of the ACS761 F̄¯Ā¯Ū¯L̄
Fault Condition Truth Table
Pin Logic State
EN
Pin
¯Ā¯Ū¯L̄
¯T̄
¯
F̄
Pin
OPDLY
Pin
OCDLY
Pin
Probable Root Cause
High
Low
High
Low
Device Overpower Fault Threshold, PF(th), exceeded
High
Low
Low
High
Device IP Overcurrent Fault Threshold, IOC, exceeded
High
Low
Low
Low
Device IP Short Circuit Fault Threshold, IPF, exceeded
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Application Information
Current Mode Operation
The ACS761 can be set to ignore a Power Mode fault condition
to operate in pure Current Mode. This can be done by grounding
the OPDLY pin to disable the overpower fault condition.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Package LF, 24-pin QSOP
8º
0º
8.66 ±0.10
24
0.25
0.15
3.91 ±0.10
2.30
5.00
5.99 ±0.20
A
1.27
0.41
1
1.04 REF
2
0.25 BSC
Branded Face
24X
1.75 MAX
0.20 C
0.30
0.20
0.635 BSC
For Reference Only, not for tooling use (reference JEDEC MO-137 AE)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.25 MAX
SEATING
PLANE
C
SEATING PLANE
GAUGE PLANE
0.40
0.635
B
PCB Layout Reference View
NNNNNNNNNNNNN
TLF-AAA
LLLLLLLLLLL
A Terminal #1 mark area
B Reference pad layout (reference IPC7351 SOP63P600X175-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
Standard Branding Reference View
N = Device part number
T = Temperature code
LF = (Literal) Package type
A = Amperage
Copyright ©2008-2013, Allegro MicroSystems, LLC
The products described herein are manufactured under one or more of the following U.S. patents: 5,619,137; 5,621,319; 6,781,359; 7,075,287;
7,166,807; 7,265,531; 7,425,821; or other patents pending.
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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