1.4 MB

The following document contains information on Cypress products.
2ch DC/DC converter IC
with PFM/ PWM synchronous
rectification
ASSP for Power Management Applications
MB39A214A
Data Sheet (Full Production)
Publication Number MB39A214A-DS405-00007
CONFIDENTIAL
Revision 2.1
Issue Date January 31, 2014
D a t a S h e e t
2
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
2ch DC/DC converter IC
with PFM/ PWM synchronous
rectification
ASSP for Power Management Applications
MB39A214A
Data Sheet (Full Production)
 DESCRIPTION
MB39A214A is a N-ch/ N-ch synchronous rectification type 2ch Buck DC/DC converter IC equipped with
a bottom detection comparator for low output voltage ripple. It supports low on-duty operation to allow
stable output of low voltages when there is a large difference between input and output voltages. It also
allows the high switching frequency setting, enabling the downsized peripheral circuits and low-cost
configuration. MB39A214A realizes ultra-rapid response and high efficiency with built-in enhanced
protection features. It is most suitable for the power supply for ASIC or FPGA core, input/output devices, or
memory.
 FEATURES

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High efficiency
Frequency setting by internal preset function : 310 kHz, 620 kHz, 1 MHz
High accuracy reference voltage
: ± 0.7% (Ta = + 25 °C)
VIN Input voltage range
: 6 V to 28 V
Output voltage setting range
: 0.7 V to 5.3 V
Possible to select the automatic PFM/PWM selection mode or PWM-fixed mode
PAF frequency limitation function (Prohibit Audio Frequency) : > 30 kHz (Min)
Built-in boost diode, external fly-back diode not required
Built-in discharge FET
Built-in over voltage protection function
Built-in under voltage protection function
Built-in over temperature protection function
Built-in over current limitation function
Soft-start circuit without load dependence
Current sense resistor not required
Built-in synchronous rectification type output steps for N-ch MOS FET
Standby current
: 0 µA (Typ)
Package
: TSSOP24 (4.4 mm6.5 mm1.2 mm [Max])
 APPLICATIONS





Digital TV
Photocopiers
STB
BD, DVD players/recorders
Projectors
etc.
Publication Number MB39A214A-DS405-00007
Revision 2.1
Issue Date January 31, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 PIN ASSIGNMENT
(TOP VIEW)
BST1
1
24
DRVH1
EN1
2
23
LX1
VOUT1
3
22
DRVL1
FB1
4
21
PGND
CS1
5
20
ILIM1
GND
6
19
VCC
FREQ
7
18
VB
CS2
8
17
MODE
FB2
9
16
ILIM2
VOUT2
10
15
DRVL2
EN2
11
14
LX2
BST2
12
13
DRVH2
(FPT-24P-M09)
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MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 PIN DESCRIPTIONS
Pin No.
Pin Name
I/O
Description
1
BST1
—
2
EN1
I
CH1 enable pin.
3
VOUT1
I
CH1 input pin for DC/DC output voltage.
4
FB1
I
CH1 input pin for feedback voltage.
5
CS1
I
CH1 soft-start time setting capacitor connection pin.
6
GND
—
CH1 boost capacitor connection pin.
Ground pin.
7
FREQ
I
Frequency switching signal input pin.
FREQ : GND Short
Switching frequency
FREQ : Open
Switching frequency
FREQ : VB Short
Switching frequency
8
CS2
I
CH2 soft-start time setting capacitor connection pin.
9
FB2
I
CH2 input pin for feedback voltage.
10
VOUT2
I
CH2 input pin for DC/DC output voltage.
11
EN2
I
CH2 enable pin.
12
BST2
—
CH2 boost capacitor connection pin.
13
DRVH2
O
CH2 output pin for external high-side FET gate drive.
14
LX2
—
CH2 inductor and external high-side FET source connection pin.
15
DRVL2
—
CH2 output pin for external low-side FET gate drive.
16
ILIM2
I
CH2 over current detection level setting voltage input pin.
310 kHz
620 kHz
1 MHz
17
MODE
I
DC/DC control mode switching signal input pin.
MODE : GND Short
PFM/PWM
MODE : Open
PFM/PWM, PAF
MODE : VB Short
PWM fixed
18
VB
O
Internal circuit bias output pin.
19
VCC
I
Power input pin for control and output circuits.
20
ILIM1
I
CH1 over current detection level setting voltage input pin.
21
PGND
—
Ground pin for output circuit.
22
DRVL1
O
CH1 output pin for external low-side FET gate drive.
23
LX1
—
CH1 inductor and external high-side FET source connection pin.
24
DRVH1
O
CH1 output pin for external high-side FET gate drive.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
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D a t a S h e e t
 BLOCK DIAGRAM
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CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Min
Max
Unit
VCC pin input voltage
VVCC
VCC pin
− 0.3
+ 30
V
BST pin input voltage
VBST
BST1, BST2 pins
− 0.3
+ 36
V
LX pin input voltage
VLX
LX1, LX2 pins
−1
+ 30
V
—
− 0.3
+7
V
VEN
EN1, EN2 pins
− 0.3
+ 30
V
VFB
FB1, FB2 pins
− 0.3
VB + 0.3
V
VVOUT
VOUT1, VOUT2 pins
− 0.3
+7
V
VILIM
ILIM1, ILIM2 pins
− 0.3
VB + 0.3
V
CS1, CS2 pins
− 0.3
VB + 0.3
V
VFREQ
FREQ pin
− 0.3
VB + 0.3
V
VMODE
MODE pin
− 0.3
VB + 0.3
V
DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins
—
60
mA
Ta ≤ + 25°C
—
+ 1282
mW
− 55
+ 125
°C
Voltage between
BST and LX
EN pin input voltage
Input voltage
Output current
Power dissipation
Storage temperature
VBST-LX
VCS
IOUT
PD
TSTG
—
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
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D a t a S h e e t
 RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
VCC pin input voltage
VVCC
VCC pin
6
—
28
V
BST pin input voltage
VBST
BST1, BST2 pins
—
—
34
V
EN pin input voltage
VEN
EN1, EN2 pins
0
—
28
V
VFB
FB1, FB2 pins
0
—
VB
V
VVOUT
VOUT1, VOUT2 pins
0
—
5.5
V
VILIM
ILIM1, ILIM2 pins
0
—
2
V
VFREQ
FREQ pin
0
—
VB
V
VMODE
MODE pin
0
—
VB
V
Input voltage
Peak output current
IOUT
DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins
Duty ≤ 5% (t = 1/fOSCDuty)
− 1200
—
+ 1200
mA
Operating ambient
temperature
Ta
—
− 30
+ 25
+ 85
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
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CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 ELECTRICAL CHARACTERISTICS
Symbol
Pin
No.
Output voltage
VVB
18
VB = 0 A
Input stability
LINE
18
Load stability
LOAD
Short-circuit
output current
Parameter
Bias Voltage
Block
[VB Reg.]
5.04
5.20
5.36
V
VCC = 6 V to 28 V
—
10
100
mV
18
VB = 0 A to − 1 mA
—
10
100
mV
IOS
18
VB = 0 V
− 145
− 100
− 75
mA
VTLH
18
VB pin
4.0
4.3
4.6
V
VTHL
18
VB pin
3.7
4.0
4.3
V
VH
18
VB pin
—
0.3*
—
V
Charge current
ICS
5,8
CS1, CS2 = 0 V
− 1.5
−1.0
− 0.75
µA
Electrical discharge
resistance
RD
3,10
EN1, EN2 = 0 V,
VOUT1, VOUT2 ≥ 0.15 V
—
25*
—
Ω
VVOVTH
3,10
EN1, EN2 = 0 V,
VOUT1, VOUT2 pins
—
0.2*
—
V
tON11
24
FREQ pin GND connection
VCC = 12 V, VOUT1 = 1.5 V
430
538
646
ns
tON21
13
FREQ pin GND connection
VCC = 12 V, VOUT2 = 1.5V
320
400
480
ns
tON12
24
FREQ pin OPEN
VCC = 12 V, VOUT1 = 1.5 V
210
263
316
ns
tON22
13
FREQ pin OPEN
VCC = 12 V, VOUT2 = 1.5 V
160
200
240
ns
tON13
24
FREQ pin VB connection
VCC = 12 V, VOUT1 = 1.5 V
130
163
196
ns
tON23
13
FREQ pin VB connection
VCC = 12 V, VOUT2 = 1.5 V
100
125
150
ns
tONMIN11
24
FREQ pin GND connection
VCC = 12 V, VOUT1 = 0V
—
136
191
ns
tONMIN21
13
FREQ pin GND connection
VCC = 12 V, VOUT2 = 0V
—
103
145
ns
Minimum
ON time
(Preset value 2)
tONMIN12
24
FREQ pin OPEN
VCC = 12 V, VOUT1 = 0V
—
77
108
ns
tONMIN22
13
FREQ pin OPEN
VCC = 12 V, VOUT2 = 0V
—
58
82
ns
Minimum
ON time
(Preset value 3)
tONMIN13
24
FREQ pin VB connection
VCC = 12V, VOUT1 = 0V
—
55
77
ns
tONMIN23
13
FREQ pin VB connection
VCC = 12 V, VOUT2 = 0V
—
43
61
ns
Minimum OFF time
tOFFMIN
24, 13
—
410
535
ns
Under
Threshold voltage
voltage
Lockout
Protection
Circuit Block Hysteresis width
[UVLO]
Soft-Start/
Discharge
Block
[Soft Start,
Discharge]
Discharge end
voltage
ON time
(Preset value 1)
ON time
(Preset value 2)
ON/OFF
Time
Generator
Block
[tON
Generator]
ON time
(Preset value 3)
Minimum
ON time
(Preset value 1)
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
(Ta = +25°C, VCC = 12 V, EN1, EN2 = 5 V)
Value
Condition
Unit
Min
Typ
Max
—
7
D a t a S h e e t
Symbol
Pin
No.
Threshold voltage
VTH
4, 9
FB pin input current
IFB
VOUT pin input
current
IVO
Parameter
Error
Comparison
Block
[Error Comp.]
Condition
Value
Unit
Min
Typ
Max
Ta = +25°C
0.695
0.700
0.705
V
4, 9
FB1, FB2 = 0.7 V
− 0.1
0
+0.1
µA
3,10
VOUT1, VOUT2 = 1.5 V
—
6.0
8.6
µA
Over current detection
VOFFILIM
offset voltage
21 to 23 PGND − LX1, LX2
21 to 14 ILIM1, ILIM2 = 500 mV
− 30
0
+30
mV
ILIM pin current
IILIM
20,16
ILIM1, ILIM2 = 0 V
−6
−5
−4
µA
ILIM pin current
Temperature slope
TILIM
20,16
Ta = +25°C
—
4500*
—
ppm/
°C
Overvoltage
Protection
Circuit Block
[OVP Comp.]
Over-voltage
detecting voltage
VOVP
4, 9
For REF1, REF2 voltage
110
115
120
%
Hysteresis width
VHOVP
4, 9
—
—
5*
—
%
Detection delay time
tOVP
—
—
10
15
20
µs
Undervoltage
Protection
Circuit Block
[UVP Comp.]
Under-voltage
detecting voltage
VUVP
4, 9
65
70
75
%
Hysteresis width
VHUVP
4, 9
—
—
10*
—
%
tUVP
—
—
100
150
200
µs
TOTPH
—
—
—
150*
—
°C
TOTPL
—
—
—
125*
—
°C
High-side output
on-resistance
ROH
24,13
DRVH1, DRVH2 =
− 100 mA
—
4
6
Ω
ROL
24,13
DRVH1, DRVH2 = 100 mA
—
1
1.5
Ω
Low-side output
on-resistance
ROH
22,15
DRVL1, DRVL2 =
− 100 mA
—
4
6
Ω
ROL
22,15
DRVL1, DRVL2 = 100 mA
—
1
1.5
Ω
ISOURCE
24,13
22,15
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2 = 2.5 V
Duty ≤ 5%
—
− 0.5*
—
A
ISINK
24,13
22,15
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2 = 2.5 V
Duty ≤ 5%
—
0.9*
—
A
15
25
35
ns
35
50
65
ns
Over Current
Detection
Block
[ILIM Comp.]
Overtemperature
Protection
Circuit Block
[OTP]
Detection delay time
Protection
temperature
Output source
current
Output Block
[DRV]
Output sink current
Dead time
tD
For REF1, REF2 voltage
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVL1, DRVL2-low to
24 to 22 DRVH1, DRVH2-on
13 to 15 LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2-low to
DRVL1, DRVL2-on
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CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
Parameter
Output Block
[DRV]
Switching
Frequency
Control Block
[FREQ]
PFM Control
Circuit Block
[MODE]
Symbol
Value
Unit
Min
Typ
Max
0.75
0.85
0.95
V
LX1, LX2 = 0 V,
BST1, BST2 = 5.2 V
11
15
22
µA
VF
1,12 IF = 10 mA
Bias current
IBST
1,12
Preset value 1
conditions
VFREQ1
7
FREQ pin:
GND connection
0
—
0.2
V
Preset value 2
conditions
VFREQ2
7
FREQ pin: OPEN
0.6
—
1.2
V
Preset value 3
conditions
VFREQ3
7
FREQ pin: VB connection
2.4
—
VB
V
FREQ pin
output voltage
VFREQ
7
FREQ = OPEN
0.63
0.9
1.17
V
PFM/PWM mode
conditions
PAF function
negate
VPFM1
17
MODE pin:
GND connection
0
—
0.2
V
PFM/PWM mode
conditions
PAF function
assert
VPFM2
17
MODE pin : OPEN
0.6
—
1.2
V
PWM-fixed mode
conditions
VPWM
17
MODE pin : VB connection
4.6
—
VB
V
fPAF
—
Ta = − 30°C to +85°C
30
45
—
kHz
VMODE
17
MODE = OPEN
0.63
0.9
1.17
V
MODE pin voltage
Power Supply
Current
Condition
BST diode voltage
PAF frequency
Enable Block
[EN1 , EN2]
Pin
No.
ON condition
VON
2, 11 EN1, EN2 pins
2.64
—
—
V
OFF condition
VOFF
2, 11 EN1, EN2 pins
—
—
0.66
V
Hysteresis width
VH
2, 11 EN1, EN2 pins
—
0.4*
—
V
Input current
IEN
2, 11 EN1, EN2 = 5V
11
15
22
µA
Standby current
ICCS
Power supply
current during idle
period
Power supply
current during
operation
ICC1
ICC2
19
EN1, EN2 = 0V
—
0
10
µA
19
LX1, LX2 = 0 V
BST1, BST2 :
VB connection
FB1, FB2 = 0.75 V
—
600
860
µA
19
LX1, LX2 = 0V
BST1, BST2 :
VB connection
FB1, FB2 = 0.6 V
—
1200
1700
µA
*: This parameter is not be specified. This should be used as a reference to support designing the circuits.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
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D a t a S h e e t
 TYPICAL CHARACTERISTICS
Power dissipation vs. Operating ambient temperature
Power dissipation PD (mW)
2000
1500
1282
1000
500
0
-50 -25 +0 +25 +50 +75 +100+125
Operating ambient temperature Ta (°C)
VB bias voltage vs. Operating ambient temperature
VB bias voltage vs. VB bias output current
5.4
5.40
5.36
Ta = +25 °C
5.3
5.28
5.24
5.20
5.16
5.12
VCC=12V
IVB=0A
5.08
VB bias voltage VVB (V)
VB bias voltage VVB (V)
5.32
5.2
VCC=12V
5.1
VCC=28V
5.04
VCC=6V
5.00
5.0
0
+20 +40 +60 +80 +100
-30
-15
-10
-5
0
Error Comp. Threshold voltage vs.
Operating ambient temperature
ILIM pin current vs. Operating ambient temperature
-3.5
-4.0
0.702
0.701
0.700
0.699
0.698
0.697
0.696
0.695
-4.5
-5.0
-5.5
-6.0
-40 -20 0 +20 +40 +60 +80+100
Operating ambient temperature Ta (°C)
CONFIDENTIAL
-20
VB bias output current IVB (mA)
0.705
0.704
0.703
10
-25
Operating ambient temperature Ta (°C)
ILIM pin current IILIM (µA)
Error Comp. Threshold voltage VTH (V)
-40 -20
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
DRVH2 on time vs. Operating ambient temperature
500
450
350
250
150
FREQ=VB
50
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
DRVH1 minimum on time vs. Input voltage
DRVH2 minimum on time vs. Input voltage
200
Ta = + 25°C
200
FREQ=GND
150
FREQ=OPEN
100
50
FREQ=VB
DRVH2 minimum on time tONMIN1 (ns)
DRVH1 minimum on time tONMIN1 (ns)
FREQ=OPEN
200
100
250
0
Ta = + 25°C
150
FREQ=GND
100
FREQ=OPEN
50
FREQ=VB
0
5
10
15
20
25
30
5
20
25
DRVH1 minimum on time vs.
Operating ambient temperature
DRVH2 minimum on time vs.
Operating ambient temperature
30
FREQ=GND
VCC=12V
VOUT1= 0 V
FREQ=OPEN
80
60
FREQ=VB
40
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
January 31, 2014, MB39A214A-DS405-00007-2v1-E
DRVH2 minimum on time tONMIN2 (ns)
140
120
100
15
Input voltage VIN (V)
160
140
10
Input voltage VIN (V)
180
DRVH1 minimum on time tONMIN1 (ns)
VCC=12V
VOUT2=1.5V
300
Operating ambient temperature Ta (°C)
CONFIDENTIAL
FREQ=GND
400
DRVH2 on time tON2 (ns)
DRVH1 on time tON1 (ns)
DRVH1 on time vs. Operating ambient temperature
700
650
600
FREQ=GND
550
500
VCC=12V
450
VOUT1=1.5V
400
350
FREQ=OPEN
300
250
200
150
FREQ=VB
100
-40 -20 0 +20 +40 +60 +80 +100
120
FREQ=GND
100
VCC=12V
VOUT2=0 V
80
FREQ=OPEN
60
40
FREQ=VB
20
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
11
D a t a S h e e t
Minimum off time vs.
Operating ambient temperature
Minimum off time vs. Input voltage
600
600
550
Ta = + 25°C
500
Minimum off time tOFFMIN (ns)
Minimum off time tOFFMIN (ns)
550
450
400
350
300
250
200
5
10
15
20
25
VCC=12V
500
450
400
350
300
250
200
-40 -20
30
0
+20 +40 +60 +80 +100
Input voltage VIN (V)
Operating ambient temperature Ta (°C)
Dead time vs. Operating ambient temperature
Bootstrap diode IF vs. VF
100
60
55
tD2
10
Ta =+ 85°C
45
40
LX=0V
VBST=VB
35
30
IF current IF (mA)
Dead time (ns)
50
1
Ta = - 30°C
0.1
Ta =+25°C
0.01
tD1
25
20
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
0.001
0.2
0.4
0.6
0.8
1
1.2
VF voltage VF (V)
tD1 : Period from DRVL off to DRVH on
tD2 : Period from DRVH off to DRVL on
12
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 FUNCTION
Bottom detection comparator system for low output voltage ripple
The bottom detection comparator system for low output voltage ripple determines the ON time (tON) using
the input voltage (VIN) and output voltage (VOUT) to hold the ON state to a specified period. During the OFF
period, the reference voltage (INTREF) is compared with the feedback voltage (FB) using the error
comparator (Error Comp.). When the feedback voltage (FB) is below the reference voltage (INTREF) ,
RS-FF is set and the ON period starts again. Switching is repeated as described above. Error Comp. is used
to compare the reference voltage (INTREF) with the feedback voltage (FB) to control the off-duty condition
in order to stabilize the output voltage.
This system adds the inductor current slope detected during the synchronous rectification period (tOFF) to
the reference voltage (INTREF) , and generates an output voltage slope during the OFF period, which is
essential for the bottom detection comparator system, in the IC. This enables the stable control operations
under the low output voltage ripple conditions.
 Circuit diagram
VOUT VIN
Bias
Reg.
VIN
tON
generator
Hi-side
Drive
tON
RS-FF
R Q RS out
<Error Comp.>
FB
INTREF
S
+
DRVH
Drive
Logic
IL
VOUT
Bias
Lo-side
Drive
+
-
DRVL
VREF
Slope
Detector
 Waveforms
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
13
D a t a S h e e t
(1) Bias Voltage Block (VB Reg.)
The 5.2 V (Typ) bias voltage is generated from the VCC pin voltage for the control, output, and boost
circuits. When either or both of the EN1 pin (pin 2) and EN2 pin (pin 11) are set to the “H” level, the
system is restored from the standby state to supply the bias voltage from the VB pin (pin 18).
(2) ON/OFF Time Generator Block (tON Generator)
This block contains a capacitor for timing setting and a resistor for timing setting and generates ON time
(tON) which depends on input voltage and output voltage. The switching frequency can be switched by
setting the FREQ pin (pin 7) to any one of GND connection, OPEN, and VB connection. ON time for each
CH is obtained from the following formula.
<FREQ pin : GND connection>
tON1 (ns) =
VVOUT1
 4300 (fOSC1
VVIN
230 kHz)
tON2 (ns) =
VVOUT2
 3200 (fOSC2
VVIN
310 kHz)
<FREQ pin : OPEN>
tON1 (ns) =
VVOUT1
 2100 (fOSC1
VVIN
460 kHz)
tON2 (ns) =
VVOUT2
 1600 (fOSC2
VVIN
620 kHz)
<FREQ pin : VB connection>
tON1 (ns) =
VVOUT1
 1300 (fOSC1
VVIN
750 kHz)
tON2 (ns) =
VVOUT2
 1000 (fOSC2
VVIN
1000 kHz)
The switching frequency of CH2 is set to 1.33 times that of CH1 to prevent the beat by the frequency
difference of channel to channel.
(3) Output Block (DRV1, DRV2)
The output circuit is configured in CMOS type for both of the high-side and the low-side. It provides the
0.5 A (Typ) source current and 0.9 A (Typ) sink current, drive the external N-ch MOS FET. The output
circuit of the high-side FET supplies the power from the boost circuit including the built-in boost diode. The
output circuit of the low-side FET supplies the power from the VB pin. This circuit monitors the gate
voltages of the high-side and low-side FETs. Until either FET is turned off, this circuit controls the ON
timing of another FET, preventing the shoot-through current. The sink ON resistance of the output circuit is
low 1 Ω (Typ), improve the self turn on margin of low-side FET.
14
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
(4) Starting sequence
When the EN1 pin (pin 2) or EN2 pin (pin 11) is set to the “H” level, the bias voltage is supplied from the
VB pin. If the voltage of the VB pin exceeds the UVLO threshold voltage, the DC/DC converter starts
operations and carries out the soft start. The soft start is a function used to prevent a rush current when the
power is started.
Activating the soft start initiates charging of the capacitor connected to the CS1 pin (pin 5) and CS2 pin (pin
8) and inputs the lamp voltage to the error comparator (Error Comp.) of each channel. The DC/DC
converter generates the output voltage according to that lamp voltage. This results in the soft start operation
that does not depend on the output load. The over voltage protection (OVP) and under voltage protection
(UVP) functions are disabled while the soft start is active.
<Timing chart>
UVLO release
CH1 soft start completed
CH2 soft start completed
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
15
D a t a S h e e t
(5) DC/DC converter stop sequence (Discharge, standby)
When the EN1 pin (pin 2) or EN2 pin (pin 11) is set to the “L” level, the output capacitor is discharged
using the discharge FET (RON
25 Ω) in the IC. If the voltage of the VOUT1 pin (pin 3) and VOUT2 pin
(pin 10) is below 0.2 V (Typ) by discharging the output capacitor, the IC stops discharge operation. Further,
if both the EN1 and EN2 pins are set to the “L” level, the IC also stops the output of the VB pin and enters
the standby state after detecting UVLO. The current of the VCC pin (IVCC) is then 10 µA (Max).
<Timing chart>
Standby
CH1 discharge FET ON
CH2 discharge FET ON
(6) Under Voltage Lockout Protection (UVLO)
The under voltage lockout protection (UVLO) protects ICs from malfunction and protects the system from
destruction/deterioration, according to the reasons mentioned below.
 Transitional state when the bias voltage (VB) or the reference voltage (VREF) starts.
 Momentary decrease
To prevent such a malfunction, this function detects a voltage drop of the VB pin (pin 18) using the
comparator (UVLO Comp.), and stops IC operations.
When the VB pin exceeds the threshold voltage of the under voltage lockout protection circuit, the system
is restored.
16
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
(7) Over Current Limitation (ILIM)
This function limits the output current when it has increased, and protects devices connected to the output.
This function detects the inductor current IL from the electromotive force of the low-side FET on-resistance
RON, and compares this voltage with the 1/5-time value of the voltage VILIM of the ILIM1 pin (pin 20) and
ILIM2 pin (pin 16) on a cyclically, using ILIM Comp. Until this voltage falls below the over current limit
value, the high-side FET is held in the off state. After the voltage has fallen below the limit value, the
high-side FET is placed into the on state. This limits the lower bound of the inductor current and also
restricts the over current. As a result, it becomes operation that the output voltage droops.
The over current limit value is set by connecting the resistor to the ILIM pin. The ILIM pin supplies the
constant current of 5 µA (Typ) . However, the current value has a temperature slope up to 4500 ppm/°C to
compensate the temperature dependence characteristics of the low-side FET on-resistance.
ILIM detection value (RON × IL =
VILIM
5
)
Keep the off state of the high-side FET
until the detection value is gained.
Output voltage setting value
Normal operation
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
Over current limit operation
17
D a t a S h e e t
(8) Over Voltage Protection (OVP)
This function stops the output voltage when the output voltage has increased, and protects devices
connected to the output.
1. Using OVP Comp, this function makes a comparison between the voltage which is 1.15 times (Typ) of
the internal reference voltage INTREF1 and INTREF2 (0.7 V), and the feedback voltage for the FB1
pin (pin 4) and the FB2 pin (pin 9).
2. If the feedback voltage mentioned in 1 detects the higher state by 15µs (Typ) or more, the operations
below will be performed.
 Set the RS latch.
 Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.
 Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “H” level.
These operations fix the high-side FET to the off state and the low-side FET to the on state for both
channels of the DC/DC converter, and stops switching (latch stop).The over-voltage protection state can be
cancelled by setting both the EN1pin (pin 2) and EN2 pin (pin 11) to the “L” level or reducing the VCC
power once until the bias voltage (VB) falls below VTHL of UVLO.
<Timing chart>
Output voltage
setting value
INTREF1.15
INTREF1.10
Output voltage
setting value
Standby
Less than 15 µs
Cancellation of over-voltage protection
state by EN = "L".
18
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
(9) Under Voltage Protection (UVP)
This function stops the output voltage when the output voltage has lowered, and protects devices connected
to the output.
1. Using UVP Comp, this function makes a comparison between the voltage which is 0.7 times (Typ) of
the internal reference voltage REF1, REF2 (0.7 V), and the feedback voltage for the FB1 pin (pin 4) and
the FB2 pin (pin 9).
2. If the feedback voltage mentioned in 1 detects the higher state by 150µs (Typ) or more, the operations
below will be performed.
 Set the RS latch.
 Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.
 Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “L” level.
These operations fix the high-side FET to the off state and the low-side FET to the off state for both
channels of the DC/DC converter, and stops switching (latch stop). The discharge operation is then carried
out to discharge the output capacitor (The discharge operation continues until the state of the under-voltage
protection is released).
The under-voltage protection state can be cancelled by setting both the EN1 pin (pin 2) and EN2 pin (pin 11)
to the “L” level or reducing the VCC power once until the bias voltage (VB) falls below VTHL of UVLO.
<Timing chart>
Output voltage
setting value
INTREF  0.8
INTREF 0.7
Output voltage
setting value
Standby
Less than 150 µs
Cancellation of over-voltage protection state by EN = "L".
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
19
D a t a S h e e t
(10) Over Temperature Protection (OTP)
The over-temperature protection circuit block (OTP) provides a function that prevents the IC from a thermal
destruction. If the junction temperature reaches + 150°C, the DRVH1 pin (pin 24) and DRVH2 pin (pin 13)
are set to the “L” level, and the DRVL1 pin (pin 22 ) and DRVL2 pin (pin 15) are set to the “L” level. This
fixes the high-side and low-side FETs to the off-state, of both channels in the DC/DC converter, causing
switching to be stopped. The discharge operation is then carried out to discharge the output capacitor (The
discharge operation continues until the state of the over-temperature protection is released). If the junction
temperature drops to + 125°C, the soft start is reactivated. (Restored automatically.)
(11) Operation mode
In the PWM-fixed mode, the system acts by the switching frequency specified with the FREQ pin
regardless of the load.
In the automatic PFM/PWM selection mode, the switching frequency is reduced at low load, for enhancing
the conversion efficiency characteristics. This function detects 0 A of the inductor current from the
electromotive force of the low-side FET ON resistance when the low-side FET ON state, and places the
low-side FET into the off state. This idle period continued until the output voltage decreased, this results the
switching frequency being reduced automatically depending on the load current when the inductor current
is below the critical current. The system acts by the switching frequency specified with the FREQ pin, when
the inductor current exceeds the critical current.
For Automatic PFM/PWM selection mode with PAF function, the switching frequency at low load is held to
30 kHz (Min) or more.
The operation mode can be switched by setting the MODE pin (pin 17) to any one of GND connection,
OPEN, and VB connection.
 PWM-fixed mode
Inductor current in the opposite
direction
 Automatic PFM/PWM selection mode
Switching frequency reduced
X : Each channel number
20
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 Enable function table
EN1 pin
EN2 pin
DC/DC converter (CH1)
DC/DC converter (CH2)
L
L
OFF
OFF
H
L
ON
OFF
L
H
OFF
ON
H
H
ON
ON
 DC/DC Control mode function table
MODE pin
DC/DC control
GND connection
Automatic PFM/PWM selection mode
OPEN
Automatic PFM/PWM selection mode with PAF function
VB connection
PWM-fixed mode
 Switching frequency control function table
FREQ pin
Switching frequency
GND connection
fOSC1
230 kHz, fOSC2
310 kHz
OPEN
fOSC1
460 kHz, fOSC2
620 kHz
VB connection
fOSC1
750 kHz, fOSC2
1000 kHz
 Protection function table
The following table shows the state of the VB pin (pin 18), the DRVH1 pin (pin 24), the DRVH2 pin (pin
13), the DRVL1 pin (pin 22), the DRVL2 pin (pin 15) when each protection function operates.
Protection
function
Under Voltage
Lockout Protection
(UVLO)
Detection condition
Output of each pin
after detection
VB
DRVH1, DRVL1,
DRVH2 DRVL2
DC/DC output
dropping operation
Natural electric
discharge
VB < 4.0 V
—
Over-current
limitation
(ILIM)
VPGND - VLX1, VLX2 >
VILIM1, VILIM2
5.2 V
Over Voltage
Protection
(OVP)
VFB1, VFB2 >
INTREF1, INTREF21.15
(15 µs or higher)
5.2 V
L
H
0 V clamping
Under Voltage
Protection
(UVP)
VFB1, VFB2 >
INTREF1, INTREF20.7
(150 µs or higher)
5.2 V
L
L
Electrical discharge by
discharge function
Tj > + 150 °C
5.2 V
L
L
Electrical discharge by
discharge function
EN1, EN2: H → L
(VOUT1, VOUT2 > 0.2 V)
5.2 V
L
L
Electrical discharge by
discharge function
Over Temperature
Protection
(OTP)
Enable
(EN)
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
L
L
Switching Switching
The voltage is dropped
by the constant current
21
D a t a S h e e t
 I/O PIN EQUIVALENT CIRCUIT DIAGRAM
FB1, FB2 pins
EN1, EN2 pins
ESD protection
element
ESD protection
element
FREQ pin
MODE pin
ILIM1, ILIM2 pins
VOUT1, VOUT2 pins
22
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
CS pin
DRVL1, DRVL2 pins
DRVH1, DRVH2, BST1, BST2, LX1, LX2 pins
VB pin
VCC pin
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
23
D a t a S h e e t
 EXAMPLE APPLICATION CIRCUIT
VIN
VCC
VIN
R1-2 R1-1
C7
3 VOUT1
PGND
VB 18
C8
FB1
R2
4
12 V
19
4
R5
3
1.0 V, 7 A
L1
VOUT1
2
+
PGND
C2-3
DRVL1 22
Q1 7 8
C2-1
17 MODE
C14
LX1 23
R23
C12
20 ILIM1
Q1 5 6
C1-1
DRVH1 24
C1-2
EN1
5 CS1
C5
2
EN1
VIN
BST1 1
1
7 FREQ
MB39A214A
R3-2 R3-1
10 VOUT2
VIN
BST2 12
3
C3-2
C6
4
C3-1
Q3 5 6
R4
9 FB2
DRVH2 13
1.8 V, 7 A
L2
VOUT2
PGND
6
24
CONFIDENTIAL
2
ILIM2
R6
C13
16
1
PGND
C4-3
DRVL2 15
+
C4-1
8 CS2
Q3 7 8
R24
11 EN2
EN2
C15
LX2 14
21
GND
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 PART LIST
Component
Item
Package
Part number
Remarks
Q1
VDS = 30 V, ID = 6.3 A, 8.6 A,
N-ch FET
FAIRCHILD
RON = 23 mΩ, 13 mΩ
Specification
Vendor
SOP8
FDS6982AS
DualType
(2elements)
Q3
N-ch FET
VDS = 30 V, ID = 6.3 A, 8.6 A,
FAIRCHILD
RON = 23 mΩ, 13 mΩ
SOP8
FDS6982AS
DualType
(2elements)
L1
Inductor
1 µH (18 A)
NEC TOKIN
-
MPC1055L1R0
L2
Inductor
1.5 µH (12.4 A)
NEC TOKIN
-
MPLC1040L1R5
C1-1
Ceramic
capacitor
10 µF (25 V)
MURATA
3216
GRM31CB31E106K
C1-2
Ceramic
capacitor
10 µF (25 V)
MURATA
3216
GRM31CB31E106K
C2-1
POSCAP
220 µF (2 V)
SANYO
D case
2TPLF220M6
C2-3
Ceramic
capacitor
1000 pF (50 V)
TDK
1608
C1608JB1H102K
C3-1
Ceramic
capacitor
10 µF (25 V)
MURATA
3216
GRM31CB31E106K
C3-2
Ceramic
capacitor
10 µF (25 V)
MURATA
3216
GRM31CB31E106K
C4-1
POSCAP
150 µF (6.3 V)
SANYO
D case
6TPL150MU
C4-3
Ceramic
capacitor
1000 pF (50 V)
TDK
1608
C1608JB1H102K
C5
Ceramic
capacitor
0.1 µF (50 V)
TDK
1608
C1608JB1H104K
C6
Ceramic
capacitor
0.1 µF (50 V)
TDK
1608
C1608JB1H104K
C7
Ceramic
capacitor
0.1 µF (50 V)
TDK
1608
C1608JB1H104K
C8
Ceramic
capacitor
4.7 µF (16 V)
TDK
1608
C1608JB1C475K
C12
Ceramic
capacitor
3300 pF (50 V)
TDK
1608
C1608JB1H332K
C13
Ceramic
capacitor
3300 pF (50 V)
TDK
1608
C1608JB1H332K
C14
Ceramic
capacitor
1500 pF (50 V)
TDK
1608
C1608JB1H152K
C15
Ceramic
capacitor
1500 pF (50 V)
TDK
1608
C1608JB1H152K
R1-1
Resistor
1.5 kΩ
SSM
1608
RR0816P152D
R1-2
Resistor
27 kΩ
SSM
1608
RR0816P273D
R2
Resistor
68 kΩ
SSM
1608
RR0816P683D
R3-1
Resistor
4.3 kΩ
SSM
1608
RR0816P432D
R3-2
Resistor
56 kΩ
SSM
1608
RR0816P563D
R4
Resistor
39 kΩ
SSM
1608
RR0816P393D
R5
Resistor
150 kΩ
SSM
1608
RR0816P154D
R6
Resistor
150 kΩ
SSM
1608
RR0816P154D
R23
Resistor
1.8 Ω
KOA
1608
RK73H1JTTD1R8F
R24
Resistor
1Ω
KOA
1608
RK73H1JTTD1R0F
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
25
D a t a S h e e t
FAIRCHILD
SANYO
NEC TOKIN
TDK
MURATA
SSM
26
CONFIDENTIAL
: Fairchild Semiconductor Corporation
: SANYO Electric Co., Ltd. / Panasonic
: NEC TOKIN Corporation
: TDK Corporation
: Murata Manufacturing Co., Ltd.
: SUSUMU Co.,Ltd.
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 APPLICATION NOTE
1. Setting Operating Conditions
Setting output voltages
The output voltage can be set by adjusting the setting output voltage resistor ratio. Setting output voltage is
calculated by the following formula.
VOUTx =
R1 + R2
R2
 (0.6946 + 0.2667ΔIL (1−
ΔVOUTx = ESR ΔIL, ΔIL =
VOUTx
VIN
ΔVOUTX
tOFF
RON_Sync
ΔIL
ESR
L
fOSC
VIN − VOUT
L

2.810-7
tOFF
VOUT
VIN  fOSC
, tOFF
=
) RON_Sync) +
ΔVOUTx
2
(VIN − VOUTx)
VINfOSC
: Output setting voltage [V]
: Power supply voltage [V]
: Output ripple voltage value [V]
: Off time [s]
: ON resistance of low-side FET [Ω]
: Ripple current peak-to-peak value of inductor [A]
: Series resistance element of output capacitor [Ω]
: Inductor value [H]
: Switching frequency [Hz]
VOUTX
VOUTx
R1
FBX
R2
x: Each channel number
The total resistor value (R1+R2) of the setting output resistor should be selected up to 100 kΩ.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
27
D a t a S h e e t
Minimum power supply voltage
The maximum on duty is limited by "the minimum off time (tOFFMIN) that an IC holds without fail as a fixed
value" and "the on time (tON) determined by the power voltage value and the output voltage setting value".
The ratio between the output voltage and the power voltage must be less than the maximum on duty.
The minimum power supply voltage that is required to sustain the output voltage can be calculated by the
following formula.
VIN_MIN =
(VOUT + IOUT_MAX  (RDC + RON_Main))  VOUT
VOUT − (VOUT + IOUT_MAX  (RDC + RON_Sync))  tOFF_MIN  fOSC 1.2
VIN_MIN
: Power supply voltage [V]
VOUT
: Output setting voltage [V]
IOUT_MAX : Maximum load current value [A]
RON_Main
: ON resistance of high-side FET [Ω]
RON_Sync
: ON resistance of low-side FET [Ω]
RDC
: Series resistance of inductor [Ω]
fOSC
: Switching frequency setting value [Hz]
tOFF_MIN
: Minimum off time (Maximum value) [s]
(For the minimum off time, see “ON/OFF Time [Minimum OFF time ] ” in
“ELECTRICAL CHARACTERISTICS”.)
Use the smaller switching frequency setting in order to make the voltage output possible with the lower
power voltage.
Slope voltages
It is necessary to sustain the Slope voltage 15 mV or higher in order to obtain the stable switching cycle.
The Slope voltage can be calculated by the following formula.
VSlope =
28
CONFIDENTIAL
(VIN − VOUT)  VOUT  RON_Sync
L  VIN  fOSC
VSlope
: Slope voltage [V]
VIN
: Power supply voltage [V]
VOUT
: Output setting voltage [V]
fOSC
: Switching frequency [Hz]
RON_Sync
: ON resistance of low-side FET [Ω]
L
: Inductor value [H]
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
Setting soft-start time
Calculate the soft-start time by the following formula.
ts = 7  105  CCS
ts
CCS
: Soft-start time [s] (time until output reaches 100%)
: CS pin capacitor value [F]
Calculate the delay time until the soft-start activation by the following formula.
td = 43  CVB
td
: VB voltage delay time (at VIN = 12 V) [s]
CVB : VB pin capacitor value [F]
When activating the other in the state where a side channel has already been activated (UVLO release: VB
output already), the delay time is hardly generated.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
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29
D a t a S h e e t
Setting switching frequency
The switching frequency is set at the FREQ pin. As for the setting process, see the switching frequency
control function table.
Setting over current limitation
The over current limitation value can be set by adjusting the over current limitation setting resistor value
connected to the ILIM pin.
Calculate the resistor value by the following formula.
RLIM = 106  RON_Sync  (ILIM −
RLIM
ILIM
ΔIL
2
)
ΔIL
: Over current limitation value setting resistor [Ω]
: Over current limitation value [A]
: Ripple current peak-to-peak value of inductor [A]
RON_Sync
: ON resistance of low-side FET [Ω]
ILIM
RLIM
Inductor current
ΔIL
Over current
limitation value
Time
If the rate of inductor saturation current is small, the inductor value decreases and the ripple current of
inductor increase when the over-current flows. At that time there is a possibility that the limited output
current increases or is not limited, because the bottom of inductor current is detected. It is necessary to use
the inductor that has enough large rate of inductor saturation current to prevent the overlap current.
30
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
The over current limit value is affected by ILIM pin source current and over current detection offset voltage
in the IC except for the on resistance of the low-side FET and the inductor value. The variation of dropped
over current limit value caused by IC characteristics is calculated by the following formula.
ΔILIM =
2 10-7 RLIM + 0.03
RON_Sync
ΔILIM
RLIM
: The variation of dropped over current limit value [A]
: Over current limitation value setting resistor [Ω]
RON_Sync
: ON resistance of low-side FET [Ω]
Inductor current
Over current limit value
ΔILIM
Dropped over current limit value due to
IC's characteristics
Time
The over current detection value needs to set a sufficient margin against the maximum load current.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
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31
D a t a S h e e t
Power dissipation and the thermal design
IC's loss increases, if IC is used under the high power supply voltage, high switching frequency, high load
and high temperature. The IC internal loss can be calculated by the following formula.
PIC = VCC  (ICC + QG_Total1  fOSC1 + QG_Total2  fOSC2)
PIC
: IC internal loss [W]
VCC
: Power supply voltage (VIN) [V]
ICC
: Power supply current [A] (2 mA Max)
QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
fOSC1
: CH1 switching frequency [Hz]
fOSC2
: CH2 switching frequency [Hz]
Calculate junction temperature (Tj) by the following formula.
Tj = Ta + θja  PIC
Tj
Ta
θja
PIC
: Junction temperature [°C] (+ 125°C Max)
: Ambient temperature [°C]
: TSSOP-24P Package thermal resistance (+ 78°C /W)
: IC internal loss [W]
Handling of the pins when using a single channel
Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel
DC/DC converter by handling the pins of the unused channel as shown in the following diagram.
VOUTx
FBx
CSx
ILIMx
ENx
LXx
BSTx
“Open”
DRVHx
“Open”
DRVLx
“Open”
Note: x is the unused channel number.
32
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
2. Selecting parts
Selection of smoothing inductor
The inductor value selects the value that the ripple current peak-to-peak value of the inductor is 50% or less
of the maximum load current as a rough standard. Calculate the inductor value in this case by the following
formula.
L≥
VIN −VOUT
LOR IOUT_MAX

VOUT
VIN fOSC
L
: Inductor value [H]
IOUT_MAX
: Maximum load current [A]
LOR
: Ripple current peak-to-peak value of inductor/Maximum load current ratio (= 0.5)
VIN
: Power supply voltage [V]
VOUT
: Output setting voltage [V]
fOSC
: Switching frequency [Hz]
It is necessary to calculate the maximum current value that flows to the inductor to judge whether the
electric current that flows to the inductor is a rated value or less. Calculate the maximum current value of
the inductor by the following formula.
ILMAX ≥ IOUT_MAX +
ILMAX
ΔIL
2
: Maximum current value of inductor [A]
IOUT_MAX : Maximum load current [A]
ΔIL
: Ripple current peak-to-peak value of inductor [A]
L
: Inductor value [H]
VIN
: Power supply voltage [V]
VOUT
: Output setting voltage [V]
fOSC
: Switching frequency [Hz]
Inductor current
ΔIL
Time
January 31, 2014, MB39A214A-DS405-00007-2v1-E
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33
D a t a S h e e t
Selection of Switching FET
If selecting the high-side FET so that the value of the high-side FET conduction loss and the high-side FET
switching loss is same, the loss is effectively decreased.
Confirm that the high-side FET loss is within the rating value.
PMainFET = PRON_Main + PSW_Main
PMainFET
: High-side FET loss [W]
PRON_Main : High-side FET conduction loss [W]
PSW_Main
: High-side FET switching loss [W]
High-side FET conduction loss
PRON_Main = IOUT_MAX2 
VOUT
 RON_Main
VIN
PRON_Main : High-side FET conduction loss [W]
IOUT_MAX : Maximum load current [A]
VIN
VOUT
: Power supply voltage [V]
: Output voltage [V]
RON_Main : ON resistance of high-side FET [Ω]
The high-side FET switching loss can be calculated roughly by the following formula.
PSW_Main
1.56  VIN  fOSC  IOUT_MAX  QSW
PSW_Main : Switching loss [W]
VIN
fOSC
: Power supply voltage [V]
: Switching frequency [Hz]
IOUT_MAX : Maximum load current [A]
QSW
: Amount of high-side FET gate switch electric charge [C]
MOSFET has a tendency where the gate drive loss increases because the lower drive voltage product has
the bigger amount of gate electric charge (QG). Normally, we recommend a 4 V drive product, however, the
idle period at light load (both the high-side FET and the low-side FET is off-period) gets longer and the gate
drive voltage of the high-side FET may decrease, in the automatic PFM/PWM selection mode. The voltage
drops most at no-load mode. At this time, confirm that the boost voltage (voltage between BST-LX pins) is
a big enough value for the gate threshold value voltage of the high-side FET.
If it is not enough, consider adding the boost diode, increasing the capacitor value of the boost capacitor or
using a 2.5 V (or 1.8 V) drive product to the high-side FET.
Select the ON resistance of low-side FET from the range below.
0.2
RON_Sync ≤
(ILIM −
CONFIDENTIAL
2
)
0.1
ΔIL
, RON_Sync ≥
0.015
ΔIL
RON_Sync
: ON resistance of low-side FET [Ω]
ΔIL
: Ripple current peak-to-peak value of inductor [A]
: Over current detection value [A]
ILIM
34
ΔIL
, RON_Sync ≤
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
If the formula above has been already satisfied and then a low ON resistance FET as possible is used for the
low-side FET, the loss is effectively decreased. Especially, it works dramatically in the low on duty mode.
The loss of the low-side FET can be calculated by the following formula.
PSyncFET = PRON_Sync = IOUT_MAX2  (1 –
PSyncFET
VOUT
)  RON_Sync
VIN
: Low-side FET loss [W]
PRON_Sync : Low-side FET conduction loss [W]
IOUT_MAX : Maximum load current [A]
VIN
: Power supply voltage [V]
VOUT
: Output voltage [V]
RON_Sync
: ON resistance of low-side FET [Ω]
Turn-on and turn-off voltage of the low-side FET is generally small and the switching loss is small enough
to ignore, so that is omitted here.
Especially, when turning on the high-side FET under the high power supply voltage condition, the
rush-current might be generated by according to self-turn-on of the low-side FET. The parasitic capacitor
value of the low-side FET needs to satisfy the following conditions.
VTH_Sync >
Crss
VIN
Ciss
VTH_Sync
: Threshold voltage of low-side FET [V]
Crss
Ciss
VIN
: Parasitic feedback capacitance of low-side FET [F]
: Parasitic input capacitance of low-side FET [F]
: Power supply voltage [V]
Also approaches of adding a capacitor close between the gate source pins of the low-side FET or adding
resistor between the BST pin and the boost capacitor, and so on are effective as a countermeasure of the
self-turn-on(adding resistor between the BST pin and the boost capacitor is also effective to adjust turn-on
time of the high-side FET).
This device monitors the gate voltage of the switching FET and optimizes the dead time. If the dumping
resistor is inserted among DRVH, DRVL and the switching FET gate to adjust turn-on and turn-off time of
the switching FET, this function might malfunction. In this device, resistor should not be connected among
the DRVH pin, the DRVL pin of IC and the switching FET gate, and should be connected by low
impedance as possible.
The gate drive power of the switching FET is supplied from LDO (VB) of IC inside. Select switching FET
so that the total amount of the switching FET electric charge for 2 channels (QG_Total1, QG_Total2)
satisfies the following formula.
IVB_MAX > QG_Total1  fOSC1 + QG_Total2  fOSC2
IVB_MAX
: VB load current upper limit value (see the following graph) [A]
QG_Total1
: Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
QG_Total2
: Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
fOSC1
: CH1Switching frequency [Hz]
fOSC2
: CH2 Switching frequency [Hz]
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
35
D a t a S h e e t
VB load current upper limit value [A]
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
6 8 10 12 14 16 18 20 22 24 26 28
VIN [V]
Moreover, select the total quantity of the high-side FET electric charge as a guide that does not exceed the
total quantity of the high-side FET electric charge upper limit value shown below.
The total quantity upper limit of electric
charge of the high-side FET QG_MAX [nC]
35
From the top line
FREQ=GND:CH1
FREQ=GND:CH2
FREQ=OPEN:CH1
FREQ=OPEN:CH2
FREQ=VB:CH1
FREQ=VB:CH2
30
25
20
15
10
5
0
5
10
15
20
25
30
Power supply voltage VIN [V]
Whether the mean current value that flows to switching FET is a rated value or less of switching FET is
judged. Each rating value for the switching FET can be calculated roughly by the following formula.
ID_Main > IOUT_MAX  D
ID_Sync > IOUT_MAX  (1 – D)
ID_Main
: high-side FET drain current [A]
ID_Sync
: Low-side FET drain current [A]
IOUT_MAX : Maximum load current [A]
D
: On-duty
VDSS > VIN
VDSS
VIN
36
CONFIDENTIAL
: Voltage between the high-side FET drain and source and the low-side FET drain and
source [V]
: Power supply voltage [V]
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
Selection of fly-back diode
This device is improved by adding the fly-back diode when the conversion efficiency improvement or the
suppression of the low-side FET fever is desired, although those are unnecessary to execute normally. The
effect is achieved in the condition where the switching frequency is high or output voltage is lower. Select
schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the
period for the electric current flow into fly-back diode is limited to dead time period because the
synchronous rectification system is adopted. (as for the dead time, see “Output Block” in “ELECTRICAL
CHARACTERISTICS”). Each rating for the fly-back diode can be calculated by the following formula.
ID ≥ IOUT_MAX fOSC  (tD1 + tD2)
ID
: Forward current rating of SBD [A]
IOUT_MAX : Maximum load current [A]
fOSC
: Switching frequency [Hz]
tD1, tD2
: Dead time [s]
IFSM ≥ IOUT_MAX +
IFSM
ΔIL
2
: Peak forward surge current ratings of SBD [A]
IOUT_MAX : Maximum load current [A]
ΔIL
: Ripple current peak-to-peak value of inductor [A]
VR_Fly > VIN
VR_Fly
: Reverse voltage of fly-back diode direct current [V]
VIN
: Power supply voltage [V]
January 31, 2014, MB39A214A-DS405-00007-2v1-E
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37
D a t a S h e e t
Selection of input capacitor
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the
tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the
ceramic capacitor can not support.
The ripple voltage is generated in the power supply voltage by the switching operation of DC/DC. Calculate
the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of
the power supply from the following formula.
ΔVIN =
IOUT_MAX
CIN
ΔVIN

VOUT
VIN  fOSC
+ ESR  (IOUT_MAX +
ΔIL
2
)
: Power supply ripple voltage peak-to-peak value [V]
IOUT_MAX : Maximum load current value [A]
CIN
VIN
VOUT
fOSC
ESR
: Input capacitor value [F]
: Power supply voltage [V]
: Output setting voltage [V]
: Switching frequency [Hz]
: Series resistance component of input capacitor [Ω]
: Ripple current peak-to-peak value of inductor [A]
ΔIL
Capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic, etc.
The effective capacitor value might become extremely small depending on the use conditions. Note the
effective capacitor value in the use conditions.
Calculate ratings of the input capacitor by the following formula:
VCIN > VIN
VCIN : Withstand voltage of the input capacitor [V]
VIN
: Power supply voltage [V]
Irms ≥ IOMAX 
Irms
IOMAX
VIN
VOUT
38
CONFIDENTIAL
√ VOUT (VIN – VOUT)
VIN
: Allowable ripple current of input capacitor (effective value) [A]
: Maximum load current value [A]
: Power supply voltage [V]
: Output setting voltage [V]
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
Selection of output capacitor
A certain level of ESR is required for stable operation of this IC. Use a tantalum capacitor or polymer
capacitor as the output capacitor. If using a ceramic capacitor with low ESR, a resistor should be connected
in series with it to increase ESR equivalently.
Calculate the output capacitor value by the following formula as a guide.
COUT ≥
1
4 fOSC  ESR
COUT
fOSC
ESR
: Output capacitor value [F]
: Switching frequency [Hz]
: Series resistance of output capacitor [Ω]
Moreover, the output capacitor values are also derived from the allowable amount of overshoot and
undershoot. The following formula is represented as the worst condition in which the shift time for a sudden
load change is 0s. The output capacitor value allow a smaller amount than the value calculated by the
following formula when a longer shift time.
COUT ≥
COUT ≥
ΔIOUT2  L
…Overshoot condition
2  VOUT  ΔVOUT_OVER
ΔIOUT2  L  (VOUT + VIN  fOSC  tOFF_MIN)
… Undershoot condition
2  VOUT  ΔVOUT_UNDER  (VIN – VOUT – VIN  fOSC  tOFF_MIN)
COUT
: Output capacitor value [F]
: Allowable amount of output voltage overshoot [V]
ΔVOUT_OVER
ΔVOUT_UNDER : Allowable amount of output voltage undershoot [V]
: Current difference in sudden load change [A]
ΔIOUT
L
VIN
VOUT
fOSC
tOFF_MIN
: Inductor value [H]
: Power supply voltage [V]
: Output setting voltage [V]
: Switching frequency [Hz]
: Minimum off time
When changing to no load suddenly, the output voltage is overshoot, however, the current sink is not
executed in the mode other than PWM fix. As a result, the decrement of the output voltage might take a
long time. This sometimes results in the stop mode because of the over voltage detection. In the mode other
than PWM fix, select the capacitor value so that the overshoot value is set to the over voltage detection
voltage value or less (115% of the output setting voltage or less).
The capacitor has frequency, operating temperature, and bias voltage characteristics, etc. Therefore, it must
be noted that its effective capacitor value may be significantly smaller, depending on the use conditions.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
39
D a t a S h e e t
Calculate each rating of the output capacitor by the following formula:
VCOUT > VOUT
VCOUT
VOUT
IRMS ≥
: Withstand voltage of the output capacitor [V]
: Output voltage [V]
ΔIL
2 3
IRMS
ΔIL
: Allowable ripple current of output capacitor (effective value) [A]
: Ripple current peak-to-peak value of inductor [A]
When connecting resistance in series configuration while a ceramic capacitor is in use, the resistor rating is
calculated by the following formula.
PESR >
ESRΔIL2
12
PESR
ESR
ΔIL
40
CONFIDENTIAL
: Power dissipation of resistor [W]
: Resistor value [Ω]
: Ripple current peak-to-peak value of inductor [A]
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
Selection of bootstrap capacitor
To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. 0.1 µF is
assumed to be standard, however, it is necessary to adjust it when the high-side FET QG is big. Consider the
capacitor value calculated by the following formula as the lowest value for the bootstrap capacitor and
select a thing any more.
CBST ≥ 10QG
CBST
QG
: Bootstrap capacitor value [F]
: Total quantity of charge for the high-side FET gate [C]
Calculate ratings of the bootstrap capacitor by the following formula:
VCBST > VB
VCBST
VB
: Withstand voltage of the bootstrap capacitor [V]
: VB voltage [V]
VB pin capacitor
4.7 µF is assumed to be a standard, and when QG of switching FET used is large, it is necessary to adjust it.
To suppress the ripple voltage by the switching FET gate drive, consider the capacitor value calculated by
the following formula as the lowest value for VB capacitor and select a thing any more.
CVB ≥ 50QG
CVB
QG
: VB pin capacitor value [F]
: Total amount of gate charge of high-side FET and low-side switching FET for 2CH [C]
Calculate ratings of the VB pin capacitor by the following formula:
VCVB > VB
VCVB
VB
: Withstand voltage of the VB pin capacitor [V]
: VB voltage [V]
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
41
D a t a S h e e t
Layout
Consider the points listed below and do the layout design.
 Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor
connected with the VCC and VB pins, and GND pin of the switching system parts with switching system
GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate
each GND, and try not to pass the heavy current path through the control system GND (AGND) as much
as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) at
the single point of GND (PGND) directly below IC. Switching system parts are Input capacitor (CIN),
Switching FET, fly-back diode (SBD), inductor (L) and Output capacitor (COUT).
 Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through-hole as much as possible.
 As for GND pins of the switching system parts, provide the through hole at the proximal place, and
connect it with GND of internal layer.
 Pay the most attention to the loop composed of input capacitor (CIN), switching FET, and fly-back diode
(SBD). Consider parts are disposed mutually to be near for making the current loop as small as possible.
 Place the bootstrap capacitor (CBST1, CBST2) proximal to BSTx and LXx pins of IC as much as possible.
 Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current
flows momentary in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.
 Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of
switching FET. Wire the linewidth of about 0.8 mm to be a standard, as short as possible. Take special
care about the line of the DRVLx pin, and wire the line as short as possible.
 By-pass capacitor (CVCC, CVB) connected with VCC, and VB should be placed close to the pin as much as
possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal
through-hole.
 Pull the feedback line to be connected to the VOUTx pin of the IC separately from near the output
capacitor pin, whenever possible. Consider the line connected with VOUTx and FBx pins to keep away
from a switching system parts as much as possible because it is sensitive to the noise.
Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to
the FBx pin. In addition, for the internal layer right under the component mounting place, provide the
control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the
power supply as much as possible.
Consider that the discharge current momentary flows into the VOUTx pin (about 200 mA at Vout = 5 V)
when the DC/DC operation stops, and then sustain the width for the feedback line.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and
parts sensitive to noise should be considered to be placed away from the inductor (or backside of place
equipped with inductor).
Layout example of IC peripheral
Layout example of switching system parts
High-side FET
High-side FET
Through-hole
Low-side FET
Low-side FET
To the LX1 pin
To the LX2 pin
Output voltage setting
resistor layout
Connect AGND and PGND right under IC
Surface
42
CONFIDENTIAL
Internal
layer
Output voltage
VOUT1 feedback
Output voltage
VOUT2 feedback
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 REFERENCE DATA
Conversion Efficiency vs.Load Current
100
90
90
80
80
Conversion Efficiency η (%)
Conversion Efficiency η (%)
Conversion Efficiency vs.Load Current
100
70
60
50
VIN = 12V
VOUT1 = 1.0V
FREQ = Open
40
30
PFM
PAF
PWM
20
10
0
0.001
0.01
0.1
1
70
60
50
VIN = 12V
VOUT2 = 1.8V
FREQ = Open
40
30
PFM
20
PAF
10
PWM
0
0.001
10
0.01
Load Current IOUT1 (A)
0.1
*: EN1 Standby mode
Switching Frequency vs. Load Current
Switching Frequency vs. Load Current
1.E+6
Switching Frequency fosc2 (kHz)
Switching Frequency fosc1 (kHz)
1.E+6
1.E+5
VIN = 12V
VOUT1 = 1.0V
FREQ = Open
1.E+4
PFM
PAF
PWM
1.E+3
0.01
0.1
1
1.E+5
VIN = 12V
VOUT2 = 1.8V
FREQ = Open
1.E+4
PFM
PAF
PWM
1.E+3
0.001
10
0.01
Load Current IOUT1(A)
Output Voltage vs. Load Current
10
Output Voltage vs. Load Current
1.87
VIN = 12V
FREQ = Open
1.02
1.01
1.00
0.99
0.98
PFM
PAF
PWM
0.97
0.96
0.01
0.1
Load Current IOUT1 (A)
January 31, 2014, MB39A214A-DS405-00007-2v1-E
1
VIN = 12V
FREQ = Open
1.85
Output Voltage VOUT2 (V)
1.03
Output Voltage VOUT1 (V)
1
1.89
1.04
CONFIDENTIAL
0.1
Load Current IOUT2 (A)
1.05
0.95
0.001
10
Load Current IOUT2 (A)
*: EN2 Standby mode
0.001
1
10
1.84
1.82
1.80
1.78
1.76
PFM
1.75
PAF
1.73
PWM
1.71
0.001
0.01
0.1
1
10
Load Current IOUT2 (A)
43
D a t a S h e e t
Output Ripple Waveform
Automatic PFM/PWM selection mode
Automatic PFM/PWM selection mode with PAF function
PWM-fixed mode
44
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
Switching Waveform
Load Sudden Change Waveform
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
45
D a t a S h e e t
Startup, Shutdown and Protection Function Operation Waveform
VIN = 12V
IOUT1=7A(0.14Ω)
IOUT2=7A(0.26Ω)
MODE=GND
FREQ=Open
VIN = 12V
IOUT1=7A(0.14Ω)
IOUT2=7A(0.26Ω)
MODE=GND
FREQ=Open
Output Over Current Waveform
Normal operation
46
CONFIDENTIAL
Over
current
protection
Under voltage protection
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings.
If the IC is used over the maximum ratings, the LSI may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside
of these conditions can have an adverse effect on the reliability of the LSI.
2. Use the device within the recommended operating conditions.
The recommended values guarantee the normal LSI operation under the recommended operating conditions.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions
and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance.
4. Take appropriate measures against static electricity.
 Containers for semiconductor materials should have anti-static protection or be made of conductive
material.
 After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
 Work platforms, tools, and instruments should be properly grounded.
 Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground.
5. Do not apply negative voltages.
The use of negative voltages below ─0.3 V may make the parasitic transistor activated to the LSI, and can
cause malfunctions.
January 31, 2014, MB39A214A-DS405-00007-2v1-E
CONFIDENTIAL
47
D a t a S h e e t
 ORDERING INFORMATION
Part number
Package
MB39A214APFT
24-pin plastic TSSOP
(FPT-24P-M09)
Remarks
 EV BOARD ORDERING INFORMATION
EV board number
EV board version No.
Remarks
MB39A214A-EVB-01
MB39A214A-EVB-01 Rev. 1.0
TSSOP-24
48
CONFIDENTIAL
MB39A214A-DS405-00007-2v1-E, January 31, 2014
D a t a S h e e t
 RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of Spansion with “E1” are compliant with RoHS Directive, and has observed the standard
of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated
diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is RoHS compliant.
 MARKING FORMAT (Lead Free version)
39A214A
XXXX
E1 XXX
INDEX
Lead-free version
January 31, 2014, MB39A214A-DS405-00007-2v1-E
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 LABELING SAMPLE (Lead free version)
Lead-free mark
JEITA logo
JEDEC logo
The part number of a lead-free product has
the trailing characters "E1".
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"ASSEMBLED IN CHINA" is printed on the label
of a product assembled in China.
MB39A214A-DS405-00007-2v1-E, January 31, 2014
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 MB39A214APFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY
LEVEL
[Spansion Recommended Mounting Conditions]
Item
Condition
Mounting Method
IR (infrared reflow), warm air reflow
Mounting times
2 times
Storage period
Storage conditions
Before opening
Please use it within two years after
manufacture.
From opening to the 2nd reflow
Less than 8 days
When the storage period after
opening was exceeded
Please process within 8 days
after baking (125°C ±3°C, 24H+ 2H/─0H) .
Baking can be performed up to two times.
5°C to 30°C, 70% RH or less (the lowest possible humidity)
[Mounting Conditions]
(1) IR (infrared reflow)
260°C
245°C
Main heating
170 °C
to
190 °C
(b)
RT
(a)
"M" rank : 250°C Max
(a) Temperature Increase gradient
(b) Preliminary heating
(c) Temperature Increase gradient
(d) Peak temperature
(d') Main Heating
(e) Cooling
(c)
(d)
(e)
(d')
: Average 1°C/s to 4°C /s
: Temperature 170°C to 190°C, 60 s to 180 s
: Average 1°C /s to 4°C /s
: Temperature 250°C Max; 245°C or more, 10 s or less
: Temperature 230°C or more, 40 s or less
or
Temperature 225°C or more, 60 s or less
or
Temperature 220°C or more, 80 s or less
: Natural cooling or forced cooling
Note: Temperature : the top of the package bod
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(2) Manual soldering (partial heating method)
Item
Condition
Before opening
Within two years after manufacture
Between opening and mounting
Within two years after manufacture
(No need to control moisture during the storage
period because of the partial heating method.)
Storage period
Storage conditions
5°C to 30°C, 70% RH or less (the lowest possible humidity)
Mounting conditions
Temperature at the tip of a soldering iron: 400°C Max
Time: Five seconds or below per pin*
*: Make sure that the tip of a soldering iron does not come in contact with the package body.
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 PACKAGE DIMENSIONS
24-pin plastic TSSOP
Lead pitch
0.50 mm
Package width ×
package length
4.40 mm × 6.50 mm
Lead shape
Gullwing
Sealing method
Pl asti c mol d
Mounting height
1.20 mm MAX
Weight
0.08 g
(FPT-24P-M09)
24-pin plastic TSSOP
(FPT-24P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
# 6.50± 0.10 (.256±. 004)
24
0.145± 0.045
(.0057±. 0018)
13
BTM E-MARK
# 4.40± 0.10 6.40± 0.20
(.173±. 004)(.252±. 008)
INDEX
Details of "A" part
+0.10
1.10 –0.15
+.004
.043 –.006
1
12
0.50(.020)
+0.07
0.20 –0.02
+.003
.008 –.001
(Mounting height)
"A"
0.13(.005) M
0~8°
0.60± 0.15
(.024±. 006)
0.10± 0.05
(Stand off)
(.004±. 002)
0.10(.004)
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F24032S-c-2-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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 MAJOR CHANGES
Page
Revision 1.0
Revision 2.0
19
24
Section
 FUNCTION
(9) Under Voltage Protection (UVP)
 EXAMPLE APPLICATION CIRCUIT
 PART LIST
25, 26
 REFERENCE DATA
43 ~ 46
Revision 2.1
-
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Change Results
Initial release
Corrected the timing chart as follows.
Less than 15 μs → Less than 150 μs
Revised the figure.
 Revised the symbol Q1, Q3, R1-1, R3-1 and R4 to R6.
 Added the symbol C14, C15, R23 and R24.
 Revised the company name.
Revised the figure.
Company name and layout design change
MB39A214A-DS405-00007-2v1-E, January 31, 2014
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 CONTENTS
page
 DESCRIPTION ··································································································· 1
 FEATURES ······································································································· 1
 APPLICATIONS ································································································· 1
 PIN ASSIGNMENT ····························································································· 2
 PIN DESCRIPTIONS ··························································································· 3
 BLOCK DIAGRAM ····························································································· 4
 ABSOLUTE MAXIMUM RATINGS ········································································· 5
 RECOMMENDED OPERATING CONDITIONS ·························································· 6
 ELECTRICAL CHARACTERISTICS ········································································ 7
 TYPICAL CHARACTERISTICS············································································· 10
 FUNCTION ······································································································ 13
 I/O PIN EQUIVALENT CIRCUIT DIAGRAM ···························································· 22
 EXAMPLE APPLICATION CIRCUIT ······································································ 24
 PART LIST ······································································································· 25
 APPLICATION NOTE ························································································· 27
 REFERENCE DATA ··························································································· 43
 USAGE PRECAUTION ······················································································· 47
 ORDERING INFORMATION ················································································ 48
 EV BOARD ORDERING INFORMATION ································································ 48
 RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION ··························· 49
 MARKING FORMAT (Lead Free version)·································································· 49
 LABELING SAMPLE (Lead free version) ·································································· 50
 MB39A214APFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL ·· 51
 PACKAGE DIMENSIONS ···················································································· 53
 MAJOR CHANGES IN THIS EDITION ···································································· 54
 CONTENTS······································································································ 55
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit®
EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the
United States and other countries. Other names used are for informational purposes only and may be trademarks of their
respective owners.
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