VBUS054B-HSF Datasheet

VBUS054B-HSF
www.vishay.com
Vishay Semiconductors
4-Line BUS-Port ESD-Protection
FEATURES
• Ultra compact LLP75-6L package
6
5
4
• Low package height < 0.6 mm
• 4-line USB ESD-protection
• Low leakage current
20397
1
2
• Low load capacitance CD = 0.8 pF
3
20453
• ESD-protection acc. IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
1
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu)
(no Sn)
MARKING (example only)
XX
YY
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912




21001
Dot = pin 1 marking
XX = date code
YY = type code (see table below)
ORDERING INFORMATION
DEVICE NAME
ORDERING CODE
TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL)
MINIMUM ORDER QUANTITY
VBUS054B-HSF
VBUS054B-HSF-GS08
3000
15 000
PACKAGE DATA
DEVICE NAME
PACKAGE
NAME
TYPE
CODE
WEIGHT
MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VBUS054B-HSF
LLP75-6L
U3
4.2 mg
UL 94 V-0
MSL level 1
(according J-STD-020)
260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Peak pulse current
Peak pulse power
ESD immunity
Operating temperature
Storage temperature
Rev. 1.7, 15-Jul-15
TEST CONDITIONS
SYMBOL
VALUE
UNIT
Pin 1, 3, 4 or 6 to pin 2
acc. IEC 61000-4-5; tP = 8/20 μs; single shot
IPPM
3
A
Pin 5 to pin 2
acc. IEC 61000-4-5; tP = 8/20 μs; single shot
IPPM
10
A
Pin 1, 3, 4 or 6 to pin 2
acc. IEC 61000-4-5; tP = 8/20 μs; single shot
PPP
45
W
Pin 5 to pin 2
acc. IEC 61000-4-5; tP = 8/20 μs; single shot
PPP
200
W
Contact discharge acc. IEC61000-4-2; 10 pulses
VESD
± 15
kV
Air discharge acc. IEC61000-4-2; 10 pulses
VESD
± 15
kV
TJ
-40 to +125
°C
TSTG
-55 to +150
°C
Junction temperature
Document Number: 81624
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
www.vishay.com
Vishay Semiconductors
ELECTRICAL CHARACTERISTICS VBUS054B-HSF
PARAMETER
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Number of line which can be protected
Nchannel
-
-
4
lines
Reverse stand-off voltage
at IR = 0.1 μA,
pin 1, 3, 4 or 6 to pin 2
VRWM
-
-
5
V
Reverse current
at VIN = VRWM = 5 V,
pin 1, 3, 4 or 6 to pin 2
IR
-
< 0.01
0.1
μA
at IR = 1 mA,
pin 5 to pin 2
VBR
6.3
7.1
8
V
at IR = 1 mA,
pin 1, 3, 4 or 6 to pin 2
VBR
6.9
7.9
8.7
V
Reverse clamping voltage
at IPP = 3 A; pin 1, 3, 4 or 6 to pin 2;
acc. IEC 61000-4-5
VC
-
-
15
V
Forward clamping voltage
at IF = 3 A; pin 2 to pin 1, 3, 4 or 6;
acc. IEC 61000-4-5
VF
-
-
5
V
Pin 1, 3, 4 or 6 to pin 2
VIN (at pin 1, 3, 4 or 6) = 0 V and
VBUS (at pin 5) = 5 V; f = 1 MHz
CD
-
0.8
1
pF
Pin 1, 3, 4 or 6 to pin 2
VIN (at pin 1, 3, 4 or 6) = 2.5 V and
VBUS (at pin 5) = 5 V; f = 1 MHz
CD
-
0.5
0.8
pF
Line symmetry
Difference of the line capacitances
dCD
-
-
0.05
pF
Supply line capacitance
Pin 5 to pin 2; at VR = 0; f = 1 MHz
CZD
-
110
-
pF
Protection paths
Reverse breakdown voltage
Capacitance
Note
• Ratings at 25 °C, ambient temperature unless otherwise specified
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
120 %
Rise time = 0.7 ns to 1 ns
8 µs to 100 %
100 %
80 %
80 %
60 %
60 %
IPPM
Discharge Current IESD
100 %
53 %
40 %
27 %
20 %
20 %
0%
-10 0 10 20 30 40 50 60 70 80 90 100
Time (ns)
20557
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Rev. 1.7, 15-Jul-15
20 µs to 50 %
40 %
0%
0
20548
10
20
30
40
Time (µs)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Document Number: 81624
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
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Vishay Semiconductors
20
1.0
15
0.8
Pin 1, 3, 4 or 6 to Pin 2
0.7
10
VC (V)
Pin 1, 3, 4 or 6 to Pin 2
0.6
C IN (pF)
Measured acc. IEC 61000-4-5
(8/20 µs - wave form)
f = 1 MHz; V BUS (at Pin 5) = 5 V
0.9
0.5
Pin 5 to Pin 2
5
0.4
VC
Pin 2 to Pin 5
0
0.3
0.2
-5
Pin 2 to Pin 1, 3, 4 or 6
0.1
- 10
0.0
0
1
2
3
20549
4
5
0
6
V IN (V)
Fig. 3 - Typical Input Capacitance CIN at Pin 1, 3, 4, or 6 vs.
Input Voltage VIN
2
3
4
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
120
100
Pin 2 to Pin 5
100
VC-ESD (V)
10
I F (mA)
1
IPP (A)
20552
1
Pin 2 to Pin 1, 3, 4 or 6
0.1
acc. IEC 61000-4-2
+ 8 kV
contact discharge
80
60
Pin 1, 3, 4, 6 to Pin 2
40
20
0.01
0.001
0.5
0
0.6
0.7
20550
0.8
0.9
1
1.1
- 20
- 10 0
1.2
20553
VF (V)
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
20
Pin 1, 3, 4 or 6 to Pin 2
8
0
VC-ESD (V)
5
4
- 40
- 60
- 80
3
- 100
2
- 120
1
- 140
0
0.01
20551
0.1
1
10
100
1000 10000
I R (µA)
Fig. 5 - Typical Reverse Voltage VR vs.
Reverse Current IR
Rev. 1.7, 15-Jul-15
Pin 1, 3, 4 or 6 to Pin 2
- 20
Pin 5 to Pin 2
6
VR (V)
t (ns)
Fig. 7 - Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
9
7
10 20 30 40 50 60 70 80 90
- 160
- 10 0
20554
acc. IEC 61000-4-2
- 8 kV
contact discharge
10 20 30 40 50 60 70 80 90
t (ns)
Fig. 8 - Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Document Number: 81624
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
www.vishay.com
Vishay Semiconductors
140
200
150
100
VC-ESD (V)
100
VC-ESD (V)
acc. IEC 61000-4-2
contact discharge
120
Pin 1, 3, 4 or 6 to Pin 2
50
acc. IEC 61000-4-2
contact discharge VC-ESD
0
- 50
Pin 5 to Pin 2
80
60
40
20
VC-ESD
0
- 100
- 20
- 150
- 40
- 200
Pin 2 to Pin 5
- 60
Pin 2 to Pin 1, 3, 4 or 6
- 80
- 250
0
5
20555
10
15
0
20
VESD (kV)
20556
Fig. 9 - Typical Peak Clamping Voltage at ESD
Contact Discharge (acc. IEC 61000-4-2)
5
10
15
20
VESD (kV)
Fig. 10 - Typical Peak Clamping Voltage at ESD
Contact Discharge (acc. IEC 61000-4-2)
APPLICATION NOTE
With the VBUS054B-HSF a double, high speed USB-port or up to 4 other high speed signal or data lines can be protected
against transient voltage signals. Negative transients will be clamped close below the ground level while positive transients will
be clamped close above the 5 V working range. An avalanche diode clamps the supply line (VBUS at pin 5) to ground (pin 2). The
high speed data lines, D1+, D2+, D1- and D2-, are connected to pin 1, 3, 4 and 6. As long as the signal voltage on the data lines
is between the ground- and the VBUS-level, the low capacitance PN-diodes offer a very high isolation to VBUS, ground and to
the other data lines. But as soon as any transient signal exceeds this working range, one of the PN-diodes starts working in the
forward mode and clamps the transient to ground or to the avalanche breakthrough voltage level of the Z-diode between pin 5
and pin 2.
t
w VBUS
i D1+
n D1U
S
B
P
o D2+
r D2t G
ND
6
5
4
1
2
3
R
E
C
E
I
V
E
R
IC
20399
Rev. 1.7, 15-Jul-15
Document Number: 81624
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
www.vishay.com
Vishay Semiconductors
BACKGROUND KNOWLEDGE:
A Zener- or avalanche diode is an ideal device for “cutting” or “clamping” voltage spikes or voltage transients down to low and
uncritical voltage values. The breakthrough voltage can easily be adjusted by the chip-technology to any desired value within a
wide range. Up to about 6 V the “zener-effect” (tunnel-effect) is responsible for the breakthrough characteristic. Above 6 V the
so-called “avalanche-effect” is responsible. This is a more abrupt breakthrough phenomenon. Because of the typical “Z-shape”
of the current-voltage-curve of such diodes, these diodes are generally called “Z-diode” (= zener or avalanche diodes). An
equally important parameter for a protection diode is the ESD- and surge-power that allows the diode to short current in the
pulse to ground without being destroyed.
This requirement can be adjusted by the size of the silicon chip (crystal). The bigger the active area the higher the current that
the diode can short to ground.
But the active area is also responsible for the diode capacitance - the bigger the area the higher the capacitance.
The dilemma is that a lot of applications require an effective protection against more then 8 kV ESD while the capacitance must
be lower then 5 pF! This is well out of the normal range of a Z-diode. However, a protection diode with a low capacitance
PN-diode (switching diode or junction diode) in series with a Z-diode, can fulfil both requirements simultaneously: low
capacitance AND high ESD- and/or surge immunity become possible!
A small signal (Vpp < 100 mV) just sees the low capacitance of the PN-diode, while the big capacitance of the Z-diode in series
remains “invisible”.
CD = 0.4 pF
D
CTOT
ZD
CZD = 110 pF
20400



Such a constellation with a Z-diode and a small PN-diode
(with low capacitance) in series (anti-serial) is a real
unidirectional protection device. The clamping current can
only flow in one direction (forward) in the PN-diode. The
reverse path is blocked.
I/O
D
ZD
Gnd
20401



Another PN-diode "opens" the back path so that the
protection device becomes bidirectional! Because the
clamping voltage levels in forward and reverse directions
are different, such a protection device has a Bidirectional
and Asymmetrical clamping behaviour (BiAs) just like a
single Z-diode.
I/O
D1
ZD
Gnd
D2
20404







Rev. 1.7, 15-Jul-15
Document Number: 81624
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
www.vishay.com

One mode of use is,…
in the very first moment before any pulses have arrived, all
three diodes are completely discharged (so the diode
capacitances are empty of charge) the first signal pulse with
an amplitude > 0.5 V will drive the upper PN-diode (D1) in a
forward direction and “sees” the empty capacitance of the
Z-diode (ZD).
Depending on the duration of this pulse and the pause to the
next one the Z-diodes capacitance can be charged up so
that the next pulse “sees” a lower capacitance. After some
pulses the big Z-diode could be completely charged up so
that the following pulses just see the small capacitance of
both PN-diodes.
For some application this can work perfectly.....


For others applications the capacitance must be the same
all the time from the first till the last pulse.

For these applications the appropriate mode of use is to
connect the Z-diode to the supply voltage.
In this mode the Z-diode is charged up immediately by the
supply voltage and both PN-diodes are always used in
reverse. This keeps their capacitance at a minimum.
Rev. 1.7, 15-Jul-15
Vishay Semiconductors


D1
ZD
I/O
D2
Gnd
20405
VBUS
D1
ZD
I/O
D2
Gnd
20406
Document Number: 81624
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
www.vishay.com
Vishay Semiconductors
0.45 (0.018)
0.55 (0.022)
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
1 (0.039)
0.2 (0.008)
0.3 (0.012)
Heat sink
0.95 (0.037)
1.05 (0.041)
PACKAGE DIMENSIONS in millimeters (inches): LLP75-6L
0.5 (0.020)
0.6 (0.024)
0.54 (0.021)
0.60 (0.023)
0.05 (0.002)
0 (0.000)
0.15 (0.006)
0.25 (0.010)
1.65 (0.065)
1.55 (0.061)
1.55 (0.061)
1.65 (0.065)
Pin 1 marking
Foot print recommendation:
0.5 (0.020)
0.5 (0.020)
0.3 (0.012)
0.3 (0.012)
Document no.:S8-V-3906.02-010 (4)
Created - Date: 04. MAY 2005
Rev. 4 - Date: 21. March 2006
0.15 (0.006)
1 (0.039)
0.5 (0.020)
1 (0.039)
0.25 (0.010)
0.15 (0.006)
Solder resist mask
Solder pad
0.5 (0.020)
20454
Rev. 1.7, 15-Jul-15
Document Number: 81624
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS054B-HSF
www.vishay.com
Vishay Semiconductors
LLP75-6x
S9
F5
Pad layout - view from top / seen at bottom side
S8-V-3906.02-004 (4)
10.01.2005
Rev. 1.7, 15-Jul-15
Pin 1 - location
Document Number: 81624
8
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000