Application Note SmartRectifier™ Control IC Design Notes 01_00 | Aug 26, 2015 | PDF | 717 kb

IR 11 61 µ S mart Re cti f ier ™ C ontr ol I C D esi g n
N otes
Authors:
Helen Ding
Peter Green
Application Note
About this document
Scope and purpose
The purpose of this document is to provide a comprehensive functional description and guide to using the
IR1161 single channel synchronous rectification control IC in the output of a switch mode power supply
(SMPS). The scope applies to all technical aspects that should be considered in the design process, including
calculation of external component values, MOSFET selection, PCB layout optimization as well as additional
circuitry that may be added if needed in certain cases.
Intended audience
Power supply design engineers, applications engineers, students.
Table of Contents
1
Introduction and Device Overview ................................................................................................. 3
2
SmartRectifier™ Concept ............................................................................................................... 4
3
3.1
3.2
3.3
3.4
Design and selection of passive components ................................................................................ 7
IR1161 VCC supply and current consumption .................................................................................... 7
Gate resistor and IC power loss calculation ....................................................................................... 9
MOT resistor calculation ................................................................................................................... 10
Thermal Verification .......................................................................................................................... 11
4
4.1
4.2
4.3
SR MOSFET Power Loss Calculation and Device Selection ........................................................... 12
Body diode conduction loss at turn-on ............................................................................................ 13
Channel conduction loss:.................................................................................................................. 14
Body diode conduction loss at turn-off ............................................................................................ 15
5
5.1
5.2
Other Application Information ..................................................................................................... 18
Driving a Logic Level MOSFET .......................................................................................................... 18
VD filter and delay ............................................................................................................................. 19
6
PCB Layout Guidelines and Examples .......................................................................................... 22
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IR1161 µSmartRectifier™ Control IC Design Notes
Introduction and Device Overview
7
Appendix ...................................................................................................................................... 24
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
Introduction and Device Overview
1
Introduction and Device Overview
The IR1161 smart secondary side controller drives an N-Channel power MOSFET used as a synchronous
rectifier in isolated Flyback converters operating in discontinuous (DCM) or quasi resonant (QR) mode, also
known as critical (CrCM) conduction, transition or boundary-mode. A pair of IR1161s and MOSFETs may be
also be used as a dual synchronous rectifier in resonant half-bridge converters.
The IR1161 precisely controls switching on and off of the synchronous MOSFET thereby bypassing its body
diode during the secondary conduction phase and emulating the rectifying action of a diode rectifier while
eliminating the majority of conduction losses. The MOSFET drain to source voltage is sensed at millivolt
levels to determine the polarity of the drain current switching the gate on and off gate in close proximity to
the zero current transition. The high voltage input structure allows the IR1161 to withstand up to 200 V from
direct connection to the drain.
Internal blanking, reverse current protection circuit and double-pulse suppression provide safe and reliable
operation. The IR1161 based smart synchronous rectifier (SR) offers significant efficiency improvement in
DCM Flyback converters over the full load range so that replacing a Schottky diode output rectifier with the
IR1161 and a correctly selected high performance MOSFET provides significantly lower power dissipation.
PCB space savings due to the IR1161’s small SOT23-5 package are further aided by reduced MOSFET heat
dissipation.
The IR1161 is able to operate from a wide VCC supply voltage ranging from 4.75 V to 20 V making it possible to
supply it from the output in a 5V system and eliminating the need for an auxiliary winding. A logic level
MOSFET is required for low output voltage applications.
A built-in arming and triggering mechanism is included to allow correct switching on and off of the SR
MOSFET under all system conditions, making it superior to a basic self-driven SR scheme or earlier
generations of SR controller.
IR1161 is available in a 5-pin SOT-23 package. The pin out is shown below:
Figure 1
IR1161 pin assignment
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IR1161 µSmartRectifier™ Control IC Design Notes
SmartRectifier™ Concept
2
SmartRectifier™ Concept
The SmartRectifier™ control technique is based on sensing the voltage across the MOSFET drain to source
and comparing it with two internal negative thresholds determine the correct points of gate turn on and off.
The first negative threshold VTH2 detects current through the body diode determining when to turn on. A
second negative threshold VTH1, which is in the range of milli-Volts, determines the level at which the gate is
turned off.
VGATE
VTH2
Figure 2
VTH1
VTH3
VDS
IR1161 SmartRectifier™ control IC voltage sensing thresholds
The secondary side of a Flyback converter is shown in Figure 3 with the IR1161 driving the SR MOSFET
connected at the low-side return. The operating waveforms of the IR1161 in this application are shown in
Figure 4.
Rcc
LOAD
Primary
Controller
4
VD
GATE
5
IR1161
Rg
3
MOT
2
GND
Cdc
1
VCC
Figure 3
Flyback converter with synchronous output rectification
T1 is the conduction phase of the primary switch during which energy is being stored in the Flyback
transformer. The T2 phase begins when the primary switch is turned off and the energy stored in the
magnetic field starts to be delivered to load through the output rectifier circuit. At this point the conduction
phase of the SR MOSFET is initiated and current starts flowing through the body diode, generating a
negative VDS voltage. The body diode has a much higher voltage drop than the turn-on threshold VTH2 causing
the IR1161 to drive the gate of the SR MOSFET on to bypass it.
When the MOSFET is turned on the instantaneous sensed voltage reduces to RDSon  I D . This voltage level
being much lower than body diode forward voltage drop is sensitive to parasitic ringing generated by the
transformer leakage inductance and MOSFET output capacitance. To avoid mis-triggering and resulting
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
SmartRectifier™ Concept
premature gate turn-off, a blanking period (MOT) is used that disables VTH1 triggering for a minimum period
of time set by an external resistor.
VTH3
ISEC
VDS
T1
T2
time
VTH1
VTH2
TDon
TDoff
Gate Drive
time
Blanking
MOT
Figure 4
Tblank
Secondary synchronous rectification waveforms of DCM/CrCM Flyback
At the end of each switching cycle the secondary current reduces to zero and the VDS voltage crosses the
turn-off threshold VTH1. The IR1161 then turns the gate off and current will again start flowing through the
body diode causing the VDS voltage to make a sharp negative transition. Depending on the amount of
residual current, VDS may once again exceed the turn on threshold VTH2. For this reason re-triggering is
disabled after the gate drive has been switched off until the controller has re-armed.
The re-arming sequence requires VDS to cross the VTH3 threshold and remain above it for a period denoted as
tBRST. If this does not occur, the gate drive will remain low for a period of tBLANK, after which time re-arming will
occur automatically.
To achieve high system efficiency and low standby loss at the same time, the IR1161 incorporates a
programmable minimum on time. This feature offers flexibility in various applications at different switching
frequencies. The MOT function determines the shut-down point at light load. During normal operation, the
designer sets the minimum on time to be shorter than the secondary conduction period. At progressively
lighter loads, the conduction period reduces until it eventually becomes shorter than the MOT. If the IR1161
detects no voltage drop signifying no SR drain current the MOT protection function causes the gate drive to
remain off for the next cycle. MOT protection operates whether or not the SR gate drive is active or whether
conduction is through the body diode. In this way the IR1161 does not drive the gate at light loads and
therefore consumes minimal power improving system efficiency.
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IR1161 µSmartRectifier™ Control IC Design Notes
SmartRectifier™ Concept
VTH3
ISEC
VDS
time
VTH1
VTH2
Gate Drive
time
MOT
Current not detected
MOT
Figure 5
time
MOT protection as load decreases
VTH3
ISEC
VDS
time
VTH1
VTH2
Gate Drive
time
MOT
MOT
Figure 6
Current not detected
Current detected
time
Gate drive resuming as load increases
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IR1161 µSmartRectifier™ Control IC Design Notes
Design and selection of passive components
3
Design and selection of passive components
3.1
IR1161 VCC supply and current consumption
The IR1161 may be biased from the output voltage if VOUT falls within the range of 4.75 V to 20 V. A small RC
filter is recommended between VOUT and VCC for noise filtering. A decoupling capacitor of at least 1 uF is
necessary to prevent noise from interfering with the correct operation of the IR1161. Although the IR1161
accepts up to 20 V supply voltage, it is suggested in higher output voltage systems to limit the supply voltage
to 12 V ~ 15 V where a standard SR MOSFET is used. This reduces gate drive switching losses since the gate
drive output is not internally clamped. The following simple voltage level shift circuit supplies Vcc from VOUT.
VCC is determined by VOUT minus the value of VZ + VBE with typically 0.5 V drop on R1. On startup as VOUT rises it
must exceed VZ + VBE + 0.5 + VCC_ON before the IR1161 gate drive is enabled. This prevents possible shoot
through from occurring due to the gate potentially being switched on due to ringing oscillations during start
up.
VOUT
R1
VZ QVCC
RVCC
IR1161
SOT-23 5 Pin
RB
VCC
GATE
GND
SR
MOSFET
VD
MOT
CVCC
RMOT
Figure 7
Simple VCC level shift supply circuit
VOUT
R1
QVCC
VZ RVCC
IR1161
SOT-23 5 Pin
R2
VCC
GATE
GND
MOT
VD
CVCC
R3
EN
SR
MOSFET
QEN
RMOT
Figure 8
VCC level shift supply circuit with external logic level enable
The IR1161 can be disabled and placed in low power standby by removing Vcc as shown above in figure 8.
The circuit above combines VIN to VCC voltage step down with an enable function from the logic level EN
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IR1161 µSmartRectifier™ Control IC Design Notes
Design and selection of passive components
input. Power dissipation for 25 V input and 12 V VCC is ~70 mW, mainly in the zener diode during operation
and zero during shutdown. This is based on a typical ICC of 5 mA as quoted in the datasheet.
In some applications, it is preferred to place the synchronous rectifier circuit at the high-side to obtain a
better grounding connection. In this case an auxiliary winding must be available on the Flyback transformer
to provide a floating bias supply VCC to the IR1161. One implementation is shown below:
VCC
MOT
2
3
5
IR1161
GND
1
4
GATE
VD
LOAD
Primary
Controller
Figure 9
High-side connection with auxiliary winding to bias the IR1161
To calculate IR1161 current consumption the gate charge of the SR MOSFET needs to be determined. The
secondary current initially flows through the body diode resulting in a low source to drain voltage drop,
therefore turn on will occur in ZVS mode. This applies in DCM or QR/CrCM mode. In zero-voltage switching
operation the MOSFET behaves like a constant capacitance load (Csync) connected to the IC gate drive
output.
The following diagram shows how the normal gate characteristics (Magenta) change when the switch is
turned on at zero voltage (Blue). The gate plateau is effectively eliminated:
VGS(V)
In this region, VDS=0V. The total
equivalent gate capacitance is the
same as in ZVS mode as shown
below:
D
Total Gate charge in ZVS mode
Total Gate charge in normal mode
10
VGS
Cgd
8
}
6
VM
4
Gate equivalent
capacitance at
VDS=0V
G
Cgs
2
S
QGS
QG(nC)
QGD
QG
Figure 10
MOSFET gate equivalent capacitance in ZVS mode
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IR1161 µSmartRectifier™ Control IC Design Notes
Design and selection of passive components
C sync 
(Qg  Qgd  Qgs)
Vgs  Vm
VGS is the gate voltage where QG, QGD and QGS are tested. In most datasheets it is specified as 10 V. Vm is the
Miller plateau voltage. If two or more MOSFETs are connected in parallel, the above capacitance is
multiplied by the number of devices.
The IC operating current can be calculated from the following equation:
I CC  I QCC  f SW CsyncVcc  110 9 f SW
where, IQCC is the IR1161 quiescent current in active mode, fsw is the converter switching frequency. The
second term is entirely due to the synchronous MOSFET gate drive while the third term accounts for the
current consumption in the IC internal control circuitry during normal operation (the factor 110 9
accounts for the frequency dependent current requirements for the internal logic).
3.2
Gate resistor and IC power loss calculation
Since IR1161 based synchronous rectification turns the SR MOSFET on and off at VDS levels close to zero, the
gate resistor does not have an impact on the transitions and can be designed in order for the gate loop to be
optimized. Oscillations should be minimized as much as possible in regular operations, therefore assuming
the total gate trace loop inductance (LG) is known, (a first order estimation can be 1 nH/mm of physical trace
length), the minimum recommended gate resistor value is:
Rg loop  2
Lg
Ciss
where, Ciss is the switch input capacitance (from MOSFET datasheet). It is evident how a correctly optimized
layout can dramatically reduce this requirement.
Rg,loop is the total resistance in the gate charge loop:
Rgloop  Rdown  RgFET  Rg
Rdown is the internal pull down resistance of the IR1161 gate driver; Rg_FET is the internal gate resistance of the
SR MOSFET and Rg is the external gate resistor.
Rearranging the equation gives:
Rg  Rg ,loop  RgFET  Rdown
The following figure shows how increasing the gate resistor reduces oscillation when loop inductance is
large due to long traces and/or MOSFET leads. The gate waveform with a 1 Ω external resistor is shown in
dark green and the waveform with a 5 Ω resistor is shown in yellow. It can be seen that the 5 Ω resistor has
faster overall rise time due to less oscillation.
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IR1161 µSmartRectifier™ Control IC Design Notes
Design and selection of passive components
Figure 11
Gate turn-on waveform with 1 Ω and 5 Ω resistor
The energy dissipated by the gate resistor is exactly equal to the energy stored in the capacitor. The IR1161
internal gate driver resistance is in series with the external gate resistor so the power dissipation is
proportionally shared.
The total power dissipated by the driver and the total gate resistance is given by:
Pdr  Csync  Vcc  f sw,max
2
The driver buffer and the gate resistance will linearly share this power dissipation as described in the
following relationship:

 Pdr
Rg  RgFET
Rg  RgFET

PRg ext  

R R
 2

R
R

R

R
g
gFET
Source
g
gFET
Sink


Solving this equation with respect to Rg,ext (which includes the external gate resistor Rg and the MOSFET
internal gate resistance Rg,FET), it is possible to determine the percentage of the total driving power
dissipated into the gate resistor as a function of its value. Pull up ( rup ) and pull down ( rdown ) resistances are
defined in the IR1161 datasheet. For the above calculations:
RSink  2rdown and RSource  2 rup
are used in order to allow for temperature shift and process variation.
The power loss in IR1161 now can be calculated as:
PIC  Vcc  Icc  PRg ext
It is clear that reducing supply voltage VCCor increasing external gate resistor value could effectively reduce
SR controller IC power dissipation.
3.3
MOT resistor calculation
The MOT is linear in relation to the resistor value RMOT, therefore the following formula can be used to
determine the required value:
RMOT  51010 t MOT
The value of RMOT should not be lower than the minimum recommended on the datasheet.
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IR1161 µSmartRectifier™ Control IC Design Notes
Design and selection of passive components
3.4
Thermal Verification
Thermal verification is based on calculated power dissipation in the IR1161. SOT23-5L is a small package
and the thermal performance strongly depends on PCB layout. For the SOT23-5L package in free air, the
thermal resistance between junction and ambient can be as high as 427°C/W. It will drop to 212°C/W when
the IC is soldered on 14 mm by 11.5 mm two-layer PCB using a standard footprint. Thus sufficient PCB area is
required for IR1161 heat dissipation.
Figure 12
IR1161 TO-220 daughter card layout
Using the junction to ambient thermal resistance, the maximum ambient temperature (where ambient
refers to the environment in which the IC will work, i.e. box, PCB etc.) and the IC maximum power
dissipation, it is possible to calculate the maximum junction temperature of the IR1161 package. The
thermal resistance quoted in the datasheet is based on 11.5 mm x 14 mm 2-layer PCB with standard
SOT23-5L footprint.
TJ max  PICmax RJA  TIC _ amb
If the maximum junction temperature exceeds the system design target it will be necessary to either; reduce
the total power dissipation by reducing VCC voltage or increasing the gate drive resistor Rg, or reduce thermal
resistance by increasing the PCB area or increasing the Copper area of the GND trace.
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IR1161 µSmartRectifier™ Control IC Design Notes
SR MOSFET Power Loss Calculation and Device Selection
4
SR MOSFET Power Loss Calculation and Device Selection
The power loss in the SR MOSFET is the sum of conduction loss, switching loss, and gate driver loss. This
application note focuses on the power loss calculation in a Flyback converter operating in DCM or quasiresonant (QR) also known as critical conduction (CrCM) mode, where the secondary synchronous rectifier is
switched on and off at zero voltage (ZVS condition) resulting in zero switching loss.
Conduction loss can be broken down into channel conduction losses and body diode conduction losses. The
conduction period is illustrated in Figure 15, refers to schematic of Figure 14. Tb1 and Tb2 are the body diode
conduction phase and TC is the channel conduction phase.
Vin
Llkp
Csn1
Llks
n=Np:Ns
Vo
IPRI
Rsn1
Np
Rcc
Ns
Dsn1
ISN1
ISEC
Rsn2
Csn2
LOAD
Coss2
VDP
Q2
Coss1
Rg
Q1
Cpar
4
VD
GATE
5
IR1161
Primary
Controller
VDS
3
2
MOT
GND
Cdc
1
VCC
Figure 13 Typical Flyback converter with parasitic capacitance (Parasitic capacitor Cpar includes
transformer cancellation inter-winding capacitance and snubber capacitance between the Drain of Q1 and
Ground if included in the circuit)
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IR1161 µSmartRectifier™ Control IC Design Notes
SR MOSFET Power Loss Calculation and Device Selection
VDP
VIN+nVO
nVO
VIN
Ippk
ISN1
IPRI
T0
T2
T1
Ispk
ISEC
VDS
Is1
Is2
time
VTH2
Gate Drive
time
Tc
Tb1
Tb2
Figure 14
SR MOSFET conduction waveform
4.1
Body diode conduction loss at turn-on
The power loss in the first body diode conduction phase can be calculated by:
1 =
1
∙ ∙ ∙ ∙
2 1   1
Tb1 is approximate the turn-on propagation delay of the IR1161 (TDon in the datasheet). If additional turn-on
delay is applied in circuit or a large gate resistor is used, the additional turn-on delay and gate rising time
should be considered in calculating Tb1.
VF is the body diode forward voltage drop and Is1 is the secondary current value at the time IR1161 gate
turns on.
At the time when the primary switch turns off, the voltage at the primary MOSFET drain increases as shown
by the black trace in Figure 14. From T0 to T1, Coss1 of the primary MOSFET Q1 and the parasitic capacitor Cpar
are charged by the primary peak current Ippk. The secondary parasitic capacitance Coss2 of Q2 and the
snubber capacitor Csn2 are then discharged. Usually the voltage on the snubber capacitor Csn1 is higher than
the transformer reflected voltage nVo, therefore Dsn1 is reverse blocked and Csn1 does not contribute to the
rise time during T0 to T1. At time T1, the primary drain voltage VDP reaches Vin + nVo. Coss2 and Csn2 are
discharged to zero voltage and the body diode of the SR MOSFET Q2 starts conducting current.
From T1 to T2, primary drain voltage is rises to a voltage higher than the voltage on snubber capacitor Csn1,
the primary snubber diode is conducting and Csn1 started to be charged. Transformer leakage inductance
resonates with Csn1, Coss1 and Cpar. The resonant period can be calculated by:
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IR1161 µSmartRectifier™ Control IC Design Notes
SR MOSFET Power Loss Calculation and Device Selection
T _ res1  2   Llkp  Csn1  Coss1  C par 
At T2 the primary drain voltage reaches its peak, which is determined by transformer leakage inductance and
the snubber elements Csn1, Rsn1. The secondary current reaches the ideal peak current ISpk.
Assuming the snubber capacitor Csn1 is being charged when the primary drain voltage reaches Vin + nVo, the
T2-T1 time interval is obtained as follows:
dT  T 2  T1 
T _ res1 1
   Llkp  Coss1  C par  Csn1 
4
2
The first body diode conduction phase of the IR1161 (Tb1) usually falls into the T1~T2 resonant period. Is1
current is obtained by:
 Tb1 2 
]
I S1  I Spk  [1  cos
T
_
res
1


For DCM or QR Flyback, the primary and secondary peak currents are calculated by the following:
I Ppk 
I Spk  n
2  Pin
L p  f SW
Np
2  Pin

L p  f SW
Ns
2  Pin
L p  f SW
Here Lp is the transformer primary magnetizing inductance and Pin is the converter input power. The
transformer primary to secondary turns ratio (Np:Ns) is denoted by n, where Np is the transformer primary
turns and Ns is the transformer secondary turns.
he MOSFET Coss is not a fixed capacitance but is actually VDS dependent exhibiting a non-linear relationship
with the VDS voltage. The charging of Coss is usually simplified with an equivalent capacitance. Most MOSFET
datasheets specify the effective value of Coss at 80% of rated voltage. For the timing calculation, the time
related effective value according to the datasheet should be used. As the actual VDS voltage in a real
application is not usually exactly 80% of VBRDSS, a more accurate calculation of T_res1 should be based on the
time equivalent of Coss at the actual VDS.
Note that the peak current Ispk here refers to secondary peak current in an ideal case (see the dotted red
line in figure 14) and that the actual peak current is higher than Ispk due to resonant action. In the worst case
the actual peak current could be as much as twice Ispk. This depends on the snubber and damping circuit so
the actual secondary peak current will reach somewhere between Ispk and 2 x Ispk.
4.2
Channel conduction loss:
The IR1161 has a very low turn-off threshold Vth1 to achieve nearly zero current turn-off. To simplify the
calculation without introducing significant error it is acceptable to consider the channel to be turned on
during the entire secondary current conduction time:
Pch  Isrms2  RDS (on)
RDS(on) is the MOSFET on state resistance RDS(on), which is normally shown in the datasheet at 25ºC. This would
be approximately 1.5 times higher at Tj=100 ºC, which should be assumed for channel conduction loss
calculations.
Isrms is output RMS current and can be calculated by:
I srms 
Application Note
2  Ioav
3.DSEC
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IR1161 µSmartRectifier™ Control IC Design Notes
SR MOSFET Power Loss Calculation and Device Selection
In this formula, Ioav is the converter output average current and DSEC is the secondary conduction dutycycle, given by:
DSEC 
4.3
2  Ioav
I Ppk  n
Body diode conduction loss at turn-off
Tb2 is the second body diode conduction time. This is included in the channel conduction time in the above
Pch calculation because the Tb2 body diode conduction loss is not negligible in some conditions. For example,
if a through-hole packaged MOSFET with low RDS(on) is used, the turn-off body diode conduction loss should
be taken into account. As illustrated here, the parasitic inductance in series with MOSFET creates a voltage
drop due to changing current (di/dt), which can degrade the accuracy and effectiveness of the voltagesensing control technique of the SR controller. Though the designer should always optimize the PCB layout
to obtain a Kelvin connection to the MOSFET, there are some limitations based on the device package.
Generally through-hole packages like TO-220 and TO-247 have larger stray inductances than surface mount
packages such as QFN, SO-8 and DirectFET. Even a small inductance can cause a voltage drop in the range of
the IC’s threshold levels with the di/dt values present in this application, which could in turn trigger the
IR1161 to turn-off the gate before the drain current drops to Vth1/RDS(on) as in the ideal case.
MOSFET Package Inductance
S
D
Device Current
+
Figure 15
-
+
-
Negative di/dt
MOSFET package inductance
ISEC
Actual gate
turn off point
VDS
Is2
T1
T2
Ideal gate
turn off point
Vth1/RDSon
time
VTH1
Actual VDS shifted up
due to stray inductance
Ideal VDS without
stray inductance
VTH2
Gate Drive
time
Tb2
Figure 16
IR1161 waveform with parasitic inductance
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IR1161 µSmartRectifier™ Control IC Design Notes
SR MOSFET Power Loss Calculation and Device Selection
The offset voltage generated by parasitic/stray inductance can be calculated by the secondary current di/dt
slope and the stray inductance (LSTRAY).
VOFFSET 
di
LSTRAY
dt
The actual gate turn-off current IS2,
IS2 
Vth1  VOFFSET
di
 TDoff 
RDSon
dt
di I Spk  f SW

dt
DSEC
Vth1 is the turn-off threshold of the IR1161. In the above equations the negative sign should not be included.
TDoff is the turn-off propagation delay of the IR1161.
Now the body diode conduction loss in the turn-off phase is calculated:
1
Pbody2   I S 2 VF  Tb 2  f SW
2
I
Tb 2  S 2
di / dt
The total conduction loss:
Pcon  Pbody1  Pch  Pbody2
The plots shown in figure 18 below, illustrate how it is not necessary to use an SR MOSFET with extremely
low RDS(on).
Low RDS(on) only provides benefit when the package inductance of the SR MOSFET is also very low such as
with a directFET or a QFN MOSFET with copper clip. A TO-220 MOSFET could have up to 20 nH package
inductance based on the number and size of internal bonding wires. It is therefore highly recommended to
carefully check the turn-off timing and the body diode conduction loss when a through-hole MOSFET is
being used. The designer could select a device with higher RDS(on) if the body diode loss is taking a significant
percentage in total conduction loss. As previously pointed out, this is due to the SR gate drive switching off
prematurely thereby increasing the second period of conduction through the body diode with the resulting
increased power dissipation.
Figure 17
Total conduction loss in sync rect MOSFET vs. RDS(on)
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IR1161 µSmartRectifier™ Control IC Design Notes
SR MOSFET Power Loss Calculation and Device Selection
The total gate driver loss is discussed in section 3.2. PRgext may be used to calculate the gate drive loss that
dissipated in MOSFET:
PRg FET 
RgFET
Rg
PRg ext
RgFET is the internal gate resistance of the SR MOSFET and Rg is the external gate resistor.
Total power loss in the SR MOSFET is therefore:
PFET  Pcon  PRgFET  Pbody1  Pch  Pbody2  PRgFET
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
Other Application Information
5
Other Application Information
5.1
Driving a Logic Level MOSFET
An external gate drive pull down circuit is recommended when driving a logic level MOSFET.
This is because during power up and power down the drain may be switching while the IR1161 remains in
UVLO.
SR MOSFET drain to gate capacitance causes voltage pulses to appear at the gate that could have sufficient
amplitude to reach the turn on threshold because the IR1161 gate sink capability is limited when VCC < 2V.
The following circuit ensures that the gate voltage remains below 1 V under all conditions:
GATE
VCC
GND
2
MOT
3
Dg
Rg
5
IR1161
CVcc
1
SR MOSFET
VD
4
Qsink
RMOT
Figure 18
Rb
Gate clamping circuit for logic level SR MOSFET
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IR1161 µSmartRectifier™ Control IC Design Notes
Other Application Information
Figure 19
Gate waveform with clamping circuit during startup
The oscilloscope traces above show that the drain voltage is switching due to primary MOSFET switching,
before the IR1161 VCC supply has reached the startup threshold. Under this condition Qsink holds the gate
voltage below 1 V.
5.2
VD filter and delay
In DCM operation the secondary drain voltage rings due to the transformer leakage inductance after all of
the stored energy the Flyback transformer has been delivered to the output. The resonant frequency of
these ringing oscillations depends on the magnitudes of primary inductance (Lp) and parasitic capacitances
(Coss1, Coss2, Csn2, Csn3). The initial amplitude of the secondary ringing is equal to the output voltage Vo plus SR
MOSFET body diode forward voltage drop VF. The ringing will be damped by the resistive elements in the
circuit and does not therefore normally transition below zero volts at each of the valleys. However, in rare
cases large body diode voltage drop and/or slow reverse recovery of the body diode can potentially drive
the VDS ringing negative peak below the turn-on threshold of the IR1161 (Vth2). In this case the IR1161 would
turn on SR MOSFET if it had previously been armed by VDS remaining above VTH3 for longer than tBRST. This
would cause negative shoot though current to flow through the MOSFET from drain to source causing the
output capacitor to be discharged and reducing system efficiency.
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
Other Application Information
Figure 20
DCM false triggering waveform
The negative ringing effect described above does not occur in the majority of practical power supply circuits
since series resistances provide sufficient damping to prevent it. Furthermore low voltage, low RDS(on) SR
MOSFET body diode characteristics should be selected with best possible reverse recovery and lowest
forward voltage.
A series RC snubber is also often connected across the SR MOSFET drain and source, which provides further
damping for such high frequency oscillations.
An RC filter can also be added to the VD pin of the IR1161 as shown below. This filter introduces a small delay
to reduce the amplitude of negative ringing appearing at the drain sensing input. Considering the turn-on
body diode conduction loss, it is not recommended to delay the IR1161 gate turn-on by more than 200 ns. A
small Schottky diode could also be added in parallel with the SR MOSFET.
VCC
GATE
1
3
IR1161
2
GND
5
VD
4
MOT
Figure 21
RC filter to VD pin
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IR1161 µSmartRectifier™ Control IC Design Notes
Other Application Information
Figure 22
VD waveform with 1.5 kΩ VD resistor and IR1161 internal capacitance
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
PCB Layout Guidelines and Examples
6
PCB Layout Guidelines and Examples
IC placement
Due to the nature of SR control based on fast and accurate voltage sensing, it is essential that the circuit
layout be optimized in order to keep the IR1161 as close as possible to the SR MOSFET. As a general
guideline, the physical distance between the two devices should never exceed 10 mm (0.4 inches).
IC decoupling capacitor
The key element to properly decoupling the IC is the physical location of the VCC capacitor and its
connections to the power terminals. In order for this capacitor to provide effective filtering, it must be
located as close as physically possible to the VCC and COM pins and connected through the shortest available
path.
Gate Drive Loop
Minimal gate drive loop will reduce requirements for damping and enhance system robustness. Gate loop
inductance plays a major role in damping requirements. Once layout is finalized, then a “rule of thumb”
estimation consists of measuring the physical loop trace length, assuming each millimeter (1mm = 39.37
mils) to add 1 nH of inductance. Other methods include measurement (low frequency RCL meters or current
slope for a given voltage pulse) or FEM simulations.
Single layer board layout examples are shown in the following figures:
Figure 23
Single layer layout example with QFN MOSFET
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
PCB Layout Guidelines and Examples
Figure 24
Single layer PCB example with TO-220 MOSFET
Application Note
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IR1161 µSmartRectifier™ Control IC Design Notes
Appendix
7
Appendix
Symbols list [1]
VTH1: IR1161 turn-off threshold
VTH2: IR1161 turn-on threshold
VTH3: IR1161 periodic logic (reset) threshold
RDS(on): synchronous rectifier MOSFET channel ON resistance
ID: synchronous rectifier MOSFET drain current
VDS: synchronous rectifier MOSFET drain to source voltage
MOT: IR1161 minimum ON time parameter
tblank: IR1161 turn off blanking time
Cdc: IR1161 decoupling capacitor on Vcc
Rg: SR MOSFET gate drive loop resistance external to IR1161 IC
RCC: supply voltage series resistor value (Vsupply to VCC)
fsw,max: converter maximum operating switching frequency
Qg: SR MOSFET total gate charge
Qgd: SR MOSFET gate to drain (Miller) charge
Qgs: SR MOSFET gate to source charge
IQCC: IR1161 quiescent current
Lg: total gate loop parasitic inductance
Ciss: SR MOSFET input capacitance
Pdr: Total power dissipated by the gate drive function for each SR MOSFET
RSource: gate driver source resistance
RSink: gate driver sink resistance
PRg: Power dissipated in each gate resistor
PIC: IR1161 IC maximum power dissipation
TIC_amb: IC environment temperature (most cases is PCB temperature where IC is soldered)
RΘJA: IR1161 IC junction to ambient thermal resistance
VCC: Supply voltage on IR1161 Vcc pin
ICC: IR1161 IC supply current
TDon: IR1161 turn on propagation delay
Coss: MOSFET output capacitance, time related effective
[1]
IR1161 SmartRectifier™ control IC datasheet, International Rectifier.
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IR1161 µSmartRectifier™ Control IC Design Notes
Appendix
Revision History
Major changes since the last revision
Page or Reference
Description of change
--
First Release
Application Note
25
Revision1.0, 2015-07-23
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