82v842av100.pdf

HT82V842A
10-Bit 20MSPS CCD Analog Signal Processor
Features
· Operating voltage: 2.7V~3.6V
· Independent ADC input conversion clock and data
output clock
· Low power consumption: 70mW (Typ.)
· Independent CDS and PGA gain control
· Power down mode: less than 30mW
- CDS: -1.94/0/6/12dB
- PGA: 0~24dB
· Accepts a direct signal input to ADC or PGA at 1.0
VPP (Typ.)
· Wide gain range: -1.94~36dB
· CCD signal input level: 1.1 VP-P (Max.)
· High speed sample and hold circuit: pulse width 11ns
· 10-bit ADC (up to 20MHz)
(Min.)
- DNL: ±0.6 LSB (Typ.)
· 48-pin LQFP package
· Black level neutralizer, target setting: 16~127LSB
· Built-in serial interface
General Description
The HT82V842A is a CMOS single-chip signal processing device for CCD area sensors. It consists of a clamp
circuit, Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), reference voltage generator,
black level detection circuit, 20MHz 10-bit A/D converter
(ADC), timing generator for internally required pulses,
serial interface for internal function control and PGA
gain control.
Block Diagram
O B P
A D C K
A D C L P /C C D C L P
C S S C K S D A T A
T im in g
G e n e ra to r
B L K
M O N O U T
S e r ia l
R e g is te r
B a n d G a p
C ir c u it
C L P C A P
D C C la m p
C C D C L P
R E F IN
P G A
R o u g h
C D S
P G A
F in e
S /H
C C D IN
C C D
V R P
V C O M
V R N
A D C L P
0 /6 /1 2 /1 8 d B
-1 .9 4 /0 /6 /1 2 d B
0 ~ 6 d B
(0 .0 4 7 d B /S te p )
1 0 - B it
A D C
D O 0 ~ D O 9
A D IN
O B P
V
Rev. 1.00
C o m p a re
D A C
O B C A P
D D
V
B la c k L e v e l
R e g is te r
R E S E T S T B Y S H R
S S
1
S H D
O U T C K
January 2, 2006
HT82V842A
Pin Assignment
D O 0
D O 1
D O 2
D O 3
D O 4
V S S
V D D
D O 5
D O 6
D O 7
D O 8
D O 9
N C
V D D
N C
V R N
V R P
V D D
V D D
V S S
V S S
V C O M
C C D IN
R E F IN
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
2
3 6
O U
R E
V D
V S
S T
C S
S D
S C
3 5
3
3 4
4
3 3
5
H T 8 2 V 8 4 2 A
4 8 L Q F P -A
6
7
8
9
3 2
3 1
3 0
2 9
2 7
1 1
D
B Y
A T A
K
O B P
N C
B L K
A D C L P /C C D C L P
2 8
1 0
S
T C K
S E T
2 6
1 2
2 5
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
S H D
S H R
A D C K
N C
V S S
V D D
N C
N C
M O N O U T
O B C A P
A D IN
C L P C A P
Pin Description
Pin No.
Pin Name
I/O
Description
¾
No connection
2, 6~7, 19, 34, 43 VDD
¾
Positive power supply for analog circuit
4
VRN
O
Negative reference voltage for internal ADC
Connect to VSS via 0.1mF
5
VRP
O
Positive reference voltage for internal ADC
Connect to VSS via 0.1mF
8~9, 20, 33, 42
VSS
¾
Negative power supply for analog circuit
10
VCOM
O
Common reference voltage for internal ADC
11
CCDIN
I
CDS circuit data input
12
REFIN
I
CDS circuit reference input
13
CLPCAP
O
Clamp level output
Connect to VSS via 0.1mF
14
ADIN
I
ADIN signal input
15
OBCAP
O
Black level integration voltage
Connect to VSS via 0.1mF~1mF (by applications)
16
MONOUT
O
Monitor output of CDS or PGA
22
ADCK
I
ADC sampling clock input
23
SHR
I
Reference sampling pulse input
24
SHD
I
Data sampling pulse input
25
ADCLP/CCDCLP
I
Pulse input for ADIN clamp and black calibration control.
Clamp control input.
26
BLK
I
Blanking pulse input
27
NC
¾
28
OBP
I
Black level period pulse input
29
SCK
I
Serial clock input
30
SDATA
I
Serial data input
1, 3, 17~18, 21
Rev. 1.00
NC
No connection
2
January 2, 2006
HT82V842A
Pin No.
Pin Name
I/O
Description
31
CS
I
Serial port chip selection (Active at low)
32
STBY
I
Power down control (Active low)
35
RESET
I
Reset signal (Active low)
36
OUTCK
I
Clock source for ADC output
37~41, 44~48
DO0~DO9
O
Digital output from ADC
Absolute Maximum Ratings
Supply Voltage .........................GND-0.3V to GND+6V
Storage Temperature ...........................-55°C to 150°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-20°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VIH
High Level Input Voltage
3V
¾
0.7VDD
¾
VDD
V
VIL
Low Level Input Voltage
3V
¾
0
¾
0.3VDD
V
IIH
High Level Input Current
3V
VIL=0V
¾
¾
200
mA
IIL
Low Level Input Current
3V
VIH=3.0V
¾
¾
1
mA
IMD
Operation Current at Monitor Disable
3V
fS=20MHz
¾
23
¾
mA
IMA
Supply Current at Monitor Active
3V
fS=20MHz
¾
26
¾
mA
ISS
Power Down Current
3V
¾
¾
10
mA
VCCDIN
3V
CCDIN input,
fIN=1MHz
¾
1.1
¾
VP-P
3V
ADIN input,
fIN=1MHz
¾
1.0
¾
VP-P
Analog Input Range
VADIN
¾
VCLPCAP
Clamp Voltage
3V
¾
1.5
1.7
1.9
V
tBLKCAL
Black Calibration Time
3V
¾
¾
¾
200
Pixel
VBLKCAL
Maximum Calibration Offset Voltage
3V
¾
¾
±200
¾
mV
G (0)
CDS Gain (Set 0 dB)
3V
Absolute gain
-2
-1
0
dB
Relative gain
G (1)
CDS Gain (Set 6.02 dB)
3V
5.52
6.02
6.52
dB
G (2)
CDS Gain (Set 12.04 dB)
3V
11.54
12.04
12.04
dB
G (3)
CDS Gain (Set -1.94 dB)
3V
-2.44
-1.94
-1.44
dB
Gmin
PGA Gain (Minimum Gain)
3V
-1.2
-0.2
0.8
dB
Gmax
PGA Gain (Maximum Gain)
3V
22.906
23.906
24.906
dB
0
0.047
0.094
dB
Absolute gain
Relative gain
Gstep
PGA Gain (Gain Step)
3V
ERPA
Total (CDS+PGA) Gain Monotony
3V
¾
¾
¾
±4
LSB
RES
Resolution
3V
¾
¾
¾
10
Bits
Rev. 1.00
3
January 2, 2006
HT82V842A
Symbol
Test Conditions
Parameter
VDD
Conditions
fS=20MHz
Min.
Typ.
Max.
Unit
¾
±0.6
±1.0
LSB
DNL
Differential Nonlinearity
3V
SN
S/N
3V
¾
¾
58
¾
dB
SND
S/(N+D)
3V
¾
¾
56
¾
dB
VCOM
ADC Common Voltage
3V
¾
1.25
1.4
1.55
V
VRP
VRP Voltage (Positive)
3V
¾
1.55
1.65
1.75
V
VRN
VRN Voltage (Negative)
3V
¾
1.05
1.15
1.25
V
CCAL
¾
127
LSB
3V
¾
16
ADC Output Black Level Calibration Code
1
¾
127
LSB
¾
1
¾
LSB
STCAL
Note:
Calibration Code Resolution
¾
3V
Black calibration period is specified when CCAL is from 16 to 127LSB. Although black level codes of 1 to 15
could be set, tBLKCAL is not guaranteed for these codes.
A.C. Characteristics
Symbol
Parameter
VSS=0V, Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fS
Conversion Frequency
3.0V
¾
0.5
¾
20
MHz
tCYC
Clock Cycle Time
3.0V
¾
50
¾
¾
ns
tR
Clock Rising Time
3.0V
¾
¾
¾
2
ns
tF
Clock Falling Time
3.0V
¾
¾
¾
2
ns
tL
Clock Low Period
3.0V
¾
23
¾
¾
ns
tH
Clock High Period
3.0V
¾
23
¾
¾
ns
tWR
SHR Pulse Width
3.0V
¾
11
¾
¾
ns
tWD
SHD Pulse Width
3.0V
¾
11
¾
¾
ns
tDR
SHR Sampling Aperture
3.0V
¾
¾
¾
4
ns
tDD
SHD Sampling Aperture
3.0V
¾
¾
¾
4
ns
tPSUP
Data Pulse Setup
3.0V
¾
2
¾
¾
ns
tHOLD
Data Pulse Hold
3.0V
¾
5
¾
¾
ns
tSP
Sampling Pulse Non-overlay
3.0V
¾
1
¾
¾
ns
tSUPE
Enable Pulse Setup
3.0V
¾
10
¾
¾
ns
tHOLDE
Enable Pulse Hold
3.0V
¾
10
¾
¾
ns
tSUPOC
OUTCK Setup
3.0V
¾
0
¾
¾
ns
tHOLDOC
OUTCK Hold
3.0V
¾
10
¾
¾
ns
tDLD
3-state Disable Delay
3.0V Active ® High-Z
¾
20
¾
ns
tDLE
3-state Disable Delay
3.0V High-Z® Active
¾
20
¾
ns
tOL
ADC Output Data Delay
3.0V
¾
18
¾
ns
Rev. 1.00
¾
4
January 2, 2006
HT82V842A
Functional Description
CDS (Correlated Double Sampling) Circuit
¨
Connect the CCDIN pin to the CCD sensor thru a capacitor. Connect also the REFIN pin to VSS thru a capacitor.
The CDS circuit holds the pre-charge voltage of the
CCD at SHR pulse and do sampling of the CCD pixel
data at SHD pulse. Correlated noise is removed by subtracting the pre-charge voltage from the pixel data level.
CDS could choose a gain setting from 0, 6.02, 12 or
-1.94dB (Mode 3, register D4 and D5 bits). A CDS gain
is controlled by PGA gain. It is recommended to increase the CDS gain then increase the PGA gain to reduce the noise level.
Clamp target (Mode 2 register D5 and D4), input
signals (REFIN and CCDIN) to be clamped are
selectable. The clamp function can be turned off.
Black Level Cancel Circuit
The purpose of a black level cancel circuit is to control
the DC level of the PGA input. The ADC output code at
an optical black period may correspond to the black
level code set up by the register. A black level code of (1
to) 16 to 127 LSB is available (the default is 64 LSB).
While the OBP pin is active a black level cancel loop is
established. In the loop, a comparison is made between
the ADC output code and the black level code, the result
controls the voltage of the OBCAP capacitor. Hence, the
OBCAP voltage settles gradually and the signal level of
the optical black period corresponds to the established
value.
Clamp Circuits
· DC clamp
The DC level of the CCDIN/REFIN input is fixed by an
internal DC clamp circuit. The DC level of the
C-coupled CCD signal at the CDS input is set to
CLPCAP by the internal DC clamp circuit. The clamp
switches are usually turned on at the black level calibration period. The CLPCAP pin connects to VSS thru
a 0.1mF capacitor.
The following conditions will reset the OBCAP capacitor:
· Set the black level reset register to ²1² (Mode 1 regis-
ter D1=1).
· Set the RESET pin to low
· ADIN signal clamp
· Power down by STBY pin or register control
Clamp operation can also be used for the ADIN path.
The clamp voltage is different from the CCDIN/REFIN
signal and it could be turned off by register setting. At
²ADIN signal to ADC² mode, the ADCLP signal controls the ²clamp circuit². Black level calibration circuit
is also controlled by ADCLP at ²ADIN signal to PGA²
mode.
The DC clamping (CCDCLP) is allowed while the OBP
pin is low. The black level cancellation is available at
²ADIN signal to PGA² mode. The black level cancellation is available at the ADCLP period in this mode. The
clamping function and black level canceling function are
done simultaneously.
· Clamp control
¨
Clamp current (Mode 2 register D7). Charge current
can select normal or fast clamp.
C C D
O B
E ffe c tiv e P ix e l
B la n k in g
A D C K
B L K
O B P
C C D C L P
O U T C K
D O
0
~ D O
9
Rev. 1.00
D a ta O u tp u t
B la c k C o d e
5
January 2, 2006
HT82V842A
E ffe c tiv e P ix e l
S ig n a l
B la n k in g
E ffe c tiv e P ix e l
S ig n a l
B la n k in g
O p tic a l B la c k P e r io d
C C D
A D C K
O B P
R e s u ltin g B la c k
C a lib r a tio n L e v e l
( H o ld )
P r e v io u s B la c k
L e v e l
O B C A P
Black Level Calibration Timing
High-speed Black Level Cancellation
gain (D3~D0=5¢b0). By setting the register D2~D0, the
gain becomes high by 1 to 7 times that of the OBP pulse
period after any access to the serial interface. After that
period, the gain returns to low. When setting D3 to 1¢b1,
the gain is always high. The CS signal becomes the
starting point of the OBP pulse count.
The HT82V842A has a high speed black level cancellation function, which by means of a register setting enhances the settling speed within a fixed period from
access to the serial interface. It increases the gain of the
setting DAC within a fixed period and in turn increases
the charge/discharge current to the OBCAP capacitor.
The following figure shows the black loop settling gain
boost timing chart when the boost control is on (D3=²0²)
and the boost period is set to 3.
The Mode 3 register D3 to D0 data controls the black
level boost function. The default setting is always low
C S
tS
tH
U C S
C S
O B P
C o u n te r
0
B la c k lo o p
g a in
1
2
3
H ig h g a in
3
L o w
0
g a in
1
2
0
1
2
H ig h g a in
Black Loop Settling Gain Boost Timing
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
tSUCS
CS Setup Time
¾
10
¾
¾
ns
tHCS
CS Hold Time
¾
10
¾
¾
ns
Gain Control Circuit
· The signal from the CCDIN input through a CDS and
PGA.
The total gain for a CCD input signal covers from
-1.94dB to 36dB. The CDS range is 0/6/12/-1.94 dB.
The PGA rough is 0/6/12/18dB and ADC fine is 0 to
6dB, 0.047dB/step. The CDS gain is controlled by a
2-bit register and the PGA gain is controlled by a 9-bit
register.
· The signal from the ADIN input through an PGA at the
ADIN mode.
· The signal from the ADIN input at the ADIN mode.
A/D Conversion Range
The analog input range of the ADC is determined by the
internal reference voltage. The full scale of the ADC is
1.0 VPP.
A/D Converter Circuit
The HT82V842A includes one 20MHz 10 bits AD converter. The ADC converts the following signals.
Rev. 1.00
6
January 2, 2006
HT82V842A
A/D Converter Output Code (Mode 1 Register D5=1)
ing edge of the ADCK input after a 5.5 clock of pipeline
delay.
The format of an ADC digital output is a straight binary.
When in the input zero reference voltage, the output
code will be all zero and when the input is a full scale
voltage, the output code will be all one.
High-Z Control of ADC Digital Output
ADC digital outputs become High-Z under the following
conditions:
Clock, Pipeline Delay, Digital Data Output Timing
· Set the ADC output bit to one. (Mode 1 register D2=1)
· Set the STBY pin to low
The ADCK input is used for an A/D conversion. The
ADC input signal is sampled at the falling edge of the
ADCK input and 10 bits parallel data is output at the ris-
· Set the power control bit to one (Mode 1 register
D0=1)
Digital Output Code
A/D Input
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
1
1
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
0
0
:
0
1
1
1
1
1
1
1
1
1
:
:
:
:
:
:
:
:
:
:
:
Zero Scale
0
0
0
0
0
0
0
0
0
0
Full Scale
ADC Data Output (Coding: Straight Binary)
Polarity Inversion
Miscellaneous Function
(ADC Direct Input, ADIN Mode)
The following input polarities can be inverted by register
setting:
The direct input path to the ADC or the PGA is achieved
by means of a register setting. The selectable paths are
as follows:
· ADCK (A/D converter sampling clock, Mode 1 register
D6)
· Function disable (default, Mode 1 register D5=0,
· SHR and SHD (CDS sampling clock, Mode 2 register
D4=0)
D3 and D2)
· ADIN input to the PGA (Mode 1 register D5=0, D4=1)
· BLK, OBP, CCDCLP and ADCLP (Mode 2 register D3
· ADIN input to the PGA (Mode 1 register D5=1,
and D2)
D4=Don¢t care)
Data Output Clock
The BLK, SHD and SHR inputs are ignored at the ADIN
mode.
The ADCK input or the OUTCK input is selectable as an
ADC data output clock.
Power Down Mode
Serial Interface Circuit
The power down mode can be set either by register setting or by the STBY pin.
The internal registers of the HT82V842A are controlled
by a 3-wire serial interface. The data is a 16-bit length
serial data that consists of a 2-bit operation code, 4 bits
address and 10 bits data. Each bit is fetched at the rising
edge of the CS input. Keep CS to high when not access
HT82V842A. It is prohibited to write to a non-defined address. When a data length is below 16 bits, the data is
not executed.
Monitor Output
When setting Mode 2 (D1 and D0), the signal from
MONOUT is selectable. The alternatives are OFF, CDS
output, PGA output or REFIN/CCDIN output. The
MONOUT pin gain is fixed to 0dB regardless of the gain
control register setting when the CDS output is selected.
The MONOUT level becomes VCOM at zero reference
level. The signals are output in reverse for the CCD input.
Rev. 1.00
Registers
The HT82V842A has 10 bits´7 registers that control the
operations. All registers are write only, the serial registers are written by the serial interface.
7
January 2, 2006
HT82V842A
R/W
Address
Register Name
Function Description
A3
A2
A1
A0
W
0
0
0
0
Mode 1
DOUT timing control/OUTCK polarity/ADCK polarity/ADIN connection/ADC output/Black level reset/Power down
W
0
0
0
1
Mode 2
Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor
selection
W
0
0
1
0
Mode 3/CDS gain
CDS gain control/Black loop gain boost/Boost period
W
0
0
1
1
PGA gain
PGA gain
W
0
1
0
0
Black level
ADC code at black level (1 LSB step)
Register Map
Register Bit Assignment
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
0
0
0
0
0
0
0
0
0
Mode 1
Default
Functions
Ö
DOUT timing control
Ö
OUTCK polarity
Ö
ADCK polarity
ADIN connection
-----Ö
Reserved
Ö
ADC output
Ö
Black level reset
Ö
Power down
Mode 2
Default
X
X
0
0
0
0
0
0
0
0
Functions
Ö
Clamp current
Ö
ADIN clamp
Clamp target
------
S/H, enable logic
------
Monitor selection
------
Mode 3
Default
X
X
X
X
0
0
0
0
0
0
Functions
CDS gain control
-----Ö
Black loop gain boost
Boost period
---------------------------
PGA Gain
Default
X
0
0
0
0
0
0
0
0
0
Functions
PGA gain
----------------------------------------------------------------------------------------------------
Black Level
Default
X
X
X
1
0
0
0
0
0
0
Functions
Black level
Rev. 1.00
------------------------------------------------------------------------
8
January 2, 2006
HT82V842A
Register Operations
Control
Operations
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mode 1
DOUT timing control
OUTCK polarity
0
DOUT synchronizes to ADCK
1
DOUT synchronizes to OUTCK
0
DOUT changes at OUTCK rising edge
1
DOUT changes at OUTCK falling edge
0
ADCK polarity
Normal operation as timing chart
1
ADIN connection
ADCK clock inversion
0
0
ADIN function OFF
0
1
ADIN signal to PGA
1
x
ADIN signal to ADC
0
Reserved
Reserved
1
ADC output
Reserved
0
Normal operation, ADC data output
1
ADC output high-Z, or logic of STBY
0
Black level reset
1
Normal operation
Black level reset, or logic of RESET
0 Normal operation
Power down
1 Power down, or logic of STBY
Mode 2
Clamp current
ADIN clamp
Clamp target
Normal clamp ±50mA
0
Fast clamp ±100mA
1
0
Clamp operation active for ADIN
1
No clamp for ADIN
0
0
Normal mode, clamp both REFIN and CCDIN
0
1
Clamp REFIN only
1
0
Clamp CCDIN only
1
1
S/H, enable logic
Clamp off
0
0
Normal operation as timing chart
0
1
S/H control polarity inversion
1
0
Enable control polarity inversion
1
1
Both of S/H and enable inversion
Monitor selection
0
0 Monitor off
0
1 CDS signal to monitor
1
0 PGA output monitor
1
1 Output REFIN and CCDIN
Mode 3
CDS gain control
Black loop gain boost
Rev. 1.00
0
0
CDS gain=odB
0
1
CDS gain=6.02dB
1
0
CDS gain=12.04dB
1
1
CDS gain=-1.94dB
0
Boost control on
1
Always high gain
9
January 2, 2006
HT82V842A
Control
Operations
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Boost period
0
0
0
0 Always low gain
0
0
0
1 High gain for 1 OBP pulse
0
0
1
0 High gain for 2 OBP pulse
0
0
1
1 High gain for 3 OBP pulse
0
1
0
0 High gain for 4 OBP pulse
0
1
0
1 High gain for 5 OBP pulse
0
1
1
0 High gain for 6 OBP pulse
0
1
1
1 High gain for 7 OBP pulse
Control
Decimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
1 1
1
0.046
0
0
0
0
0
0
0
0
1
0 2
2
0.093
0
0
0
0
0
0
0
0
1
1 3
3
0.142
0
0
0
0
0
0
0
1
0
0 4
4
0.187
¯
¯
¯
0
0
0
0
1
1
1
1
1
0 62
3E
2.915
0
0
0
0
1
1
1
1
1
1 63
3F
2.962
0
0
0
1
0
0
0
0
0
0 64
40
3.011
0
0
0
1
0
0
0
0
0
1 65
41
3.056
¯
¯
¯
0
0
0
1
1
1
1
1
1
1 127
7F
5.972
0
0
1
0
0
0
0
0
0
0 128
80
6.021
0
0
1
0
0
0
0
0
0
1 129
81
6.058
¯
¯
¯
C0
9.031
¯
¯
¯
¯
0
0
1
1
0
0
0
0
0
¯
0 192
¯
0
0
1
1
1
1
1
1
1
1 255
FF
11.994
0
1
0
0
0
0
0
0
0
0 256
100
12.041
0
1
0
0
0
0
0
0
0
1 257
101
12.087
0
1
0
1
0
0
0
0
0
0 320
¯
¯
¯
¯
¯
¯
140
15.05
¯
¯
0
1
0
1
1
1
1
1
1
1 383
17F
18.14
0
1
1
0
0
0
0
0
0
0 384
180
18.061
0
1
1
0
0
0
0
0
0
1 385
181
18.108
0
1
1
1
0
0
0
0
0
0 448
¯
¯
0
1
1
1
1
1
1
1
1
0 510
1FE
23.987
0
1
1
1
1
1
1
1
1
1 511
1FF
24.032
¯
¯
¯
Rev. 1.00
PGA Gain (dB)
0
¯
PGA gain
HEX
¯
10
¯
¯
1C0
21.071
January 2, 2006
HT82V842A
Operation, ADC Code
Black Code
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Decimal
HEX
0
0
0
0
0
0
0 Forbidden
Forbidden
0
0
0
0
0
0
1 1
1
¯
¯
¯
0
0
0
1
1
1
1 15
F
0
0
1
0
0
0
0 16
10
0
0
1
0
0
0
1 17
11
0
0
1
0
0
1
0 18
12
0
0
1
0
0
1
1 19
13
¯
Black level
0
1
0
0
¯
0
0
0 32
¯
1
0
0
1
1
1
1
1
1
1
0
¯
20
¯
¯
0
0
0 64
1
1
0
0 124
7C
1
1
1
0
1 125
7D
1
1
1
1
1
0 126
7E
1
1
1
1
1
1 127
7F
¯
40
¯
¯
Timing Diagrams
tD
tD
R
D
C C D
R e fe r e n c e S a m p lin g
D a ta S a m p lin g
tW
R
S H R
tW
D
tP
tS
S U P
P
S H D
tC
tH
Y C
O L D
A D C K
B L
O B
C C D C L
A D C L
P
tH
K
P
P
O L D E
tH
tH
tS
O L D C
tL
tS
U P E
U P O C
O U T C K
tO
D O
0
Rev. 1.00
~ D O
L
9
11
January 2, 2006
HT82V842A
AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1)
0 .7 A V
D D
A D C K
0 .3 A V
F a llin g E d g e
A D C
N + 1
N + 6
N + 5
N + 4
N
In p u t
D D
S a m p lin g P o in t
0 .7 A V
D D
O U T C K
0 .3 A V
tD
D ig ita l O u tp u t
N -6
N -2
N -5
D D
L
N -1
N
ADC Direct Input Chart
A D C K
A D C K
R is in g E d g e
A D C K In p u t
N + 1
tH
N
tS
O L D C
U P O C
O U T C K
S a m p lin g P o in t
OUTCK Timing Chart
ADCK Inversion Chart
These figures are shown when the Mode 1 D8 bit is set to ²1², and an external clock is input to the OUTCK pin. When
setting D8 bit to ²0², the ADCK is used as OUTCK.
Note:
At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at
the rising edge of the OUTCK clock. Set the ADCK polarity register to ²1² when the data are sampled and are
output at the falling edge of the ADCK clock.
The diagram on the upper portion of this page shows the default timing and the lower left figure shows the inverted timing.
Delay from data sampling to data output
ADCK normal: At Mode 1 register D6=0; 5.5 clk delay
ADCK inversion: At Mode 1 register D6=1; 6.0 clk delay
In ADIN input mode, the above mentioned register setting is available.
At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks.
ADCK Clock Waveform
tH
0 .7 V
D D
0 .3 V
D D
tR
tL
tF
tC
Rev. 1.00
12
Y C
January 2, 2006
HT82V842A
Control Interface Timing
Symbol
VSS=0V, Ta=25°C)
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
SCYC
SCK Clock Frequency
3.0V
¾
¾
¾
10
MHz
SLO
SCK Clock Low Level Width
3.0V
¾
40
¾
¾
ns
SHI
SCK Clock High Level Width
3.0V
¾
40
¾
¾
ns
SSU
Data Setup Time Period
3.0V
¾
20
¾
¾
ns
SH
Data hold Time Period
3.0V
¾
20
¾
¾
ns
SR
SCK, CS Rising Time Period
3.0V 30%®70%
¾
¾
6
ns
SF
SCK, CS Falling Time Period
3.0V 70%®30%
¾
¾
6
ns
SNUM
Number of Serial Data
3.0V
¾
¾
16
¾
pcs
C S
S
S
S U
S
S
C Y C
S
L O
S
O 0
V
D D
5 0 %
V
D D
5 0 %
V
D D
H
H I
S C K
S D A T A
5 0 %
O 1
S
S U
H
A 0 ...
D 8
S
D 9
N U M
Serial I/F Timing Chart
Data Output Sequence
C C D
0
1
2
3
4
5
6
7
8
S H R
S H D
A D C K
O U T C K
B L K
D O
0
~ D O
9
B la c k L e v e l C o d e
0
1
2
3
Pixel Data Readout Sequence (1): Start of Conversion
Rev. 1.00
13
January 2, 2006
HT82V842A
C C D
(N -1 )
N
S H R
S H D
A D C K
O U T C K
B L K
D O
~ D O
0
N -8
9
N -7
N -6
N -5
N -4
N -3
N -2
N -1
N
B la c k L e v e l C o d e
Pixel Data Readout Sequence (2): End of Conversion
Clock Timing Variations by Register Setting
Clock timing variations when it is inverted by register settings.
· No inversion
Mode 1 register D6=0, Mode 2 register D2=0; Default
C C D
S H R
S H D
A D C K
O U T C K
D O
0
~ D O
9
Pulse Control (Default: No Inversion)
Rev. 1.00
14
January 2, 2006
HT82V842A
· ADCK inversion
Mode 1 register D6=1, Mode 2 register D2=0
C C D
S H R
S H D
A D C K
O U T C K
~ D O
D O
0
9
Pulse Control (ADCK Inversion)
· SHR & SHD inversion
Mode 1 register D6=0, Mode 2 register D2=1
C C D
S H R
S H D
A D C K
O U T C K
~ D O
D O
0
9
Pulse Control (SHR & SHD Inversion)
· ADCK, SHR & SHD inversion
Mode 1 register D6=1, Mode 2 register D2=1
C C D
S H R
S H D
A D C K
O U T C K
D O
0
~ D O
9
Pulse Control (ADCK, SHR & SHD Inversion)
Rev. 1.00
15
January 2, 2006
HT82V842A
Application Circuits
0 .1 m F
P o w e r In
3 7
D O 0
D O 1
D O 2
D O 3
D O 4
V S S
R E S E T
V D D
N C
V R N
V R P
5
3 8
3 9
4 0
4 1
4 2
V D D
D O 5
D O 6
3
4
V S S
S T B Y
0 .1 m F
6
7
V D D
8
V S S
9
V S S
B L K
C C D IN
A D C L P /C C D C L P
3 6
3 5
P o w e r In
3 4
3 3
0 .1 m F
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
S H D
S H R
A D C K
N C
V S S
2 4
2 3
2 2
2 1
2 0
1 9
*
0 .1 m F
1 8
1 7
1 6
0 .1 m F
N C
N C
1 5
1 4
1 3
0 .1 m F
0* * . 1 m F
V D D
R E F IN
M O N O U T
V C O M
C C D
0 .1 m F
N C
O B C A P
0 .1 m F
O B P
A D IN
1 2
S D A T A
S C K
C L P C A P
1 1
0 .1 m F
C S
H T 8 2 V 8 4 2 A
V D D
0 .1 m F
1 0
Note:
4 3
4 4
4 5
4 6
O U T C K
V D D
0 .1 m F
1 0 m F
D O 7
N C
2
0 .1 m F
D O 8
D O 9
1
4 7
4 8
P o w e r In
P o w e r In
²*² Pin 18 can also connect to ground with a 4.7kW resistor.
²**² The capacitor connects to OBCAP pin maybe need adjust by user¢s applications from 0.1mF~1mF typically.
Rev. 1.00
16
January 2, 2006
HT82V842A
Package Information
48-pin LQFP (7´7) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
A
Rev. 1.00
1 2
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
17
January 2, 2006
HT82V842A
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533
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Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
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709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
18
January 2, 2006
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