Data Sheet

BUK9Y53-100B
N-channel TrenchMOS logic level FET
Rev. 01 — 30 August 2007
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package
using NXP High-Performance Automotive (HPA) TrenchMOS technology.
1.2 Features
n Very low on-state resistance
n 175 °C rated
n Q101 compliant
n Logic level compatible
1.3 Applications
n Automotive systems
n Motors, lamps and solenoids
n General purpose power switching
n 12 V, 24 V and 42 V loads
1.4 Quick reference data
n EDS(AL)S ≤ 85 mJ
n ID ≤ 23 A
n RDSon = 45 mΩ (typ)
n Ptot ≤ 75 W
2. Pinning information
Table 1.
Pin
Pinning
Description
Simplified outline
Symbol
mb
D
1, 2, 3 source (S)
4
gate (G)
mb
mounting base; connected to drain (D)
G
1 2 3 4
SOT669 (LFPAK)
mbl798
S1 S2 S3
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Type number
BUK9Y53-100B
Package
Name
Description
Version
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDS
drain-source voltage
VDGR
drain-gate voltage (DC)
VGS
gate-source voltage
ID
drain current
Conditions
RGS = 20 kΩ
Min Max
Unit
-
100
V
-
100
V
-
±15
V
Tmb = 25 °C; VGS = 5 V; see Figure 2 and 3
-
23
A
Tmb = 100 °C; VGS = 5 V; see Figure 2
-
16
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
-
94
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 1
-
75
W
Tstg
storage temperature
−55 +175 °C
Tj
junction temperature
−55 +175 °C
Source-drain diode
IDR
reverse drain current
Tmb = 25 °C
-
23
A
IDRM
peak reverse drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
94
A
unclamped inductive load; ID = 23 A;
VDS ≤ 100 V; VGS = 5 V; RGS = 50 Ω; starting at
Tj = 25 °C
-
85
mJ
-
[1]
-
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source avalanche
energy
EDS(AL)R
repetitive drain-source avalanche
energy
[1]
Conditions:
a) Maximum value not quoted. Repetitive rating defined in Figure 16.
b) Single-pulse avalanche rating limited by Tj(max) of 175 °C.
c) Repetitive avalanche rating limited by Tj(avg) of 170 °C.
d) Refer to application note AN10273 for further information.
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
2 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab844
120
Pder
(%)
003aab225
30
ID
(A)
80
20
40
10
0
0
0
50
100
150
200
0
50
100
Tmb (°C)
150
200
Tmb (°C)
VGS ≥ 5 V
P tot
P der = ------------------------ × 100 %
P tot ( 25°C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Continuous drain current as a function of
mounting base temperature
003aab226
103
ID
(A)
Limit RDSon = VDS / ID
102
tp = 10 µs
100 µs
10
DC
1
1 ms
10 ms
100 ms
10−1
1
102
10
103
VDS (V)
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
3 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol
Parameter
Rth(j-mb)
thermal resistance from junction to mounting base see Figure 4
Conditions
Min
Typ
Max
Unit
-
-
2
K/W
003aab219
1
Zth(j−mb)
(K/W)
1
δ = 0.5
0.2
0.1
10−1
δ=
P
0.05
tp
T
0.02
10−2
10−6
t
tp
single pulse
T
10−5
10−4
10−3
10−2
10−1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
4 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
100
-
-
V
Tj = −55 °C
89
-
-
V
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V
gate-source threshold voltage
drain leakage current
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
1.1
1.5
2
V
Tj = 175 °C
0.5
-
-
V
Tj = −55 °C
-
-
2.3
V
VDS = 100 V; VGS = 0 V
Tj = 25 °C
-
0.02
1
µA
Tj = 175 °C
-
-
500
µA
-
2
100
nA
VGS = ±15 V; VDS = 0 V
IGSS
gate leakage current
RDSon
drain-source on-state resistance VGS = 5 V; ID = 10 A; see Figure 6 and 8
Tj = 25 °C
-
45
53
mΩ
Tj = 175 °C
-
-
132
mΩ
VGS = 4.5 V; ID = 10 A
-
-
59
mΩ
VGS = 10 V; ID = 10 A
-
41
49
mΩ
ID = 15 A; VDS = 80 V; VGS = 5 V;
see Figure 14
-
18
-
nC
-
4.1
-
nC
-
8
-
nC
-
1600
2130
pF
-
141
170
pF
-
60
82
pF
-
18
-
ns
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz;
see Figure 12
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
rise time
-
26
-
ns
td(off)
turn-off delay time
-
52
-
ns
tf
fall time
-
16
-
ns
VDS = 30 V; RL = 2.5 Ω;
VGS = 5 V; RG = 10 Ω
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; see Figure 15
-
0.85
1.2
V
trr
reverse recovery time
-
71
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 30 V
-
83
-
nC
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
5 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab421
60
VGS (V) = 15
5
4
ID
(A)
003aab423
56
RDSon
(mΩ)
3.4
52
40
3.2
48
3
20
2.8
44
2.6
2.4
2.2
0
40
0
2
4
6
8
10
VDS (V)
3
9
12
15
VGS (V)
Tj = 25 °C
Tj = 25 °C; ID = 20 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aab422
100
RDSon
(mΩ)
6
VGS (V) = 3
3.4
80
3.8
4
5
15
03aa29
3
a
2
60
1
40
20
0
10
20
30
40
50
0
-60
0
ID (A)
Tj = 25 °C
120
Tj (°C)
180
R DSon
a = ----------------------------R DSon ( 25°C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
BUK9Y53-100B_1
Product data sheet
60
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
6 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab986
2.5
003aab987
10−1
ID
(A)
VGS(th)
(V)
2.0
10−2
max
min
1.5
typ
min
1.0
typ
max
10−3
10−4
10−5
0.5
10−6
0.0
−60
0
60
120
180
0
1
2
Tj (°C)
3
VGS (V)
Tj = 25 °C; VDS = VGS
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
003aab425
50
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aab418
2500
C
(pF)
gfs
(S)
2000
Ciss
40
15000
1000
30
Coss
500
Crss
20
5
10
15
20
25
30
0
10−1
1
Tj = 25 °C; VDS = 25 V
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
BUK9Y53-100B_1
Product data sheet
102
10
VDS (V)
ID (A)
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
7 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab424
50
ID
(A)
003aab420
5
VGS
(V)
40
4
VDS = 14 V
VDS = 80 V
30
3
20
2
10
Tj = 175 °C
1
Tj = 25 °C
0
0
1
2
3
0
4
0
VGS (V)
5
10
15
20
QG (nC)
Tj = 25 °C; ID = 10 A
VDS = 25 V
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aab419
50
Fig 14. Gate-source voltage as a function of gate
charge; typical values
003aab224
102
IS
(A)
40
IAL
(A)
(1)
30
10
20
(2)
Tj = 175 °C
Tj = 25 °C
10
(3)
0
0.0
0.2
0.4
0.6
0.8
1.0
VSD (V)
VGS = 0 V
1
10−3
10−2
10−1
1
10
tAL (ms)
See Table note 1 of Table 3 Limiting values.
(1) Single-pulse; Tj = 25 °C.
(2) Single-pulse; Tj = 150 °C.
(3) Repetitive.
Fig 15. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
Fig 16. Single-pulse and repetitive avalanche rating;
avalanche current as a function of avalanche
time
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
8 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
X
c
1/2 e
A
(A 3)
A1
C
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
mm
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
06-03-16
MO-235
Fig 17. Package outline SOT669 (LFPAK)
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
9 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK9Y53-100B_01
20070830
Product data sheet
-
-
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
10 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
BUK9Y53-100B_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 30 August 2007
11 of 12
BUK9Y53-100B
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 30 August 2007
Document identifier: BUK9Y53-100B_1
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