4xR0xB_xNv110.pdf

HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Small Package 8-Bit OTP MCU
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features
· LIRC oscillator function for watchdog timer
· Operating voltage:
· All instructions executed in one or two instruction
cycles
fSYS= 4MHz: 2.2V~5.5V
fSYS= 8MHz: 3.0V~5.5V
fSYS= 12MHz: 4.5V~5.5V
· Table read instructions
· 63 powerful instructions
· Up to 0.33ms instruction cycle with 12MHz system
· 6-level subroutine nesting
clock at VDD= 5V
· Bit manipulation instruction
· Sleep mode and wake-up functions to reduce
· Low voltage reset function
power consumption
· 10-pin MSOP, 16-pin NSOP package types
· Oscillator types:
External high frequency Crystal
External RC
Internal RC
External low frequency crystal
Watchdog Timer internal RC oscillator
Peripheral Features
· Up to 10 bidirectional I/O lines
· 4 channel 12-bit ADC
· 1 channel 8-bit PWM
· Three operational modes: Normal, Slow, Sleep
· External interrupt input shared with an I/O line
· Fully integrated internal 4MHz, 8MHz and 12MHz
· Two 8-bit programmable Timer/Event
oscillator requires no external components
Counter with overflow interrupt and prescaler
· OTP Program Memory: 1K´15 ~ 2K´15
· Time-Base function
· RAM Data Memory: 96´8
· Programmable Frequency Divider - PFD
· Watchdog Timer function
General Description
The Small Package MCUs are a series of 8-bit high performance, RISC architecture microcontrollers specifically designed for a wide range of applications. The
usual Holtek microcontroller features of low power consumption, I/O flexibility, timer functions, oscillator options, power down and wake-up functions, watchdog
timer and low voltage reset, combine to provide devices
with a huge range of functional options while still main-
Rev.1.10
taining a high level of cost effectiveness. The fully integrated system oscillator HIRC, which requires no
external components and which has three frequency
selections, opens up a huge range of new application
possibilities for these devices, some of which may include industrial control, consumer products, household
appliances subsystem controllers, etc.
1
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Selection Table
Part No.
Program
Data
Memory Memory
I/O
8-bit Time
Timer Base
Interrupt
Ext.
Int.
A/D
PWM
Stack
Package
HT48R01B
1K´15
96´8
8
2
1
1
3
¾
¾
6
10MSOP
HT48R02B
2K´15
96´8
8
2
1
1
3
¾
¾
6
10MSOP
HT46R01B
1K´15
96´8
8
2
1
1
4
12-bit´4
8-bit´1
6
10MSOP
HT46R02B
2K´15
96´8
8
2
1
1
4
12-bit´4
8-bit´1
6
10MSOP
HT48R01N
1K´15
96´8
10
2
1
1
3
¾
¾
6
16NSOP
HT48R02N
2K´15
96´8
10
2
1
1
3
¾
¾
6
16NSOP
HT46R01N
1K´15
96´8
10
2
1
1
4
12-bit´4
8-bit´1
6
16NSOP
HT46R02N
2K´15
96´8
10
2
1
1
4
12-bit´4
8-bit´1
6
16NSOP
Block Diagram
The following block diagram illustrates the main functional blocks.
L o w
V o lta g e
R e s e t
P W M
D r iv e r
O T P
P ro g ra m
M e m o ry
R A M
D a ta
M e m o ry
P F D
D r iv e r
W a tc h d o g
T im e r
I/O
P o rts
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
In te rru p t
C o n tr o lle r
E x te rn a l
R C /X T
O s c illa to r
A /D
C o n v e rte r
Rev.1.10
T im e r s
T im e
B a s e
2
In te rn a l
O s c illa to r
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Pin Assignment
P A 3 /IN T
1
1 0
P A 4 /T C 1
P A 3 /IN T /A N 3
1
1 0
P A 2 /T C 0
2
9
P A 5 /O S C 2
P A 2 /T C 0 /A N 2
2
9
P A 5 /O S C 2
P A 1 /P F D
3
8
P A 6 /O S C 1
P A 1 /P F D /A N 1
3
8
P A 6 /O S C 1
P A 0
4
7
P A 7 /R E S
P A 0 /A N 0
4
7
P A 7 /R E S
V S S
5
V S S
5
6
V D D
H T 4 8 R 0 1 B /H T 4 8 R 0 2 B
1 0 M S O P -A
6
P A 4 /T C 1 /P W M
V D D
H T 4 6 R 0 1 B /H T 4 6 R 0 2 B
1 0 M S O P -A
P A 3 /IN T
1
1 6
P A 4 /T C 1
P A 3 /IN T /A N 3
1
1 6
P A 4 /T C 1 /P W M
P A 2 /T C 0
2
1 5
P A 5 /O S C 2
P A 2 /T C 0 /A N 2
2
1 5
P A 5 /O S C 2
P A 1 /P F D
3
1 4
P A 6 /O S C 1
P A 1 /P F D /A N 1
3
1 4
P A 6 /O S C 1
P A 0
4
1 3
P A 7 /R E S
P A 0 /A N 0
4
1 3
P A 7 /R E S
P B 0
5
1 2
P B 1
P B 0
5
1 2
P B 1
V S S
6
1 1
V D D
V S S
6
1 1
V D D
N C
7
1 0
N C
N C
7
1 0
N C
N C
8
9
N C
N C
8
9
N C
H T 4 8 R 0 1 N /H T 4 8 R 0 2 N
1 6 N S O P -A
H T 4 6 R 0 1 N /H T 4 6 R 0 2 N
1 6 N S O P -A
Pin Description
HT46R01B/HT46R02B
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
AN0
ADCR
AN
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
AN1
ADCR
AN
PA2
PAPU
PAWK
ST
TC0
¾
ST
¾
External Timer 0 clock input
AN2
ADCR
AN
¾
A/D channel 2
PA3
PAPU
PAWK
ST
INT
¾
ST
¾
External interrupt input
AN3
ADCR
AN
¾
A/D channel 3
PA4
PAPU
PAWK
ST
TC1
¾
ST
PWM
CTRL0
¾
CMOS PWM output
PA5
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC2
CO
¾
PA0/AN0
PA1/PFD/AN1
PA2/TC0/AN2
PA3/INT/AN3
PA4/TC1/PWM
PA5/OSC2
Rev.1.10
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
¾
A/D channel 0
A/D channel 1
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OSC
External Timer 1 clock input
Oscillator pin
3
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Pin Name
Function
OPT
I/T
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
¾
Reset input
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
PA6/OSC1
PA7/RES
Note:
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
The important point to note here is that the PB0 and PB1 pads will not be bounded to pins in the 10-pin MSOP
package. These two pads default to an input state, the designer should set the register PBPU to pull high options. In this way, these two internal pads can be pulled up in order to prevent input pin floating power consumption.
HT48R01B/HT48R02B
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
¾
ST
PA3
PAPU
PAWK
ST
INT
¾
ST
PA4
PAPU
PAWK
ST
TC1
¾
ST
PA5
PAPU
PAWK
ST
OSC2
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
¾
Reset input
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
PA0
PA1/PFD
PA2/TC0
PA3/INT
PA4/TC1
PA5/OSC2
PA6/OSC1
PA7/RES
Rev.1.10
O/T
¾
Description
External Timer 0 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External interrupt input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External Timer 1 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
4
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Note:
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
The important point to note here is that the PB0 and PB1 pads will not be bounded to pins in the 10-pin MSOP
package. These two pads default to an input state, the designer should set the register PBPU to pull high options. In this way, these two internal pads can be pulled up in order to prevent input pin floating power consumption.
HT46R01N/HT46R02N
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
AN0
ADCR
AN
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
AN1
ADCR
AN
PA2
PAPU
PAWK
ST
TC0
¾
ST
¾
External Timer 0 clock input
AN2
ADCR
AN
¾
A/D channel 2
PA3
PAPU
PAWK
ST
INT
¾
ST
¾
External interrupt input
AN3
ADCR
AN
¾
A/D channel 3
PA4
PAPU
PAWK
ST
TC1
¾
ST
PWM
CTRL0
¾
CMOS PWM output
PA5
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC2
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
PB0
PB0
PBPU
ST
CMOS General purpose I/O. Register enabled.
PB1
PB1
PBPU
ST
CMOS General purpose I/O. Register enabled.
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
PA0/AN0
PA1/PFD/AN1
PA2/TC0/AN2
PA3/INT/AN3
PA4/TC1/PWM
PA5/OSC2
PA6/OSC1
PA7/RES
Rev.1.10
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
¾
A/D channel 0
A/D channel 1
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
OSC
External Timer 1 clock input
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
Reset input
5
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Note:
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
HT48R01N/HT48R02N
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
¾
ST
PA3
PAPU
PAWK
ST
INT
¾
ST
PA4
PAPU
PAWK
ST
TC1
¾
ST
PA5
PAPU
PAWK
ST
OSC2
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA7
PAWK
ST
RES
CO
ST
PB0
PB0
PBPU
ST
CMOS General purpose I/O. Register enabled.
PB1
PB1
PBPU
ST
CMOS General purpose I/O. Register enabled.
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
PA0
PA1/PFD
PA2/TC0
PA3/INT
PA4/TC1
PA5/OSC2
PA6/OSC1
PA7/RES
Note:
O/T
¾
Description
External Timer 0 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External interrupt input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External Timer 1 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
Reset input
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
Rev.1.10
6
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................100mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.0
¾
5.5
V
fSYS=12MHz
4.5
¾
5.5
V
¾
0.8
1.2
mA
¾
1.5
2.25
mA
¾
1.4
2.1
mA
¾
2.8
4.2
mA
¾
4
6
mA
¾
5
10
mA
¾
12
24
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
¾
¾
5
mA
¾
¾
10
mA
VDD
VDD
IDD1
IDD2
Operating Voltage
Operating Current
(HXT, HIRC, ERC)
3V
Operating Current
(HXT, HIRC, ERC)
3V
IDD3
Operating Current
(HXT, HIRC, ERC)
IDD4
Operating Current
(HIRC + LXT, Slow Mode)
ISTB1
ISTB2
¾
Standby Current
(LIRC On, LXT Off)
Standby Current
(LIRC Off, LXT Off)
Conditions
No load, fSYS=4MHz
5V
No load, fSYS=8MHz
5V
5V
No load, fSYS=12MHz
3V
No load, fSYS=32768Hz
(LVR disabled, LXTLP=1)
5V
3V
No load, system HALT
5V
3V
No load, system HALT
5V
3V
Standby Current
(LIRC Off, LXT On, LXTLP=1)
5V
VIL1
Input Low Voltage for I/O,
TCn and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O,
TCn and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR1
Low Voltage Reset 1
¾
VLVR = 4.2V
3.98
4.2
4.42
V
VLVR2
Low Voltage Reset 2
¾
VLVR = 3.15V
2.98
3.15
3.32
V
VLVR3
Low Voltage Reset 3
¾
VLVR = 2.1V
1.98
2.1
2.22
V
ISTB3
Rev.1.10
No load, system HALT
7
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
IOL1
3V
I/O Port Sink Current
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
IOL2
3V
PA7 Sink Current
VOL=0.1VDD
5V
RPH
Min.
Typ.
Max.
Unit
4
8
¾
mA
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
0.8
1.2
¾
mA
2.0
3.0
¾
mA
Conditions
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
Note: The standby current (ISTB1~ISTB3) and IDD4 are measured with all I/O pins in input mode and tied to VDD.
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.2V~5.5V
32
¾
4000
kHz
3.0V~5.5V
32
¾
8000
kHz
4.5V~5.5V
32
¾
12000
kHz
3V/5V Ta=25°C
-2%
4
+2%
MHz
3V/5V Ta=25°C
-2%
8
+2%
MHz
-2%
12
+2%
MHz
3V/5V Ta=0~70°C
-5%
4
+5%
MHz
3V/5V Ta=0~70°C
-5%
8
+5%
MHz
Ta=0~70°C
-5%
12
+5%
MHz
2.2V~
Ta=0~70°C
3.6V
-8%
4
+8%
MHz
3.0V~
Ta=0~70°C
5.5V
-8%
4
+8%
MHz
3.0V~
Ta=0~70°C
5.5V
-8%
8
+8%
MHz
4.5V~
Ta=0~70°C
5.5V
-8%
12
+8%
MHz
2.2V~
Ta= -40°C~85°C
3.6V
-12%
4
+12%
MHz
3.0V~
Ta= -40°C~85°C
5.5V
-12%
4
+12%
MHz
3.0V~
Ta= -40°C~85°C
5.5V
-12%
8
+12%
MHz
4.5V~
Ta= -40°C~85°C
5.5V
-12%
12
+12%
MHz
VDD
fSYS
System Clock
¾
5V
5V
fHIRC
Rev.1.10
System Clock
(HIRC)
Conditions
Ta=25°C
8
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
System Clock
(ERC)
fERC
fLXT
System Clock (LXT)
fTIMER
Timer Input Frequency
(TCn)
fLIRC
External Reset Low Pulse Width
System Start-up time Period
Max.
Unit
Ta=25°C, R=120kW *
-2%
4
+2%
MHz
5V
Ta=0~70°C, R=120kW *
-5%
4
+5%
MHz
5V
Ta= -40°C~85°C,
R=120kW *
-7%
4
+7%
MHz
2.2V~ Ta= -40°C~85°C,
5.5V R=120kW *
-11%
4
+11%
MHz
¾
32768
¾
Hz
2.2V~5.5V
0
¾
4000
kHz
3.0V~5.5V
0
¾
8000
kHz
4.5V~5.5V
0
¾
12000
kHz
¾
¾
¾
3V
¾
5
10
15
kHz
5V
¾
6.5
13
19.5
kHz
¾
¾
1
¾
¾
ms
¾
1024
¾
tSYS
¾
2
¾
tSYS
¾
1024
¾
tSYS
For HXT/LXT
tSST
Typ.
5V
LIRC Oscillator
tRES
Min.
Conditions
¾
For ERC/IRC
(By configuration option)
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tRSTD
Reset Delay Time
¾
¾
¾
100
¾
ms
Note:
1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
Rev.1.10
9
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
A/D Converter Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
tAD=0.5ms
-2
¾
2
LSB
tAD=0.5ms
-4
¾
4
LSB
¾
0.5
0.75
mA
¾
1.0
1.5
mA
VDD
DNL
INL
IADC
A/D Converter Differential
Non-Linearity
3V
A/D Converter Integral
Non-Linearity
3V
Additional Power Consumption
if A/D Converter is Used
3V
5V
5V
Conditions
¾
5V
Power-on Reset Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Rev.1.10
10
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility.
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two instruction cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev.1.10
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HT48R01B/02B/01N/02N
Program Counter
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program
Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored
to its previous value from the stack. After a device reset,
the Stack Pointer will point to the top of the stack.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
P ro g ra m
T o p o f S ta c k
Program Counter
High Byte
PCL
Register
HT46R01B/01N
HT48R01B/01N
PC9~PC8
PCL7~PCL0
HT46R02B/02N
HT48R02B/02N
PC10~PC8
PCL7~PCL0
S ta c k
P o in te r
B o tto m
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l 6
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register. By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
· Increment and Decrement INCA, INC, DECA, DEC
Stack
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is neither part of the Data or Program Memory
space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is
Rev.1.10
S ta c k L e v e l 1
S ta c k L e v e l 2
Program Counter
Device
C o u n te r
SIZA, SDZA, CALL, RET, RETI
12
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HT48R01B/02B/01N/02N
Program Memory
program will jump to its respective location and begin
execution if the associated Timer/Event Counter interrupt is enabled and the stack is not full.
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applications which may be useful during debug or for products
requiring frequent upgrades or program changes.
· A/D interrupt vector
This internal vector is used by the A/D converter. If
A/D conversion complete , the program will jump to
this location and begin execution if the A/D interrupt is
enabled and the stack is not full.
· Time base interrupt vector
Structure
This internal vector is used by the internal Time Base.
If a Time Base overflow occurs, the program will jump
to this location and begin execution if the Time Base
counter interrupt is enabled and the stack is not full.
The Program Memory has a capacity of 2K´15. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by separate
table pointer registers.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Reset Vector
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
· External interrupt vector
This vector is used by the external interrupt. If the external interrupt pin on the device receives an edge
transition, the program will jump to this location and
begin execution if the external interrupt is enabled and
the stack is not full. The external interrupt active edge
transition type, whether high to low, low to high or both
is specified in the CTRL1 register.
· Timer/Event 0/1 counter interrupt vector
This internal vector is used by the Timer/Event Counters. If a Timer/Event Counter overflow occurs, the
H T 4 8 R 0 1 B
H T 4 8 R 0 1 N
H T 4 8 R 0 2 B
H T 4 8 R 0 2 N
0 0 H
R e s e t
R e s e t
E x te rn a l
In te rru p t
0 4 H
E x te rn a l
In te rru p t
E x te rn a l
In te rru p t
T im e r 0
In te rru p t
T im e r 0
In te rru p t
0 8 H
T im e r 0
In te rru p t
T im e r 0
In te rru p t
0 C H
T im e r 1
In te rru p t
T im e r 1
In te rru p t
0 C H
T im e r 1
In te rru p t
T im e r 1
In te rru p t
1 0 H
A /D
In te rru p t
A /D
In te rru p t
1 0 H
1 4 H
T im e B a s e
In te rru p t
T im e B a s e
In te rru p t
1 4 H
T im e B a s e
In te rru p t
T im e B a s e
In te rru p t
H T 4 6 R 0 1 B
H T 4 6 R 0 1 N
H T 4 6 R 0 2 B
H T 4 6 R 0 2 N
0 0 H
R e s e t
R e s e t
0 4 H
E x te rn a l
In te rru p t
0 8 H
1 8 H
1 8 H
3 F F H
1 5 b its
3 F F H
7 F F H
1 5 b its
1 5 b its
7 F F H
1 5 b its
Program Memory Structure
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
dress ²F06H² or 6 locations after the start of the last
page. Note that the value for the table pointer is referenced to the first address of the present page if the
²TABRDC [m]² instruction is being used. The high byte
of the table data which in this case is equal to zero will
be transferred to the TBLH register automatically when
the ²TABRDL [m]² instruction is executed.
The following diagram illustrates the addressing/data
flow of the look-up table:
L a s t p a g e o r
p re s e n t p a g e
P C x ~ P C 8
P ro g ra m
H ig h B y te
A d d re s s
P C
T B L P R e g is te r
M e m o ry
D a ta
R e g is te r T B L H
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
U s e r S e le c te d
R e g is te r
H ig h B y te
L o w
B y te
Table Program Example
The accompanying example shows how the table
pointer and table data is defined and retrieved from the
device. This example uses raw table data located in the
last page which is stored there using the ORG statement. The table pointer is setup here to have an initial
value of ²06H². This will ensure that the first data read
from the data table will be at the Program Memory ad-
Instruction
Table Location Bits
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
HT46R01B/HT48R01B/HT46R01N/HT48R01N: PC9~PC8: Current program Counter bits
HT46R02B/HT48R02B/HT46R02N/HT48R02N: PC10~PC8: Current program Counter bits
@[email protected]: Table Pointer TBLP bits
· Table Read Program Example - 1K ROM size
tempreg1 db ?
; temporary register #1
tempreg2 db ?
; temporary register #2
:
:
mov a,06h
; initialise table pointer - note that this address is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl
; transfers value in table referenced by table pointer to tempregl
; data at prog. memory address ²306H² transferred to tempreg1 and TBLH
tempreg1
dec tblp
tabrdl
:
:
org 300h
dc
; reduce value of table pointer by one
tempreg2
;
;
;
;
;
transfers value in table referenced by table pointer to tempreg2
data at prog.memory address ²305H² transferred to tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte register TBLH
; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev.1.10
14
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HT48R01B/02B/01N/02N
Data Memory
Special Purpose Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary information is stored.
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
Structure
Divided into two sections, the first of these is an area of
RAM where special function registers are located. These
registers have fixed locations and are necessary for correct operation of the device. Many of these registers can
be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for
general purpose use. All locations within this area are
read and write accessible under program control.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8
bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address
²00H².
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
0 0 H
IA R 0
0 1 H
M P 0
S p e c ia l
P u rp o s e
R e g is te r s
9 6 b y te s
G e n e ra l
P u rp o s e
R e g is te r s
3 F H
4 0 H
6 R 0 1 B
6 R 0 1 N
R 0
P 0
R 1
P 1
H T 4 6
H T 4 6
IA
M
IA
M
R 0 2 B
R 0 2 N
R 0
P 0
R 1
P 1
H T 4 8
H T 4 8
IA
M
IA
M
R 0 1 B
R 0 1 N
R 0
P 0
R 1
P 1
H T 4 8
H T 4 8
IA
M
IA
M
R 0 2 B
R 0 2 N
R 0
P 0
R 1
P 1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P A P U
P A W K
P B
P B C
P B P U
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P A P U
P A W K
P B
P B C
P B P U
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P A P U
P A W K
P B
P B C
P B P U
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P A P U
P A W K
P B
P B C
P B P U
C T R L 0
C T R L 1
C T R L 0
C T R L 1
C T R L 0
C T R L 1
C T R L 0
C T R L 1
IN T
P W
A D
A D
A D
A C
IN T
P W
A D
A D
A D
A C
IN T C 1
IN T C 1
C 1
M 0
R L
R H
C R
S R
C 1
M 0
R L
R H
C R
S R
3 F H
: U n u s e d , re a d a s "0 0 "
9 F H
Special Purpose Data Memory
Data Memory Structure
Note:
H T 4
H T 4
IA
M
IA
M
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer registers.
Rev.1.10
15
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HT48R01B/02B/01N/02N
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory begins at the address ²00H² and are mapped into Bank 0.
Any unused Data Memory locations between these special function registers and the point where the General
Purpose Memory begins is reserved and attempting to
read data from these locations will return a value of
²00H².
Memory Pointers - MP0, MP1
Indirect Addressing Registers - IAR0, IAR1
Accumulator - ACC
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 with MP0 and IAR1 with MP1 can together access data from the Data Memory. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in
the same way as normal registers providing a convenient way with which to indirectly address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer. The following example shows how to clear a section of four Data Memory
locations already defined as locations adres1 to adres4.
· Indirect Addressing Program Example
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory
addresses.
Rev.1.10
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HT48R01B/02B/01N/02N
Program Counter Low Register - PCL
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Status Register - STATUS
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt routine can change the status register, precautions must be
taken to correctly save it. Note that bits 0~3 of the
STATUS register are both readable and writeable bits.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
· STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TO
PDF
OV
Z
AC
C
R/W
¾
¾
R
R
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
x
x
x
x
²x² unknown
Bit 7, 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev.1.10
Unimplemented, read as ²0²
TO: Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
17
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Input/Output Ports and Control Registers
System Control Registers - CTRL0, CTRL1
Within the area of Special Function Registers, the port
PA, PB, etc data I/O registers and their associated control register PAC, PBC, etc play a prominent role. These
registers are mapped to specific addresses within the
Data Memory as shown in the Data Memory table. The
data I/O registers, are used to transfer the appropriate
output or input data on the port. The control registers
specifies which pins of the port are set as inputs and
which are set as outputs. To setup a pin as an input, the
corresponding bit of the control register must be set
high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O
ports. One flexible feature of these registers is the ability
to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
These registers are used to provide control over various
internal functions. Some of these include the PFD control, PWM control, certain system clock options, the LXT
Oscillator low power control, external Interrupt edge trigger type, Watchdog Timer enable function, Time Base
function division ratio, and the LXT oscillator enable
control.
Wake-up Function Register - PAWK
When the microcontroller enters the Sleep Mode, various methods exist to wake the device up and continue
with normal operation. One method is to allow a falling
edge on the I/O pins to have a wake-up function. This
register is used to select which Port A I/O pins are used
to have this wake-up function.
Pull-high Registers - PAPU, PBPU
The I/O pins, if configured as inputs, can have internal
pull-high resistors connected, which eliminates the need
for external pull-high resistors. This register selects which
I/O pins are connected to internal pull-high resistors.
· CTRL0 Register - HT46R01B/HT46R02B/HT46R01N/HT46R02N
Bit
7
6
5
4
3
2
1
0
Name
¾
PFDCS
R/W
¾
R/W
PWMSEL
¾
PWMC0
PFDC
LXTLP
CLKMOD
R/W
¾
R/W
R/W
R/W
R/W
POR
¾
0
0
¾
0
0
0
0
Bit 7
unimplemented, read as ²0²
Bit 6
PFDCS: PFD clock source
0: timer0
1: timer1
Bit 5
PWMSEL: PWM type selection
0: 6+2
1: 7+1
Bit 4
unimplemented, read as ²0²
Bit 3
PWMC0: I/O or PWM
0: I/O
1: PWM
Bit 2
PFDC: I/O or PFD
0: I/O
1: PFD
Bit 1
LXTLP: LXT oscillator low power control function
0: LXT Oscillator quick start-up mode
1: LXT Oscillator Low Power Mode
Bit 0
CLKMOD: system clock mode selection.
0: High speed - HIRC used as system clock
1: Low speed - LXT used as system clock, HIRC oscillator stopped.
These selections are only valid if the oscillator configuration options
have selected the HIRC+LXT.
Note:
If PWM output is selected by PWMC0 bit, fTP comes always from fSYS.
(fTP is the clock source for timer0/2, time base and PWM)
Rev.1.10
18
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
· CTRL0 Register - HT48R01B/HT48R02B/HT48R01N/HT48R02N
Bit
7
6
5
4
3
2
1
0
Name
¾
PFDCS
¾
R/W
¾
R/W
¾
¾
¾
PFDC
LXTLP
CLKMOD
¾
¾
R/W
R/W
R/W
POR
¾
0
¾
¾
¾
0
0
0
Bit 7
unimplemented, read as ²0²
Bit 6
PFDCS: PFD clock source
0: timer0
1: timer1
Bit 5~3
unimplemented, read as ²0²
Bit 2
PFDC: I/O or PFD
0: I/O
1: PFD
Bit 1
LXTLP: LXT oscillator low power control function
0: LXT Oscillator quick start-up mode
1: LXT Oscillator Low Power Mode
Bit 0
CLKMOD: system clock mode selection.
0: High speed - HIRC used as system clock
1: Low speed - LXT used as system clock, HIRC oscillator stopped.
These selections are only valid if the oscillator configuration options
have selected the HIRC+LXT.
· CTRL1 Register
Bit
7
6
5
4
3
2
1
0
Name
INTEG1
INTEG0
TBSEL1
TBSEL0
WDTEN3
WDTEN2
WDTEN1
WDTEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
1
0
1
0
Bit 7, 6
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Bit 5, 4
TBSEL1, TBSEL0: Time base period selection
00: 210 ´ (1/fTP)
01: 211 ´ (1/fTP)
10: 212 ´ (1/fTP)
11: 213 ´ (1/fTP)
Bit 3~0
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled - Recommended value is 0101
If the ²watchdog timer enable² configuration option is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
Note:
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0=1010.
The WDT is enabled when either the WDT configuration option is enabled or when bits
WDTEN3~WDTEN0¹1010.
Rev.1.10
19
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Oscillator
most resonator types, to ensure oscillation and accurate
frequency generation, it is necessary to add two small
value external capacitors, C1 and C2. The exact values
of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer¢s specification.
Various oscillator options offer the user a wide range of
functions according to their various application requirements. The flexible features of the oscillator functions
ensure that the best optimisation can be achieved in
terms of speed and power saving. Oscillator selections
and operation are selected through a combination of
configuration options and registers.
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
System Oscillator Overview
12MHz
8pF
10pF
In addition to being the source of the main system clock
the oscillators also provide clock sources for the Watchdog Timer and Time Base functions. External oscillators
requiring some external components as well as a two
fully integrated internal oscillators, requiring no external
components, are provided to form a wide range of both
fast and slow system oscillators.
8MHz
8pF
10pF
4MHz
8pF
10pF
100pF
100pF
Type
Name
Freq.
External Crystal
HXT
400kHz~
12MHz
External RC
ERC
400kHz~
12MHz
Internal High Speed RC
HIRC
4, 8 or
12MHz
External Low Speed Crystal
LXT
32768Hz
Internal Low Speed RC
LIRC
13kHz
1MHz
Note:
C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
External RC Oscillator - ERC
Using the ERC oscillator only requires that a resistor,
with a value between 24kW and 1.5MW, is connected
between OSC1 and VDD, and a capacitor is connected
between OSC and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external
capacitor has no influence over the frequency and is
connected for stability purposes only. Device trimming
during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation
frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 120K
resistor connected and with a 5V voltage power supply
and temperature of 25 degrees, the oscillator will have a
frequency of 4MHz within a tolerance of 2%. Here only
the OSC1 pin is used, which is shared with I/O pin PA6,
leaving pin PA5 free for use as a normal I/O pin.
Oscillator Types
System Clock Configurations
There are five system oscillators. Three high speed oscillators and two low speed oscillators. The high speed
oscillators are the external crystal/ceramic oscillator HXT, the external - ERC, and the internal RC oscillator HIRC. The two low speed oscillator are the external
32768Hz oscillator - LXT and the internal 13kHz
(VDD=5V) oscillator - LIRC.
V
D D
External Crystal/Resonator Oscillator - HXT
R
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation. However, for some crystals and
C 1
O S C 1
R p
C 2
R f
O S C 2
O S C
P A 6 /O S C 1
4 7 0 p F
In te r n a l
O s c illa to r
C ir c u it
P A 5 /O S C 2
External RC Oscillator - ERC
T o in te r n a l
c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT
Rev.1.10
20
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Internal RC Oscillator - HIRC
C2 should be selected in consultation with the crystal or
resonator manufacturer¢s specification. The external
parallel feedback resistor, RP, is required. For the device the LXT oscillator must be used together with the
HIRC oscillator.
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal
RC oscillator has three fixed frequencies of either
4MHz, 8MHz or 12MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that
the influence of the power supply voltage, temperature
and process variations on the oscillation frequency are
minimised. As a result, at a power supply of either 3V or
5V and at a temperature of 25 degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock
option is selected, as it requires no external pins for its
operation, I/O pins PA5 and PA6 are free for use as normal I/O pins.
P A 5 /O S C 2
P A 6 /O S C 1
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
32768Hz
8pF
10pF
Note:
1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
32768Hz Crystal Recommended Capacitor Values
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the
Quick Start Mode and the Low Power Mode. The mode
selection is executed using the LXTLP bit in the CTRL0
register.
In te rn a l R C
O s c illa to r
LXTLP Bit
LXT Mode
N o te : P A 5 /P A 6 u s e d a s n o rm a l I/O s
0
Quick Start
Internal RC Oscillator - HIRC
1
Low-power
After power on the LXTLP bit will be automatically
cleared to zero ensuring that the LXT oscillator is in the
Quick Start operating mode. In the Quick Start Mode the
LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can
be placed into the Low-power mode by setting the
LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current
consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery
applications, where power consumption must be kept to
a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds
after power-on.
External 32768Hz Crystal Oscillator - LXT
When the microcontroller enters the Sleep Mode, the
system clock is switched off to stop microcontroller activity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
the internal timers operational even when the
microcontroller is in the Power-down Mode. To do this,
another clock, independent of the system clock, must be
provided. To do this a configuration option exists to allow
a high speed oscillator to be used in conjunction with a a
low speed oscillator, known as the LXT oscillator. The
LXT oscillator is implemented using a 32768Hz crystal
connected to pins OSC1/OSC2. However, for some
crystals, to ensure oscillation and accurate frequency
generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and
In te r n a l
O s c illa to r
C ir c u it
C 1
3 2 7 6 8 H z
It should be noted that, no matter what condition the
LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more
time to start up if in the Low-power mode.
R p
Internal Low Speed Oscillator - LIRC
The LIRC is a fully self-contained free running on-chip
RC oscillator with a typical frequency of 13kHz at 5V requiring no external components. When the device enters the Sleep Mode, the system clock will stop running
but the WDT oscillator continues to free-run and to keep
the watchdog active. However, to preserve power in certain applications the LIRC can be disabled via a configuration option.
In te rn a l R C
O s c illa to r
T o in te r n a l
c ir c u its
C 2
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n p in s h a v e a
p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External LXT Oscillator
Rev.1.10
21
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Operating Modes
By using the LXT low frequency oscillator in combination with a high frequency oscillator, the system can be
selected to operate in a number of different modes.
These Modes are Normal, Slow and Sleep.
OSC1/OSC2 Configuration
Operating
Mode
Mode Types and Selection
HIRC + LXT
HXT
Normal
The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher
power requirements, while the opposite is of course true
for the lower frequency oscillators. With the capability of
dynamically switching between fast and slow oscillators,
the device has the flexibility to optimise the performance/power ratio, a feature especially important in
power sensitive portable applications.
ERC
HIRC
HIRC
LXT
Run
Run
Run
Run
Run
Slow
¾
¾
¾
Stop
Run
Sleep
Stop
Stop
Stop
Stop
Run
²¾² unimplemented
Operating Mode Control
Mode Switching
The devices are switched between one mode and another using a combination of the CLKMOD bit in the
CTRL0 register and the HALT instruction. The CLKMOD
bit chooses whether the system runs in either the Normal or Slow Mode by selecting the system clock to be
sourced from either a high or low frequency oscillator.
The HALT instruction forces the system into either the
Sleep Mode, depending upon whether the LXT oscillator is running or not. The HALT instruction operates independently of the CLKMOD bit condition.
If the LXT oscillator is used then the internal RC oscillator, HIRC, must be used as the high frequency oscillator.
If the HXT or the ERC oscillator is chosen as the high
frequency system clock then the LXT oscillator cannot
be used for sharing the same pins. The CLKMOD bit in
the CTRL0 register can be used to switch the system
clock from the high speed HIRC oscillator to the low
speed LXT oscillator. When the HALT instruction is executed and the device enters the Sleep Mode the LXT oscillator will always continue to run. For the device the
LXT crystal is connected to the OSC1/OSC2 pins and
LXT will always run.
When a HALT instruction is executed and the LXT oscillator is not running, the system enters the Sleep mode
the following conditions exist:
Note that CLKMOD is only valid in HIRC+LXT oscillator
configuration.
· The system oscillator will stop running and the appli-
When the system enters the Sleep Mode, the high frequency system clock will always stop running. The accompanying tables shows the relationship between the
CLKMOD bit, the HALT instruction and the high/low frequency oscillators. The CLMOD bit can change normal
or Slow Mode.
· The Data Memory contents and registers will maintain
f
H X T
cation program will stop at the ²HALT² instruction.
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
or LXT oscillator. The WDT will stop if its clock source
originates from the system clock.
C L K M O D
( D e te r m in e N o r m a l/
S lo w M o d e )
H X T
C o n fig u r a tio n o p tio n
f
E R C
E R C
M U X
H IR C
f
( N o r m a l)
M U X
H IR C
(S L O W
f
f
S Y S
)
L X T
L X T
C o n fig u r a tio n o p tio n
L IR C
f
L IR C
f
M U X
S Y S
T o w a tc h d o g tim e r
/4
System Clock Configurations
Rev.1.10
22
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
· The I/O ports will maintain their present condition.
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the
²HALT² instruction. The TO flag is set if a WDT time-out
occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain
in their original status.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Sleep Mode is to
keep the current consumption of the MCU to as low a
value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised.
Pins PA0 to PA7 can be setup via the PAWK register to
permit a negative transition on the pin to wake-up the
system. When a PA0 to PA7 pin wake-up occurs, the program will resume execution at the instruction following
the ²HALT² instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Sleep Mode, then any future interrupt
requests will not generate a wake-up function of the related interrupt will be ignored.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be connected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
If the configuration options have enabled the Watchdog
Timer internal oscillator LIRC then this will continue to
run when in the Sleep Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer. The LXT, if configured for use, will
also consume a limited amount of power, as it continues
to run when the device enters the Sleep Mode. To keep
the LXT power consumption to a minimum level the
LXTLP bit in the CTRL0 register, which controls the low
power function, should be set high.
No matter what the source of the wake-up event is, once
a wake-up event occurs, there will be a time delay before normal program execution resumes. Consult the table for the related time.
Wake-up
Source
Wake-up
External RES
After the system enters the Sleep Mode, it can be woken
up from one of various sources listed as follows:
PA Port
Interrupt
· An external reset
ERC, IRC
Crystal
tRSTD + tSST1
tRSTD + tSST2
tSST1
tSST2
WDT Overflow
· An external falling edge on PA0 to PA7
Note:
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
Rev.1.10
Oscillator Type
1. tRSTD (reset delay time), tSYS (system clock)
2. tRSTD is power-on delay, typical time=100ms
3. tSST1= 2 or 1024 tSYS
4. tSST2= 1024 tSYS
Wake-up Delay Time
23
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Watchdog Timer
operate in noisy environments, using the LIRC or the
LXT as the clock source is therefore the recommended
choice. The division ratio of the prescaler is determined
by bits 0, 1 and 2 of the WDTS register, known as WS0,
WS1 and WS2. If the Watchdog Timer internal clock
source is selected and with the WS0, WS1 and WS2 bits
of the WDTS register all set high, the prescaler division
ratio will be 1:128, which will give a maximum time-out
period.
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain
uncontrollable external events such as electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the Watchdog
Timer function is not enabled, then any instructions related to the Watchdog Timer will result in no operation.
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Sleep Mode, when a
Watchdog Timer time-out occurs, the device will be
woken up, the TO bit in the status register will be set and
only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external
hardware reset, which means a low level on the external
reset pin, the second is using the Clear Watchdog Timer
software instructions and the third is when a HALT instruction is executed. There are two methods of using
software instructions to clear the Watchdog Timer, one
of which must be chosen by configuration option. The
first option is to use the single ²CLR WDT² instruction
while the second is to use the two commands ²CLR
WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the Watchdog Timer
while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully
clear the Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will have
no effect, only the execution of a ²CLR WDT2² instruction will clear the Watchdog Timer. Similarly after the
²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.
Setting up the various Watchdog Timer options are controlled via the configuration options and two internal registers WDTS and CTRL1. Enabling the Watchdog Timer
can be controlled by both a configuration option and the
WDTEN bits in the CTRL1 internal register in the Data
Memory.
Configuration
Option
CTRL1
Register
WDT
Function
Disable
Disable
OFF
Disable
Enable
ON
Enable
x
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits
WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration option is disable. This will be the condition when the device
is powered up. Although any other data written to
WDTEN3~WDTEN0 will ensure that the Watchdog
Timer is enabled, for maximum protection it is recommended that the value 0101B is written to these bits.
The Watchdog Timer clock can emanate from three different sources, selected by configuration option. These
are LXT, fSYS/4, or LIRC. It is important to note that when
the system enters the Sleep Mode the instruction clock is
stopped, therefore if the configuration options have selected fSYS/4 as the Watchdog Timer clock source, the
Watchdog Timer will cease to function. For systems that
C L R
W D T 1 F la g
C L R
W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
/4
L X T
L IR C
Y S
C L R
C o n fig .
O p tio n
S e le c t
fW
D T C K
W D T C lo c k S o u r c e S e le c tio n
1 5 s ta g e c o u n te r
W D T T im e - o u t
W S 2 ~ W S 0
Watchdog Timer
Rev.1.10
24
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
· WDTS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
WS2
WS1
WS0
R/W
¾
¾
¾
¾
¾
R/W
R/W
R/W
POR
¾
¾
¾
¾
¾
1
1
1
Bit 7~3 :
unimplemented, read as ²0²
Bit 2~0
WS2, WS1, WS0: WDT time-out period selection
000: 28 tWDTCK
001: 29 tWDTCK
010: 210 tWDTCK
011: 211 tWDTCK
100: 212 tWDTCK
101: 213 tWDTCK
110: 214 tWDTCK
111: 215 tWDTCK
Reset and Initialisation
· Power-on Reset
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
R E S
D D
t RR
SS TT DD ++
t SS
SS TT
In te rn a l R e s e t
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
Note: tRSTD is power-on delay, typical time=100ms
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
Reset Functions
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
Rev.1.10
0 .9 V
25
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
V
· Watchdog Time-out Reset during Normal Operation
D D
0 .0 1 m F * *
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
V D D
1 N 4 1 4 8 *
1 0 k W ~
1 0 0 k W
W D T T im e - o u t
tR
R E S /P A 7
3 0 0 W *
S T
WDT Time-out Reset during Normal Operation
Timing Chart
²*² It is recommended that this component is
added for added ESD protection
²**² It is recommended that this component is
added in environments where power line noise
is significant
· Watchdog Time-out Reset during Sleep mode
The Watchdog time-out Reset during Sleep mode is a
little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
External RES Circuit
W D T T im e - o u t
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
tS
WDT Time-out Reset during Sleep
Timing Chart
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
0 .9 V
S T
In te rn a l R e s e t
· RES Pin Reset
0 .4 V
tS
Note: tRSTD is power-on delay, typical time=100ms
V S S
R E S
+
In te rn a l R e s e t
0 .1 ~ 1 m F
Note:
S T D
Note:
The tSST can be chosen to be either 1024 or 2
clock cycles via configuration option if the system clock source is provided by ERC or HIRC.
The SST is 1024 for HXT or LXT.
D D
Reset Initial Conditions
D D
tR
S T D
+
tS
S T
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the Sleep
function or Watchdog Timer. The reset flags are shown
in the table:
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=100ms
RES Reset Timing Chart
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
TO
PDF
RESET Conditions
0
0
Power-on reset
u
u
RES or LVR reset during Normal or Slow
Mode operation
1
u
WDT time-out reset during Normal or
Slow Mode operation
1
1
WDT time-out reset during Sleep Mode
operation
Note: ²u² stands for unchanged
L V R
tR
S T D
+
tS
S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=100ms
Low Voltage Reset Timing Chart
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
The following table indicates the way in which the various components of the microcontroller are affected after a
power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will be cleared
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
HT46R01B/HT46R02B/HT46R01N/HT46R02N
Power-on
Reset
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(Sleep)
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
---- -111
---- -111
---- -111
---- -uuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
Register
INTC1
--00 --00
--00 --00
--00 --00
--uu --uu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWK
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAPU
-000 0000
-000 0000
-000 0000
-uuu uuuu
PB
---- --11
---- --11
---- --11
---- --uu
PBC
---- --11
---- --11
---- --11
---- --uu
PBPU
---- --00
---- --00
---- --00
---- --uu
CTRL0
-00- 0000
-00- 0000
-00- 0000
-uu- uuuu
CTRL1
1000 1010
1000 1010
1000 1010
uuuu uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Rev.1.10
27
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Power-on
Reset
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(Sleep)
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
10-- -000
10-- -000
10-- -000
uu-- -uuu
Power-on
Reset
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(Sleep)
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
---- -111
---- -111
---- -111
---- -uuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
--0- --0-
--0- --0-
--0- --0-
--u- --u-
Register
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Note:
HT48R01B/HT48R02B/HT48R01N/HT48R02N
Register
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWK
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAPU
-000 0000
-000 0000
-000 0000
-uuu uuuu
PB
---- --11
---- --11
---- --11
---- --uu
PBC
---- --11
---- --11
---- --11
---- --uu
PBPU
---- --00
---- --00
---- --00
---- --uu
CTRL0
-0-- -000
-0-- -000
-0-- -000
-u-- -uuu
CTRL1
1000 1010
1000 1010
1000 1010
uuuu uuuu
Note:
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Rev.1.10
28
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. Most pins can have either an input or output designation under user program control. Additionally, as there are pull-high resistors and wake-up
software configurations, the user is provided with an I/O
structure to meet the needs of a wide range of application possibilities.
tors are implemented using weak PMOS transistors.
Note that pin PA7 does not have a pull-high resistor selection.
Port A Wake-up
If the HALT instruction is executed, the device will enter
the Sleep Mode, where the system clock will stop resulting in power being conserved, a feature that is important
for battery and other low-power applications. Various
methods exist to wake-up the microcontroller, one of
which is to change the logic condition on one of the
PA0~PA7 pins from high to low. After a HALT instruction
forces the microcontroller into entering the Sleep Mode,
the processor will remain in a low-power state until the
logic condition of the selected wake-up pin on Port A
changes from high to low. This function is especially suitable for applications that can be woken up via external
switches. Note that pins PA0 to PA7 can be selected individually to have this wake-up feature using an internal
register known as PAWK, located in the Data Memory.
For input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external
resistor. To eliminate the need for these external resistors, when configured as an input have the capability of
being connected to an internal pull-high resistor. These
pull-high resistors are selectable via a register known as
PAPU located in the Data Memory. The pull-high resis· PAWK, PAC, PAPU Register
Register
Name
POR
PAWK
Bit
7
6
5
4
3
2
1
0
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAWK0
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
²¾² Unimplemented, read as ²0²
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn: I/O type selection
0: output
1: input
PAPUn: Pull-high function enable
0: disable
1: enable
· PBPU Register
Register
Name
POR
PBC
PBPU
Bit
7
6
5
4
3
2
1
0
FFH
¾
¾
¾
¾
¾
¾
PBC1
PBC0
00H
¾
¾
¾
¾
¾
¾
PBPU1
PBPU0
²¾² Unimplemented, read as ²0²
PBCn: I/O type selection
0: output
1: input
PBPUn: Pull-high function enable
0: disable
1: enable
Rev.1.10
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February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
· PFD Output
I/O Port Control Registers
The PFD function output is pin-shared with an I/O pin.
The output function of this pin is chosen using the
CTRL0 register. Note that the corresponding bit of the
port control register, must setup the pin as an output
to enable the PFD output. If the port control register
has setup the pin as an input, then the pin will function
as a normal logic input with the usual pull-high selection, even if the PFD function has been selected.
Each Port has its own control register, known as PAC,
PBC, which controls the input/output configuration. With
this control register, each I/O pin with or without
pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be
written as a ²1². This will then allow the logic state of the
input pin to be directly read by instructions. When the
corresponding bit of the control register is written as a
²0², the I/O pin will be setup as a CMOS output. If the pin
is currently setup as an output, instructions can still be
used to read the output register. However, it should be
noted that the program will in fact only read the status of
the output data latch and not the actual logic status of
the output pin.
· PWM Outputs
The PWM function whose outputs are pin-shared with
I/O pins. The PWM output functions are chosen using
the CTRL0 register. Note that the corresponding bit of
the port control registers, for the output pin, must
setup the pin as an output to enable the PWM output.
If the pins are setup as inputs, then the pin will function
as a normal logic input with the usual pull-high selections, even if the PWM registers have enabled the
PWM function.
Pin-shared Functions
· A/D Inputs
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
Each device in this series has either four or eight inputs to the A/D converter. All of these analog inputs
are pin-shared with I/O pins on Port B. If these pins
are to be used as A/D inputs and not as I/O pins then
the corresponding PCRn bits in the A/D converter
control register, ADCR, must be properly setup. There
are no configuration options associated with the A/D
converter. If chosen as I/O pins, then full pull-high resistor configuration options remain, however if used
as A/D inputs then any pull-high resistor options associated with these pins will be automatically disconnected.
· External Interrupt Input
The external interrupt pin, INT, is pin-shared with an
I/O pin. To use the pin as an external interrupt input
the correct bits in the INTC0 register must be programmed. The pin must also be setup as an input by
setting the PAC3 bit in the Port Control Register. A
pull-high resistor can also be selected via the appropriate port pull-high resistor register. Note that even if
the pin is setup as an external interrupt input the I/O
function still remains.
· External Timer/Event Counter Input
The Timer/Event Counter pins, TC0 and TC1 are
pin-shared with I/O pins. For these shared pins to be
used as Timer/Event Counter inputs, the Timer/Event
Counter must be configured to be in the Event Counter or Pulse Width Capture Mode. This is achieved by
setting the appropriate bits in the Timer/Event Counter
Control Register. The pins must also be setup as inputs by setting the appropriate bit in the Port Control
Register. Pull-high resistor options can also be selected using the port pull-high resistor registers. Note
that even if the pin is setup as an external timer input
the I/O function still remains.
Rev.1.10
30
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
V
P u ll- H ig h
S e le c t
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
I/O
R e a d C o n tr o l R e g is te r
p in
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
R e a d D a ta R e g is te r
S y s te m
D D
U
X
P A o n ly
W a k e -u p
W a k e - u p S e le c t
Generic Input/Output Ports
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
C K
Q
S
C h ip R e s e t
P A 7 /R E S
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
X
W a k e -u p (P A 7 )
P A W K 7
R E S fo r P A 7 o n ly
PA7 NMOS Input/Output Port
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
I/O Pin Structures
retrieves the contents of the Timer/Event Counter. The
second type of associated register is the Timer Control
Register which defines the timer options and determines how the timer is to be used. The device can have
the timer clock configured to come from the internal
clock source. In addition, the timer clock source can also
be configured to come from an external timer pin.
The diagrams illustrate the I/O pin internal structures. As
the exact logical construction of the I/O pin may differ
from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O
pins.
Programming Considerations
Configuring the Timer/Event Counter Input Clock
Source
Within the user program, one of the first things to consider is port initialisation. After a reset, the I/O data register and I/O port control register will be set high. This
means that all I/O pins will default to an input state, the
level of which depends on the other connected circuitry
and whether pull-high options have been selected. If the
port control registers, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated port data
register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide
by loading the correct value into the port control register
or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
The Timer/Event Counter clock source can originate
from various sources, an internal clock or an external
pin. The internal clock source source is used when the
timer is in the timer mode or in the pulse width capture
mode. For some Timer/Event Counters, this internal
clock source is first divided by a prescaler, the division
ratio of which is conditioned by the Timer Control Register bits T0PSC0~T0PSC2. For Timer/Event Counter 0,
the internal clock source can be either fSYS or the LXT
Oscillator, the choice of which is determined by the T0S
bit in the TMR0C register.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on an external timer pin TCn. Depending upon the condition of the TnEG bit, each high to low, or low to high
transition on the external timer pin will increment the
counter by one.
T 4
Timer Registers - TMR0, TMR1
C lo c k
The timer registers are special function registers located
in the Special Purpose Data Memory and is the place
where the actual timer value is stored. These registers
are known as TMR0 and TMR1. The value in the timer
registers increases by one each time an internal clock
pulse is received or an external transition occurs on the
external timer pin. The timer will count from the initial
value loaded by the preload register to the full count of
FFH at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting.
P o rt D a ta
R e a d fro m
P o rt
W r ite to P o r t
Read Modify Write Timing
Pins PA0 to PA7 each have a wake-up functions, selected via the PAWK register. When the device is in the
Sleep Mode, various methods are available to wake the
device up. One of these is a high to low transition of any
of the these pins. Single or multiple pins on Port A can
be setup to have this function.
Timer/Event Counters
Note that to achieve a maximum full range count of FFH,
the preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the
Timer/Event Counter is in an OFF condition and data is
written to its preload register, this data will be immediately written into the actual counter. However, if the
counter is enabled and counting, any new data written
into the preload data register during this period will remain in the preload register and will only be written into
the actual counter the next time an overflow occurs.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The devices contain from one
to three count-up timer of 8-bit capacity. As the timers
have three different operating modes, they can be configured to operate as a general timer, an external event
counter or as a pulse width capture device. The provision of an internal prescaler to the clock circuitry on
gives added range to the timers.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register
Rev.1.10
32
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
P W M
P W M C 0
T 0 S
fS
Y S
fL
X T
C o n tro l
P W M
T im e - B a s e e v e n t in te r r u p t P e r io d
1
(2 10 ~ 2 13 ) *
fT P
T im e - B a s e C o n tr o l
0
M U X
1
fT
T 0 P S C
[2 :0 ]
P
7 S ta g e C o u n te r
7
T o T im e r 0 in te r n a l c lo c k
(fT 0 C K = fT P ~ fT P /1 2 8 )
8 -1 M U X
T im e r P r e s c a le r
Clock Structure for Timer/PWM/Time Base
D a ta B u s
T 0 M 1 , T 0 M 0
T im e r 0 In te r n a l C lo c k
(fT 0 C K )
P r e lo a d R e g is te r
M o d e C o n tro l
T 0 O V
O v e r flo w
to In te rru p t
U p C o u n te r
T C 0
T 0 O N
T 0 E G
¸
P F D 0
2
8-bit Timer/Event Counter 0 Structure
D a ta B u s
T 1 M 1 , T 1 M 0
fS Y S /4
L X T O s c illa to r
M
U
X
P r e lo a d R e g is te r
M o d e C o n tro l
T 1 O V
T 1 S
O v e r flo w
to In te rru p t
U p C o u n te r
T C 1
T 1 O N
T 1 E G
¸
2
P F D 1
8-bit Timer/Event Counter 1 Structure
P F D C S
P F D 0
0
P F D 1
1
M U X
P F D
o u tp u t
Note: If PWM0/PWM1 is enabled, then fTP comes from fSYS (ignore T0S)
Rev.1.10
33
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
· TMR0C Register
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
T0S
T0ON
T0EG
T0PSC2
T0PSC1
T0PSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
0
0
Bit 7,6
T0M1, T0M0: Timer0 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T0S: timer clock source
0: fSYS
1: LXT oscillator
T0S selects the clock source for fTP which is provided for Timer 0, the Time-Base and
the PWM. If the PWM is enabled, then fSYS will be selected, overriding the T0S selection.
Bit 4
T0ON: Timer/event counter counting enable
0: disable
1: enable
Bit 3
T0EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010: fTP/4
011: fTP/8
100: fTP/16
101: fTP/32
110: fTP/64
111: fTP/128
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
· TMR1C Register
Bit
7
6
5
4
3
2
1
0
Name
T1M1
T1M0
T1S
T1ON
T1EG
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
1
¾
¾
¾
Bit 7,6
T1M1, T1M0: Timer 1 Operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T1S: timer clock source
0: fSYS/4
1: LXT oscillator
T1ON: Timer/event counter counting enable
0: disable
1: enable
Bit 4
Bit 3
T1EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
unimplemented, read as ²0²
Rev.1.10
35
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Timer Control Registers - TMR0C, TMR1C
In this mode the internal clock is used as the timer clock.
The timer input clock source is either fSYS , fSYS/4 or the
LXT oscillator. However, this timer clock source is further divided by a prescaler, the value of which is determined by the bits TnPSC2~TnPSC0 in the Timer
Control Register. The timer-on bit, TnON must be set
high to enable the timer to run. Each time an internal
clock high to low transition occurs, the timer increments
by one; when the timer is full and overflows, an interrupt
signal is generated and the timer will reload the value already loaded into the preload register and continue
counting. A timer overflow condition and corresponding
internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring
that the ETnI bits of the INTCn register are reset to zero.
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
The Timer Control Register is known as TMRnC. It is the
Timer Control Register together with its corresponding
timer register that control the full operation of the
Timer/Event Counter. Before the timer can be used, it is
essential that the Timer Control Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during
program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the pulse width capture mode, bits 7 and 6 of the
Timer Control Register, which are known as the bit pair
TnM1/TnM0, must be set to the required logic levels.
The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, provides the basic on/off control of the respective timer. Setting the bit high allows the
counter to run, clearing the bit stops the counter. Bits
0~2 of the Timer Control Register determine the division
ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If
the timer is in the event count or pulse width capture
mode, the active transition edge level type is selected by
the logic level of bit 3 of the Timer Control Register
which is known as TnEG. The TnS bit selects the internal clock source if used.
Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer TCn pin, can be
recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TnM1/TnM0,
in the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Bit7 Bit6
1
0
1
In this mode, the external timer TCn pin, is used as the
Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If
the Active Edge Select bit, TnEG, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter
will increment each time the external timer pin receives
a low to high transition. If the TnEG is high, the counter
will increment each time the external timer pin receives
a high to low transition. When it is full and overflows, an
interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload
register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Inter-
Timer Mode
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7 Bit6
0
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart (TnEG=1)
Rev.1.10
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February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Timer/Event Counter will stop counting. If the Active
Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when
the external timer pin returns to its original low level. As
before, the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. It is important to note that in the pulse width capture Mode, the
enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its
original level, whereas in the other two modes the enable bit can only be reset to zero under program control.
rupt Enable bit in the corresponding Interrupt Control
Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
t h e microcontroller i s i n t h e S l eep M o d e , t h e
Timer/Event Counter will continue to record externally
changing logic events on the timer input TCn pin. As a
result when the timer overflows it will generate a timer
interrupt and corresponding wake-up source.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the TCn pin. As the
enable bit has now been reset, any further transitions on
the external timer pin will be ignored. The timer cannot
begin further pulse width capture until the enable bit is
set high again by the program. In this way, single shot
pulse measurements can be easily made.
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair, TnM1/TnM0, in the Timer Control
Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Pulse Width
Capture Mode
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external
timer pin and not by the logic level. When the Timer/Event
Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that
the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
Bit7 Bit6
1
1
In this mode the internal clock, fSYS , fSYS/4 or the LXT, is
used as the internal clock for the 8-bit Timer/Event
Counter. However, the clock source, fSYS, for the 8-bit
timer is further divided by a prescaler, the value of which
is determined by the Prescaler Rate Select bits
TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control
Register have been setup, the enable bit TnON, which is
bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the
external timer pin.
As the TCn pin is shared with an I/O pin, to ensure that
the pin is configured to operate as a pulse width capture
pin, two things have to happen. The first is to ensure that
the Operating Mode Select bits in the Timer Control
Register place the Timer/Event Counter in the pulse
width capture Mode, the second is to ensure that the
port control register configures the pin as an input.
Prescaler
If the Active Edge Select bit TnEG, which is bit 3 of the
Timer Control Register, is low, once a high to low transition has been received on the external timer pin, the
Timer/Event Counter will start counting until the external
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Bits TnPSC0~TnPSC2 of the TMRnC register can be
used to define a division ratio for the internal clock
source of the Timer/Event Counter enabling longer time
out periods to be setup.
E x te rn a l T C n
P in In p u t
T n O N
- w ith T n E G = 0
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Capture Mode Timing Chart (TnEG=0)
Rev.1.10
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February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
T im e r O v e r flo w
P F D
C lo c k
P A 1 D a ta
P F D
O u tp u t a t P A 1
PFD Function
PFD Function
Programming Considerations
The Programmable Frequency Divider provides a
means of producing a variable frequency output suitable
for applications, such as piezo-buzzer driving or other
interfaces requiring a precise frequency generator.
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an internal
interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width capture
mode, the internal system clock is also used as the timer
clock source but the timer will only run when the correct
logic condition appears on the external timer input pin. As
this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a
result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is
configured to be in the event counting mode, which again
is an external event and not synchronised with the internal system or timer clock.
The Timer/Event Counter overflow signal is the clock
source for the PFD function, which is controlled by
PFDCS bit in CTRL0. For applicable devices the clock
source can come from either Timer/Event Counter 0 or
Timer/Event Counter 1. The output frequency is controlled by loading the required values into the timer
prescaler and timer registers to give the required division
ratio. The counter will begin to count-up from this preload
register value until full, at which point an overflow signal is
generated, causing both the PFD outputs to change
state. The counter will then be automatically reloaded
with the preload register value and continue counting-up.
If the CTRL0 register has selected the PFD function,
then for PFD output to operate, it is essential for the Port
A control register PAC, to setup the PFD pins as outputs.
PA1 must be set high to activate the PFD. The output
data bits can be used as the on/off control bit for the PFD
outputs. Note that the PFD outputs will all be low if the
output data bit is cleared to zero.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must
be properly set otherwise the internal interrupt associated
with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also
important to ensure that an initial value is first loaded into
the timer registers before the timer is switched on; this is
because after power-on the initial values of the timer registers are unknown. After the timer has been initialised
the timer can be turned on and off by controlling the enable bit in the timer control register.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very precise values of frequency can be generated.
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width capture mode, requires the
use of an external timer pin for its operation. As this pin is
a shared pin it must be configured correctly to ensure that
it is setup for use as a Timer/Event Counter input pin. This
is achieved by ensuring that the mode select bits in the
Timer/Event Counter control register, select either the
event counter or pulse width capture mode. Additionally
the corresponding Port Control Register bit must be set
high to ensure that the pin is setup as an input. Any
pull-high resistor connected to this pin will remain valid
even if the pin is used as a Timer/Event Counter input.
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the Timer/Event Counter interrupt
is enabled this will in turn generate an interrupt signal.
However irrespective of whether the interrupts are enabled or not, a Timer/Event Counter overflow will also
generate a wake-up signal if the device is in a
Power-down condition. This situation may occur if the
Timer/Event Counter is in the Event Counting Mode and
if the external signal continues to change state. In such
a case, the Timer/Event Counter will continue to count
these external events and if an overflow occurs the device will be woken up from its Power-down condition. To
prevent such a wake-up from occurring, the timer inter-
rupt request flag should first be set high before issuing
the ²HALT² instruction to enter the Sleep Mode.
Timer Program Example
The program shows how the Timer/Event Counter registers are setup along with how the interrupts are enabled
and managed. Note how the Timer/Event Counter is
turned on, by setting bit 4 of the Timer Control Register.
The Timer/Event Counter can be turned off in a similar
way by clearing the same bit. This example program sets
the Timer/Event Counters to be in the timer mode, which
uses the internal system clock as their clock source.
· PFD Programming Example
org
04h
; external interrupt vector
org
08h
; Timer Counter 0 interrupt vector
Jmp
tmr0int
; jump here when Timer 0 overflows
:
:
org
20h
; main program
:
:
;internal Timer 0 interrupt routine
tmr0int:
:
; Timer 0 main program placed here
:
:
begin:
;setup Timer 0 registers
mov
a,09bh
; setup Timer 0 preload value
mov
tmr0,a
mov
a,081h
; setup Timer 0 control register
mov
tmr0c,a
; timer mode and prescaler set to /2
;setup interrupt register
mov
a,00dh
; enable master interrupt and both timer interrupts
mov
intc0,a
:
:
set tmr0c.4
; start Timer 0
:
:
Time Base
The device includes a Time Base function which is used to generate a regular time interval signal.
The Time Base time interval magnitude is determined using an internal 13 stage counter sets the division ratio of the
clock source. This division ratio is controlled by both the TBSEL0 and TBSEL1 bits in the CTRL1 register. The clock
source is selected using the T0S bit in the TMR0C register.
When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as the Time Base
clock source is the same as the Timer/Event Counter clock source, care should be taken when programming.
Rev.1.10
39
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Pulse Width Modulator
bit2~bit7 is denoted here as the DC value. The second
group which consists of bit0~bit1 is known as the AC
value. In the 6+2 PWM mode, the duty cycle value of
each of the four modulation sub-cycles is shown in the
following table.
The device contains an 8-bit PWM function. Useful for
such applications such as motor speed control, the
PWM function provides outputs with a fixed frequency
but with a duty cycle that can be varied by setting particular values into the corresponding PWM register.
PWM Operation
A single register, known as PWMn and located in the
Data Memory is assigned to each Pulse Width Modulator channel. It is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of
the output waveform, should be placed. To increase the
PWM modulation frequency, each modulation cycle is
subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. The required mode and the on/off control for each
PWM channel is selected using the CTRL0 register.
Note that when using the PWM, it is only necessary to
write the required value into the PWMn register and select the required mode setup and on/off control using the
CTRL0 register, the subdivision of the waveform into its
sub-modulation cycles is implemented automatically
within the microcontroller hardware. The PWM clock
source is the system clock fSYS. This method of dividing
the original modulation cycle into a further 2 or 4
sub-cycles enable the generation of higher PWM frequencies which allow a wider range of applications to be
served. The difference between what is known as the
PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However,
when in the 7+1 mode of operation the PWM modulation
frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
PWM
Modulation
fSYS/64 for (6+2) bits mode
fSYS/128for (7+1) bits mode
DC
(Duty Cycle)
Modulation cycle i
(i=0~3)
i<AC
DC+1
64
i³AC
DC
64
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into
4 individual modulation cycles, numbered from 0~3 and
how the AC value is related to the PWM value.
7+1 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM
register, has 256 clock periods. However, in the 7+1
PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. Each one of these
two sub-cycles contains 128 clock cycles. In this mode, a
modulation frequency increase of two is achieved. The
8-bit PWM register value, which represents the overall
duty cycle of the PWM waveform, is divided into two
groups. The first group which consists of bit1~bit7 is denoted here as the DC value. The second group which
consists of bit0 is known as the AC value. In the 7+1
PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table.
[PWM]/256
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM
register, has 256 clock periods. However, in the 6+2
PWM mode, each PWM cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. Each one of
these four sub-cycles contains 64 clock cycles. In this
mode, a modulation frequency increase of four is
achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of
Rev.1.10
AC (0~3)
6+2 Mode Modulation Cycle Values
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
Parameter
Parameter
AC (0~1)
DC
(Duty Cycle)
Modulation cycle i
(i=0~1)
i<AC
DC+1
128
i³AC
DC
128
7+1 Mode Modulation Cycle Values
The following diagram illustrates the waveforms associated with the 7+1 mode PWM operation. It is important
to note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how
the AC value is related to the PWM value.
40
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
fS
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
6+2 PWM Mode
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(6 + 2 ) M o d e
PWM Register for 6+2 Mode
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
7+1 PWM Mode
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(7 + 1 ) M o d e
PWM Register for 7+1 Mode
Rev.1.10
41
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
PWM Output Control
the PWM data to appear on the pin. Writing a zero value
will disable the PWM output function and force the output low. In this way, the Port data output registers can be
used as an on/off control for the PWM function. Note
that if the CTRL0 register have selected the PWM function, but a high value has been written to its corresponding bit in the PAC control register to configure the pin as
an input, then the pin can still function as a normal input
line, with pull-high resistor options.
The PWM outputs are pin-shared with the I/O pins PA4.
To operate as a PWM output and not as an I/O pin, the
correct bits must be set in the CTRL0 register. A zero
value must also be written to the corresponding bit in the
I/O port control register PAC.4 to ensure that the corresponding PWM output pin is setup as an output. After
these two initial steps have been carried out, and of
course after the required PWM value has been written
into the PWMn register, writing a high value to the corresponding bit in the output data register PA.4 will enable
· PWM Programming Example
The following sample program shows how the PWM0 output is setup and controlled.
mov
mov
set
set
clr
set
::
clr
a,64h
pwm0,a
ctrl0.5
ctrl0.3
pac.4
pa.4
; setup PWM value of decimal 100
pa.4
; disable the PWM output_ pin
; PA4 forced low
Rev.1.10
;
;
;
;
select the 7+1 PWM mode
select pin PA4 to have a PWM function
setup pin PA4 as an output
enable the PWM output
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HT48R01B/02B/01N/02N
Analog to Digital Converter
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
In the following table, D0~D11 is the A/D conversion
data result bits.
A/D Overview
A/D Converter Control Registers - ADCR, ACSR
The device contains an 4-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals
and convert these signals directly into either a 12-bit digital value.
To control the function and operation of the A/D converter, two control registers known as ADCR and ACSR
are provided. These 8-bit registers define functions
such as the on/off function, selection of which analog
channel is connected to the internal A/D converter,
which pins are used as analog inputs and which are
used as normal I/Os, the A/D clock source as well as
controlling the start function and monitoring the A/D converter end of conversion status.
A/D Converter Data Registers - ADRL, ADRH
fS
A D O N B B it
A /D E n a b le
P A 0
P A 1
P A 2
P A 3
/A N
/A N
/A N
/A N
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11 D10 D9
D8
D7
D6
D5
D4
The ACS1~ACS0 bits in the ADCR register define the
channel number. As the device contains only one actual
analog to digital converter circuit, each of the individual
4 analog inputs must be routed to the converter. It is the
function of the ACS1~ACS0 bits in the ADCR register to
determine which analog channel is actually connected
to the internal A/D converter.
The device, which has an internal 12-bit A/D converter,
requires two data registers, a high byte register, known
as ADRH, and a low byte register, known as ADRL. After
the conversion process takes place, these registers can
be directly read by the microcontroller to obtain the digitised conversion value. Only the high byte register,
ADRH, utilises its full 8-bit contents. The low byte register utilises only 4 bit of its 8-bit contents as it contains
only the lowest bits of the 12-bit converted value.
R e g is te r
Bit
7
A/D Data Registers
The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers.
A C S R
Register
Y S
C lo c k
D iv id e r
¸ N
V
D D
A D O N
B it
0
1
A D R L
A D C
2
A D R H
3
P C R 0 ~ P C R 3
P in C o n fig u r a tio n
B its
A D C S 0 ~ A D C S 2
C h a n n e l S e le c t
B its
S T A R T
E O C B
A /D D a ta
R e g is te r s
A D C R
R e g is te r
S ta r t B it E n d o f
C o n v e r s io n B it
A/D Converter Structure
Rev.1.10
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HT48R01B/02B/01N/02N
· ADRH, ADRL Register
ADRH
ADRL
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Name
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
¾
¾
¾
¾
R/W
R
R
R
R
R
R
R
R
R
R
R
R
¾
¾
¾
¾
POR
x
x
x
x
x
x
x
x
x
x
x
x
¾
¾
¾
¾
²x² unknown
unimplemented, read as ²0²
D11~D0: ADC conversion data
· ADCR Register
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
PCR3
PCR2
PCR1
PCR0
ACS1
ACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
0
0
0
0
0
Bit 7
START: Start the A/D conversion
0®1®0 : start
0®1
: reset the A/D converter and set EOCB to ²1²
Bit 6
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
Bit 5~2
PCR3, PCR2, PCR1, PCR0: A/D channel configuration
0: I/O
1: analog input n (n=0~3)
If PCR0~PCR3 are all zero, the ADC circuit is power off to reduce power consumption
Bit 1~0
ACS1 ~ ACS0: Select A/D channel
00: AN0
01: AN1
10: AN2
11: AN3
Rev.1.10
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HT48R01B/02B/01N/02N
· ACSR Register
Bit
7
6
5
4
3
2
1
0
Name
TEST
ADONB
¾
¾
¾
ADCS2
ADCS1
ADCS0
R/W
R/W
R/W
¾
¾
¾
R/W
R/W
R/W
POR
1
0
¾
¾
¾
0
0
0
Bit 7
TEST: for test mode use only
Bit 6
ADONB: ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
Note: 1. it is recommended to set ADONB=1 before entering sleep for saving power.
2. ADONB=1 will power down the ADC module.
Bit 5~3
unimplemented, read as ²0²
Bit 2~0
ADCS2~ADCS0 : Select A/D converter clock source
000: system clock/2
001: system clock/8
010: system clock/32
011: undefined, can¢t be used.
100: system clock
101: system clock/4
110: system clock/16
111: undefined, can¢t be used.
The ADCR control register also contains the
PCR3~PCR0 bits which determine which pins on
PA0~PA3 are used as analog inputs for the A/D converter
and which pins are to be used as normal I/O pins. Note
that if the PCR3~PCR0 bits are all set to zero, then all the
PA0~PA3 pins will be setup as normal I/Os.
The A/D converter overall on/off control is a function of
both the ADONB bit in the ACSR register and the PCRn
bits in the ADCR register as shown in the table. Either
the ADONB bit cleared to zero or the PCRn bits set to a
zero value will switch off the A/D converter. These are
important consideration in power sensitive applications
and must be taken into account if power consumption is
to be minimised. As the table illustrates, execution of the
HALT instruction has no effect on the A/D converter
on/off control and subsequently its power consumption.
The START bit in the register is used to start and reset
the A/D converter. When themicrocontroller sets this bit
from low to high and then low again, an analog to digital
conversion cycle will be initiated. When the START bit is
brought from low to high but not low again, the EOCB bit
in the ADCR register will be set to a ²1² and the analog
to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal
analog to digital converter.
PCRn
Bits
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is complete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.
ADONB
Bit
ADC
On/Off
=0
X
X
Off
>0
X
0
On
>0
X
1
Off
Note: X: Don¢t care
A/D Converter On/Off Control
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2, ADCS1 and ADCS0,
there are some limitations on the maximum A/D clock
source speed that can be selected. As the minimum value
of permissible A/D clock period, tAD, is 0.5ms, care must be
taken for system clock speeds equal to or greater than
4MHz. For example, the system clock operates at a frequency of 4MHz, the ADCS2, ADCS1 and ADCS0 bits
should not be set to ²100². Doing so will give A/D clock periods that are less than the minimum A/D clock period
which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values
marked with an asterisk * show where, depending upon
the device, special care must be taken, as the values may
be less than the specified minimum A/D Clock Period.
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the ADCS2,
ADCS1 and ADCS0 bits in the ACSR register.
Rev.1.10
HALT
Instruction
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HT48R01B/02B/01N/02N
A/D Clock Period (tAD)
ADCS2,
ADCS1,
ADCS0=000
(fSYS/2)
ADCS2,
ADCS1,
ADCS0=001
(fSYS/8)
ADCS2,
ADCS1,
ADCS0=010
(fSYS/32)
1MHz
2ms
8ms
2MHz
1ms
4ms
4MHz
500ns
8MHz
250ns*
12MHz
167ns*
fSYS
ADCS2,
ADCS1,
ADCS0=100
(fSYS)
ADCS2,
ADCS1,
ADCS0=101
(fSYS/4)
32ms
1ms
4ms
16ms
Undefined
16ms
500ns
2ms
8ms
Undefined
2ms
8ms
250ns*
1ms
4ms
Undefined
1ms
4ms
125ns*
500ns
2ms
Undefined
667ns
2.67ms
83ns*
333ns*
1ms
Undefined
ADCS2,
ADCS2,
ADCS1,
ADCS1,
ADCS0=110 ADCS0=011,
(fSYS/16)
111
A/D Clock Period Examples
A/D Input Pins
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D
converter interrupt function is active. The master interrupt control bit, EMI, in the INTC0 interrupt control register must be set to ²1², and the A/D converter interrupt
bit, ADE, in the INTC1 register must also be set to ²1².
All of the A/D analog input pins are pin-shared with the
I/O pins on Port A. Bits PCR3~PCR0 in the register, determine whether the input pins are setup as normal Port
A input/output pins or whether they are setup as analog
inputs. In this way, pins can be changed under program
control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors,
which are setup through register programming, apply to
the input pins only when they are used as normal I/O
pins, if setup as A/D inputs the pull-high resistors will be
automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PAC port
control register to enable the A/D input as when the
PCR3~PCR0 bits enable an A/D input, the status of the
port control register will be overridden.
· Step 6
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR register from ²0² to ²1² and then to ²0² again. Note that this
bit should have been originally set to ²0².
· Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register
can be polled. The conversion process is complete
when this bit goes low. When this occurs the A/D data
registers ADRL and ADRH can be read to obtain the
conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur.
Note: When checking for the end of the conversion
process, if the method of polling the EOCB bit in
the ADCR register is used, the interrupt enable
step above can be omitted.
Summary of A/D Conversion Steps
The following summarises the individual steps that
should be executed in order to implement an A/D conversion process.
· Step 1
Select the required A/D conversion clock by correctly
programming bits ADCS2, ADCS1 and ADCS0 in the
register.
The accompanying diagram shows graphically the various stages involved in an analog to digital conversion
process and its associated timing.
· Step 2
Enable the A/D by clearing the ADONB bit in the
ACSR register to zero.
The setting up and operation of the A/D converter function is fully under the control of the application program as
there are no configuration options associated with the
A/D converter. After an A/D conversion process has been
initiated by the application program, the microcontroller
internal hardware will begin to carry out the conversion,
during which time the program can continue with other
functions. The time taken for the A/D conversion is 16tAD
where tAD is equal to the A/D clock period.
· Step 3
Select which channel is to be connected to the internal
A/D converter by correctly programming the
ACS1~ACS0 bits which are also contained in the register.
· Step 4
Select which pins are to be used as A/D inputs and
configure them as A/D input pins by correctly programming the PCR3~PCR0 bits in the ADCR register.
Note that this step can be combined with Step 3. into a
single ADCR register programming operation.
· Step 5
Rev.1.10
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HT48R01B/02B/01N/02N
Programming Considerations
between the analog input value and the digitised output
value for the A/D converter.
When programming, special attention must be given to
the PCR[3:0] bits in the register. If these bits are all
cleared to zero no external pins will be selected for use
as A/D input pins allowing the pins to be used as normal
I/O pins. When this happens the internal A/D circuitry
will be power down. Setting the ADONB bit high has the
ability to power down the internal A/D circuitry, which
may be an important consideration in power sensitive
applications.
Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the
digitised zero value, the subsequent digitised values will
change at a point 0.5 LSB below where they would
change without the offset, and the last full scale digitised
value will change at a point 1.5 LSB below the VDD level.
A/D Programming Example
The following two programming examples illustrate how
to setup and implement an A/D conversion. In the first
example, the method of polling the EOCB bit in the
ADCR register is used to detect when the conversion
cycle is complete, whereas in the second example, the
A/D interrupt is used to determine when the conversion
is complete.
A/D Transfer Function
As the device contain a 12-bit A/D converter, its
full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the
VDD voltage, this gives a single bit analog input value of
VDD/4096. The diagram show the ideal transfer function
P C R 3 ~
P C R 0
0 0 0 B
x x x B - P C R [3 :0 ] is n o t e q u a l to " 0 "
A D O N B
tO
A D C m o d u le
O N
N 2 S T
o n
A /D
tA
s a m p lin g tim e
A /D
tA
D C S
o ff
s a m p lin g tim e
o n
D C S
S T A R T
E O C B
A C S 1 ~
A C S 0
x x B
P o w e r-o n
R e s e t
1 0 B
0 0 B
0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
1 : D e fin e p o r t c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D c lo c k m u s t b e fs y s , fS
tA D C S = 4 tA D
tA D C = 1 6 tA D
Y S
E n d o f A /D
c o n v e r s io n
tA D C
c o n v e r s io n tim e
/2 , fS
Y S
/4 , fS
Y S
/8 , fS
A /D
/1 6 o r fS
Y S
Y S
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
1 .5 L S B
F F F H
F F E H
F F D H
A /D C o n v e r s io n
R e s u lt
0 .5 L S B
0 3 H
0 2 H
0 1 H
0
1
2
3
4 0 9 3 4 0 9 4
4 0 9 5 4 0 9 6
(
V D D
)
4 0 9 6
A n a lo g In p u t V o lta g e
Ideal A/D Transfer Function
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Example: using an EOCB polling method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
; select fSYS/8 as A/D clock and ADONB=0
mov a,00000100B
; setup ADCR register to configure Port as A/D inputs
mov ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end
; of A/D conversion
jmp polling_EOC
; continue polling
mov a,ADRL
; read low byte conversion result value
mov adrl_buffer,a
; save result to user defined register
mov a,ADRH
; read high byte conversion result value
mov adrh_buffer,a
; save result to user defined register
:
jmp start_conversion
; start next A/D conversion
Note: To power off ADC module, it is necessary to set ADONB as ²1².
Example: using the interrupt method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
; select fSYS/8 as A/D clock and ADONB=0
mov a,00000100B
; setup ADCR register to configure Port as A/D inputs
mov ADCR,a
; and select AN0 to be connected to the A/D
:
:
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
clr ADF
; clear ADC interrupt request flag
set ADE
; enable ADC interrupt
set EMI
; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_:
mov acc_stack,a
; save ACC to user defined memory
mov a,STATUS
mov status_stack,a
; save STATUS to user defined memory
:
:
mov a,ADRL
; read low byte conversion result value
mov adrl_buffer,a
; save result to user defined register
mov a,ADRH
; read high byte conversion result value
mov adrh_buffer,a
; save result to user defined register
:
:
EXIT_ISR:
mov a,status_stack
mov STATUS,a
; restore STATUS from user defined memory
mov a,acc_stack
; restore ACC from user defined memory
clr ADF
; clear ADC interrupt flag
reti
Note: To power off ADC module, it is necessary to set ADONB as ²1².
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter or Time Base requires
microcontroller attention, their corresponding interrupt
will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to
their respective needs.
Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction
from this interrupt vector. The instruction at this vector
will usually be a JMP statement which will jump to another section of program which is known as the interrupt
service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must
be terminated with a RETI instruction, which retrieves
the original Program Counter address from the stack
and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
The devices contain a single external interrupt and multiple internal interrupts. The external interrupt is controlled by the action of the external interrupt pin, while
the internal interrupt is controlled by the Timer/Event
Counters and Time Base overflows.
The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by using two registers, INTC0 and INTC1. By controlling the appropriate
enable bits in this registers each individual interrupt can
be enabled or disabled. Also when an interrupt occurs,
the corresponding request flag will be set by the
microcontroller. The global enable flag if cleared to zero
will disable all interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A Timer/Event Counter overflow, a Time Base event or
an active edge on the external interrupt pin will all generate an interrupt request by setting their corresponding
request flag, if their appropriate interrupt enable bit is
set. When this happens, the Program Counter, which
stores the address of the next instruction to be executed, will be transferred onto the stack. The Program
A u to m a tic a lly D is a b le d w h e n in te r r u p t
e v e n t is s e r v ic e d E n a b le d m a n u a lly o r
a u to m a tic a lly w ith R E T I in s tr u c tio n
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
E x te rn a l In te rru p t
R e q u e s t F la g IN T F
IN T E
E M I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
T 0 E
E M I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
T 1 E
E M I
A /D C o n v e r s io n
In te r r u p t R e q u e s t F la g A D F
A D E
E M I
T im e B a s e
In te r r u p t R e q u e s t F la g T B F
T B E
E M I
P r io r ity
H ig h
In te rru p t
P o llin g
L o w
Note: HT48R01B/HT48R02B/HT48R01N/HT48R02N haven¢t ADC interrupt
Interrupt Scheme
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
When an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the interrupt
vector. If the device is in the Sleep Mode and is woken
up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
Main
Program
External Interrupt
Interrupt Request or
Interrupt Flag Set by Instruction
N
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, INTE,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, INTF, is
set, a situation that will occur when an edge transition
appears on the external INT line. The type of transition
that will trigger an external interrupt, whether high to low,
low to high or both is determined by the INTEG0 and
INTEG1 bits, which are bits 6 and 7 respectively, in the
CTRL1 control register. These two bits can also disable
the external interrupt function.
Enable Bit Set ?
Y
Main
Program
Automatically Disable Interrupt
Clear EMI & Request Flag
Wait for 2 ~ 3 Instruction Cycles
ISR Entry
RETI
(it will set EMI automatically)
Interrupt Flow
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
· HT46R01B/HT46R02B/HT46R01N/HT46R02N
Priority Vector
External Interrupt
1
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
A/D Conversion Complete
4
10H
Time Base Overflow
5
14H
INTEG0
0
0
External interrupt disable
Edge Trigger Type
0
1
Rising edge Trigger
1
0
Falling edge Trigger
1
1
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin
PA3 and can only be configured as an external interrupt
pin if the corresponding external interrupt enable bit in
the INTC0 register has been set and the edge trigger
type has been selected using the CTRL1 register. The
pin must also be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and a transition
appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 04H, will take
place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts. Note that any pull-high resistor connections
on this pin will remain valid even if the pin is used as an
external interrupt input.
Interrupt Priority
Interrupt Source
INTEG1
04H
· HT48R01B/HT48R02B/HT48R01N/HT48R02N
Interrupt Source
Priority Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
Time Base Overflow
4
14H
Rev.1.10
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HT48R01B/02B/01N/02N
· INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
T1F
T0F
INTF
T1E
T0E
INTE
EMI
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
Bit 7
unimplemented, read as ²0²
Bit 6
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
Bit 5
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
Bit 4
INTF: External interrupt request flag
0: inactive
1: active
Bit 3
T1E: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
Bit 2
T0E: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
Bit 1
INTE: external interrupt enable
0: disable
1: enable
Bit 0
EMI: Master interrupt global enable
0: disable
1: enable
· INTC1 Register
¨
HT46R01B/HT46R02B/HT46R01N/HT46R02N
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TBF
ADF
¾
¾
TBE
ADE
R/W
¾
¾
R/W
R/W
¾
¾
R/W
R/W
POR
¾
¾
0
0
¾
¾
0
0
Bit 7~6
unimplemented, read as ²0²
Bit 5
TBF: Time Base event interrupt request flag
0: inactive
1: active
Bit 4
ADF: A/D Conversion interrupt request flag
0: inactive
1: active
Bit 3~2
unimplemented, read as ²0²
Bit 1
TBE: Time base event interrupt enable
0: disable
1: enable
Bit 0
ADE: A/D Conversion interrupt enable
0: disable
1: enable
Rev.1.10
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
¨
HT48R01B/HT48R02B/HT48R01N/HT48R02N
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TBF
¾
¾
¾
TBE
¾
R/W
¾
¾
R/W
¾
¾
¾
R/W
¾
POR
¾
¾
0
¾
¾
¾
0
¾
Bit 7~6
unimplemented, read as ²0²
Bit 5
TBF: Time Base event interrupt request flag
0: inactive
1: active
Bit 4~2
unimplemented, read as ²0²
Bit 1
TBE: Time base event interrupt enable
0: disable
1: enable
Bit 0
unimplemented, read as ²0²
Timer/Event Counter Interrupt
Programming Considerations
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, TnE, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter request flag, TnF, is set, a situation
that will occur when the relevant Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a
subroutine call to the relevant timer interrupt vector, will
take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts.
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt register until the corresponding
interrupt is serviced or until the request flag is cleared by
a software instruction.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
Time Base Interrupt
All of these interrupts have the capability of waking up
the processor when in the Sleep Mode.
For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit
TBE, must first be set. An actual Time Base interrupt will
take place when the time base request flag TBF is set, a
situation that will occur when the Time Base overflows.
When the interrupt is enabled, the stack is not full and a
time base overflow occurs a subroutine call to time base
vector will take place. When the interrupt is serviced, the
time base interrupt flag. TBF will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
Rev.1.10
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
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HT48R01B/02B/01N/02N
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the OTP Program Memory device during the programming process. During the development process, these options are selected using the HT-IDE
software development tools. As these options are programmed into the device using the hardware programming tools,
once they are selected they cannot be changed later by the application software. All options must be defined for proper
system function, the details of which are shown in the table.
No.
Options
1
Watchdog Timer: enable or disable
2
Watchdog Timer clock source: LXT, LIRC or fSYS/4
Note: LXT oscillator must be selected by OSC configuration option if WDT clock source is from LXT.
3
CLRWDT instructions: 1 or 2 instructions
4
System oscillator configuration: HXT, HIRC, ERC, HIRC + LXT
5
LVR function: enable or disable
6
LVR voltage: 2.1V, 3.15V or 4.2V
7
RES or PA7 pin function
8
SST: 1024 or 2 clocks (determine tSST for HIRC/ERC)
9
Internal RC: 4MHz, 8MHz or 12MHz
Application Circuits
V
D D
0 .0 1 m F
0 .1 m F
V D D
R e s e t
C ir c u it
1 0 k W ~
1 0 0 k W
1 N 4 1 4 8
0 .1 ~ 1 m F
R E S /P A 7
3 0 0 W
V S S
P A 0
P A 1 /P F D
P A 2 /T C 0
P A 3 /IN T
P A 4 /T C 1 /P
/A N
/A N
/A N
/A N
W M
0
1
3
2
0
P B 0
P B 1
O S C 1
O S C
C ir c u it
O S C 2
S e e O s c illa to r
S e c tio n
Rev.1.10
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HT48R01B/02B/01N/02N
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev.1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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HT48R01B/02B/01N/02N
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev.1.10
60
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev.1.10
61
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev.1.10
62
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev.1.10
63
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev.1.10
64
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev.1.10
65
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev.1.10
66
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Package Information
10-pin MSOP Outline Dimensions
6
1 0
E 1
1
5
E
D
L
A 2
A
e
R
0 .1 0
B
C
q
A 1
L 1
(4 C O R N E R S )
Symbol
Nom.
Max.
A
¾
¾
0.043
A1
0.000
¾
0.006
A2
0.030
0.033
0.037
B
0.007
¾
0.011
C
¾
¾
0.010
D
¾
0.118
¾
E
¾
0.193
¾
E1
¾
0.118
¾
e
¾
0.020
¾
L
0.016
0.024
0.031
L1
¾
0.037
¾
q
0°
¾
8°
Symbol
Rev.1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
¾
¾
1.10
A1
0.00
¾
0.15
A2
0.75
0.85
0.95
B
0.17
¾
0.27
C
¾
¾
0.25
D
¾
3.00
¾
E
¾
4.90
¾
E1
¾
3.00
¾
e
¾
0.50
¾
L
0.40
0.60
0.80
L1
¾
0.95
¾
q
0°
¾
8°
67
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
16-pin NSOP (150mil) Outline Dimensions
1 6
A
9
B
8
1
C
C '
G
H
D
E
a
F
· MS-012
Symbol
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.012
¾
0.020
C¢
0.386
¾
0.394
D
¾
¾
0.069
E
¾
0.050
¾
F
0.004
¾
0.010
G
0.016
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
A
Rev.1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.30
¾
0.51
C¢
9.80
¾
10.01
D
¾
¾
1.75
E
¾
1.27
¾
F
0.10
¾
0.25
G
0.41
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
68
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev.1.10
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
69
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
B 0
C
D 1
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev.1.10
70
February 12, 2010
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
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Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev.1.10
71
February 12, 2010
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