ATS682 Datasheet

ATS682LSH
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
Features and Benefits
Description
▪ True zero-speed operation
▪ Automatic Gain Control (AGC) for air gap independent
switchpoints
▪ Automatic Offset Adjustment (AOA) for signal processing
optimization
▪ Running-mode calibration for continuous optimization
▪ Precise duty cycle over operating temperature range
▪ Internal current regulator for two-wire operation
▪ Undervoltage lockout
▪ On-chip voltage regulator with wide operating voltage
range and stability in the presence of a variety of complex
load impedances
▪ Single chip IC for high reliability
The ATS682LSH is a Hall-effect integrated circuit and rare
earth pellet combination that provides a user-friendly solution
for true zero-speed digital gear-tooth sensing in two-wire
applications. This small package, with an optimized two-wire
leadframe, can be easily assembled and used in conjunction
with a wide variety of gear shapes and sizes.
Package: 4-pin SIP (suffix SH)
Signal optimization occurs at power-up through the adjustment
of offset and gain and is and is maintained throughout operation
with the use of a running-mode calibration scheme. Runningmode calibration provides immunity from environmental effects
such as micro-oscillations of the sensed target or sudden air
gap changes.
The integrated circuit incorporates a dual-element Hall-effect
circuit and signal processing that switches in response to
differential magnetic signals created by ferrous gear teeth.
The circuitry contains a sophisticated digital circuit that
reduces magnet and system offsets, calibrates the gain for air
gap independent switchpoints and provides true zero-speed
operation.
The regulated current output is configured for two-wire interface
circuitry and is ideally suited for obtaining speed information in
wheel speed applications. The Hall element spacing is optimized
for high resolution, small diameter targets. The package is lead
(Pb) free, with 100% matte tin lead frame plating.
Not to scale
Functional Block Diagram
Hall
Amplifier
Automatic Offset
Control
VCC
Gain
AOA DAC
AGC DAC
Internal Regulator
Gain Control
Tracking
DAC
Peak Hold
GND
Test Signals
ATS682-DS, Rev. 2
Test
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Selection Guide
Part Number
Packing*
ATS682LSHTN-T
800 pieces per 13-in. reel
*Contact Allegro™ for additional packing options
Absolute Maximum Ratings
Characteristic
Symbol
Supply Voltage
VCC
Reverse Supply Voltage
VRCC
Notes
Refer to Power Derating curve
Rating
Unit
28
V
–18
V
Operating Ambient Temperature
TA
–40 to 150
ºC
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Storage Temperature
Pin-out Diagram
1 2 3 4
Range L
Terminal List
Number
Name
Function
1
VCC
2
NC
3
TEST
Test (float or tie to ground)
4
GND
Ground terminal
Connects power supply to chip
No connection
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
OPERATING CHARACTERISTICS Valid at VCC and TA within specification; unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.1
Max.
Unit2
Electrical Characteristics
Supply Voltage3
Undervoltage Lockout
VCC
VCCUV
Operating, TJ < TJ(max)
4.0
–
24
V
VCC = 0 → 5 V or 5 → 0 V
–
–
3.95
V
Supply Zener Clamp Voltage
VZ
ICC = ICC(max) + 3 mA, TA = 25°C
28
–
–
V
Supply Zener Current
IZ
TA = 25°C, VS = 28 V
–
–
19.8
mA
Supply Current
Supply Current Ratio
Reverse Battery Current4
ICC(LOW)
5.0
7
8.4
mA
ICC(HIGH)
11.8
14
16.8
mA
1.9
–
–
–
ICC(HIGH)/
ICC(LOW)
Measured as ratio of high current to low current
IRCC
VRCC = –18 V
–
–
–5
mA
tPO
VCC > VCC(min), fOP < 100 Hz
–
1
2
ms
POS
t > tPO
–
ICC(HIGH)
–
–
dI/dt
RSENSE = 100 Ω, CLOAD = 10 pF, no CBYP
(see figure 7)
–
14
–
mA/μs
Power-On State Characteristics
Power-On Time5
Power-On
State6
Output Stage
Output Slew Rate7,8
Performance Characteristics
Operating Frequency9
fOP
0
–
8000
Hz
Analog Signal Bandwidth
BW
20
40
–
kHz
Operate Point
BOP
Magnitude (see figure 6)
–
120
–
mV
Release Point
BRP
Magnitude (see figure 6)
–
120
–
mV
CALI
Quantity of rising output (current) edges
required for accurate edge detection; edge
accuracy not guaranteed during initial
calibration.
–
–
3
edge
Calibration
Initial Calibration
Continued on the next page…
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3
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
OPERATING CHARACTERISTICS (continued) Valid at VCC and TA within specification; unless otherwise noted
Characteristics
Min.
Typ.1
Max.
Unit2
Operation within specification
–
± 60
–
G
Differential signal, measured peak-to-peak;
operation within specification
30
–
1000
G
Output switching (no missed edges); duty cycle
not guaranteed
20
–
–
G
See Functional Description section
Symbol
Test Conditions
Digital-to-Analog Converter (DAC) Characteristics
Allowable User-Induced Differential
Offset
ΔBDIFFEXT
Functional Characteristics
Operating Signal Range10
BDIFF
Minimum Operating Signal
BDIFFOP(MIN)
Allowable Signal Amplitude Variation
Operational Air Gap Range
Maximum Operational Air Gap Range
Duty Cycle11
Consecutive Duty Cycle Variation12
BSOA
–
–
–
–
AG
Using Reference Target 60-0, duty cycle within
specification
0.5
–
2.75
mm
AGOP(MAX)
Using Reference Target 60-0, output switching
(no missed edges); duty cycle not guaranteed
–
–
3.00
mm
AG within specification
41
–
61
%
AG = 1.5 mm
–
±1.5
–
%
D
errD
1Typical
values are at TA = 25°C and VCC = 12 V. Performance may vary for individual units, within the specified maximum and minimum limits.
G (gauss) = 0.1 mT (millitesla).
3Maximum voltage must be adjusted for power dissipation and junction temperature; see Power Derating section.
4Negative current is defined as conventional current coming out of (sourced from) the specified device terminal.
5Power-On Time includes the time required to complete the internal automatic offset adjust after which the DAC is ready for peak acquisition.
6See Device Operation section.
7dI is the difference between 10% of I
CC(LOW) and 90% of ICC(HIGH), and dt is the time period between those two points.
8C
LOAD is the probe capacitance of the oscilloscope used to make the measurement.
9Refer to Functional Description section for performance over input magnetic frequency.
10AG is dependent on the available magnetic field. The available field is dependent on target geometry and material, and should be independently
characterized. The field available from the Reference Target is given in the Reference Target parameter section of the datasheet.
11Target rotation from pin 4 to pin 1.
12Consecutive Duty Cycle Variation represents the difference between consecutive duty cycles, D(n) – D(n–1); mean ± 3 sigma.
21
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115 Northeast Cutoff
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4
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Thermal Characteristics may require derating at maximum conditions, see Power Derating section
Characteristic
Symbol
Test Conditions*
Single layer PCB, with copper limited to solder pads
RθJA
Package Thermal Resistance
Single layer PCB, with copper limited to solder pads and 3.57
cm2) copper area each side
in.2
(23.03
Value
Unit
126
ºC/W
84
ºC/W
*Additional thermal information available on the Allegro website
Maximum Allowable V
CC(V)
Power Derating Curve
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
V CC(max)
(R θJA = 84 °C/W)
(R θJA= 126 °C/W)
V CC(min)
20
40
60
80
100
120
140
160
180
Temperature (°C)
Power Dissipation, PD (m W)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
RQJA = 84 ºC/W
RQJA = 126 ºC/W
20
40
60
80
100
120
Temperature (°C)
140
160
180
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115 Northeast Cutoff
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Reference Target 60-0 (60 Tooth Target)
Characteristics
Symbol
Test Conditions
Typ.
Units
Symbol Key
120
mm
t
Do
Outside diameter of target
Face Width
F
Breadth of tooth, with respect
to branded face
6
mm
Angular Tooth Thickness
t
Length of tooth, with respect
to branded face
3
deg.
Angular Valley Thickness
tv
Length of valley, with respect
to branded face
3
deg.
Tooth Whole Depth
ht
3
mm
–
–
Outside Diameter
Material
Low Carbon Steel
Do
ht
F
tv
Air Gap
Branded Face of Package
Branded Face
of Package
Reference Target
60-0
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Characteristic Performance
Supply Current (Low) versus Supply Voltage
-40°C
25°C
150°C
8.0
Vcc: 4V
Vcc: 12V
Vcc: 24V
8.0
7.5
ICC(LOW) (mA)
7.5
ICC(LOW) (mA)
Supply Current (Low) versus Ambient Temperature
7.0
6.5
7.0
6.5
6.0
6.0
5.5
5.5
5.0
5.0
0
5
10
15
20
-50
25
0
Suppply Current (High) versus Supply Voltage
100
150
Supply Current (High) versus Ambient Temperature
16.8
16.8
15.8
15.8
ICC(HIGH) (mA)
15.3
Vcc: 24V
Vcc: 12V
Vcc: 4V
16.3
-40°C
25°C
150°C
16.3
14.8
14.3
13.8
15.3
14.8
14.3
13.8
13.3
13.3
12.8
12.8
12.3
12.3
11.8
11.8
0
5
10
15
20
25
-50
0
VCC (V)
50
100
150
TA (°C)
Supply Current Ratio versus Ambient Temperature
2.50
Vcc: 4V
Vcc: 18V
2.40
ICC(HIGH) / ICC(LOW)
ICC(HIGH) (mA)
50
TA (°C)
VCC (V)
2.30
2.20
2.10
2.00
1.90
-50
0
50
100
150
TA (°C)
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Duty Cycle versus Air Gap
Allegro 60-0 Target at 1000 rpm
61
59
55
53
51
49
47
150°C
25°C
-40°C
45
43
41
0.5
1
1.5
2
2.5
3
AG (mm)
The trend of duty cycle versus air gap is driven by the actual
magnetic profile of the target (see Reference Target figures)
Duty Cycle versus Ambient Temperature
Allegro 60-0 Target at 1000 rpm
61
59
57
Duty Cycle (%)
Duty Cycle (%)
57
55
53
51
49
47
AG: 0.5mm
AG: 1.25mm
AG: 2.75mm
45
43
41
-50
0
50
100
150
TA (°C)
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115 Northeast Cutoff
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Functional Description
Hall Technology
This single-chip differential Hall-effect sensor IC possesses
two Hall elements spaced at a fixed distance (1.5 mm), which
simultaneously are affected by the magnetic profile of the target,
and generate a differential internal analog voltage, VPROC, that is
processed for precise switching of the digital output signal.
The Hall IC is self-calibrating and also possesses a temperature
compensated amplifier and offset compensation circuitry. Its
voltage regulator provides supply noise rejection throughout the
operating voltage range. Changes in temperature do not greatly
affect this device due to the stable amplifier design and the offset
compensation circuitry. The Hall transducers and signal processing electronics are integrated on the same silicon substrate, using
a proprietary BiCMOS process.
Target Profiling
An operating device is capable of providing digital information that is representative of the magnetic features on a rotating
target. The waveform diagram shown in figure 3 represents the
automatic translation of the magnetic profile to the digital output
signal of the IC.
Output Polarity
Figure 3 shows the output polarity for the orientation of the target
and package shown in figure 2. The target direction of rotation
shown is perpendicular to the leads, across the face of the device,
from pin 1 to pin 4. This results in the IC output switching from
high, ICC(HIGH), to low ICC(LOW), as the leading edge of a tooth (a
rising mechanical edge, as detected by the IC) passes the branded
face. In this configuration, the device output current switches to
its low polarity when a tooth is the target feature nearest to the
branded face. If the direction of rotation is reversed, then the
output polarity inverts.
Note: the translated output voltage polarity is dependent on the
position of a sense resistor, RSENSE (see figure 4).
Target
Mechanical Profile
Representative
Differential
Magnetic Profile
IC Electrical
Output Profile, IOUT
Figure 3. Output Profile of a gear target for the polarity indicated in figure 2.
VCC
VCC
Target (Gear)
Element Pitch
Hall Element 2
Dual-Element
Hall Effect Device
RSENSE
Hall Element 1
Hall IC
Pole Piece
(Concentrator)
South Pole
ICC
VOUT(H)
1
Back-biasing
Rare-earthPellet
North Pole
Case
(Pin 4 Side)
(Pin 1 Side)
Branded Face
of Package
VCC
VCC
ATS682
ATS682
GND
4
GND
4
VOUT(L)
ICC
Figure 1. Relative motion of the target is detected by the dual Hall
elements mounted on the Hall IC.
Rotating Target
1
RSENSE
I+
IOUT
V+
VOUT(L)
1
4
V+
VOUT(H)
Figure 2. This left-to-right (pin 1 to pin 4) direction of target rotation results
in a low output signal when a tooth of the target gear is nearest the face
of the package (see Figure 3). A right-to-left (pin 4 to pin 1) rotation inverts
the output signal polarity.
Figure 4. Voltage profiles for high-side and low-side two-wire sensing.
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ATS682LSH
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
Automatic Gain Control (AGC)
AGC allows the device to operate with an optimal internal electrical signal, regardless of the air gap (within the operating signal
range specification). During calibration, the device determines
the peak-to-peak amplitude of the signal generated by the target
and automatically adjusts the signal gain. Figure 5 illustrates the
effect of this feature.
Automatic Offset Adjust (AOA)
AOA circuitry automatically compensates for the effects of chip,
magnet, and installation offsets. (For capability, see Allowable
User-Induced Differential Offset, in the Operating Characteristics
table.) This circuitry is continuously active in both calibration
mode and running mode. Continuous operation of AOA allows
the IC to compensate for offset drift and for offsets induced by
temperature variations over time.
Digital Peak Detection
A digital-to-analog converter (DAC) tracks the internal analog
voltage signal VPROC, and is used for holding the peak value
of the internal analog signal. In the example shown in figure 6,
the DAC would first track up with the signal and hold the upper
peak value. When VPROC drops below this peak value by BOP, the
device hysteresis, the output switches, and the DAC begin tracking the signal downward toward the negative VPROC peak. After
the DAC acquires the negative peak, the output again switches
states when VPROC is greater than the peak by the value BRP. At
this point, the DAC tracks up again and the cycle repeats. The
digital tracking of the differential analog signal allows the IC to
achieve true zero-speed operation.
Ferrous Target
Mechanical Profile
V+
Internal Differential
Analog Signal
Response, without AGC
V+
AGLarge
Internal
Differential
Analog Signal
BOP
BRP
AGSmall
V+
Internal Differential
Analog Signal
Response, with AGC
I+
AGSmall
AGLarge
Figure 5: Automatic Gain Control (AGC). The AGC function corrects for
variances in the air gap. Differences in the air gap affect the magnetic
gradient, but AGC prevents that from affecting device performance, as
shown in the lowest panel.
Device
Output Current
Figure 6. Peak detection switchpoint detail
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Power Supply Protection
The device contains an on-chip regulator and can operate over a
wide VCC range. For devices that need to operate from an unregulated power supply, transient protection must be added externally.
For applications using a regulated line, EMI/RFI protection may
still be required. Contact Allegro for information on the circuitry
needed for compliance with various EMC specifications. Refer to
figure 7 for an example of a basic application circuit.
Undervoltage Lockout
When the supply voltage falls below the undervoltage lockout
threshold, VCC(UV), the device enters Reset mode, where the
output state returns to the Power-On State (POS) until sufficient
VCC is supplied. ICC levels may not meet datasheet limits when
VCC < VCC(min).
Assembly Description
This device is molded into a plastic body that has been optimized
for size, ease of assembly, and manufacturability. High operat-
ing temperature materials are used in all aspects of construction.
Refer to the Allegro website, www.allegromicro.com, for more
specific applications notes on finished package processing.
Diagnostics
The regulated current output is configured for two-wire applications, requiring one less wire for operation than do switches with
the traditional open-collector output. Additionally, the system
designer inherently gains diagnostics because there is always
output current flowing, which should be in either of two narrow ranges, shown in figure 8 as ICC(HIGH) and ICC(LOW). Any
current level not within these ranges indicates a fault condition.
If ICC > ICC(HIGH)(max), then a short condition exists, and if ICC
< ICC(LOW)(min), then an open condition exists. Any value of ICC
between the allowed ranges for ICC(HIGH) and ICC(LOW) indicates
a general fault condition.
V+
1
VCC
ATS682
CBYP
+mA
0.01 μF
ICC(HIGH)(max)
GND
4
Test pin floating
ICC(HIGH)(min)
ICC(LOW)(max)
ECU
ICC(LOW)(min)
Short

Range for Valid ICC(HIGH)

Range for Valid ICC(LOW)
Fault
Open
0
100 7
RSENSE
CLOAD
Figure 7. Typical application circuit
Figure 8. Diagnostic characteristics of supply current values
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Device Operation
Power-On When power (VCC > VCC(min)) is applied to the
device, a short period of time is required to activate the various
portions of the IC. During this period, the ATS682 powers-on in
the high current state, ICC(HIGH). After power-on, there are conditions that could induce a change in the output state. Such an event
could be caused by thermal transients, but it would also require a
static applied magnetic field, proper signal polarity, and particular
direction and magnitude of internal signal drift.
Initial Offset Adjust The IC initially compensates for differential offset, ΔBAPP, that results from chip, magnet, and installation alignment. Once the effective differential magnetic offset
has been cancelled, the digital tracking DAC is ready to track the
signal and provide output switching.
The period of time required for both power-on and initial offset
adjust is defined as the Power-On Time specification.
Calibration Mode The calibration mode allows the IC to automatically select the proper signal gain and continue to adjust for
1
2
DC differential magnetic offset. The AGC is active, and selects
the optimal signal gain based on the amplitude of the VPROC
signal. Following each adjustment to the AGC DAC, the Offset
DAC is also adjusted to ensure the internal analog signal is properly centered. During this mode, the tracking DAC is active and
output switching occurs, but the duty cycle is not guaranteed to
be within specification.
Running Mode After the initial calibration process (CALI
edges) establishes a signal gain, the device moves to Running
mode. During Running mode, the IC tracks the input signal and
continues to give an output edge for every peak of the signal.
AOA remains active to compensate for any offset drift over time.
The ATS682 also incorporates an algorithm for adjusting the
signal gain during Running mode. This algorithm is designed to
optimize the VPROC signal amplitude in instances where the magnetic signal during the calibration period is not representative of
the amplitude of the magnetic signal for the installed application
air gap (see figure 9).
3
4
5
BOP
Internal Differential
Signal, VPROC
BOP
BRP
BRP
IC Electrical
Output, IOUT
Figure 9: Operation of Running Mode Gain Adjust.
Position 1. The device is initially powered-on. Self-calibration occurs.
Position 2. Small amplitude oscillation of the target sends an erroneously small differential signal to the device. The amplitude of VPROC is greater than
the switching hysteresis (BOP and BRP), and the device output switches.
Position 3. The calibration period completes on the third rising output edge, and the device enters Running mode.
Position 4. True target rotation occurs and the correct magnetic signal is generated for the installation air gap. The established signal gain is too large for
the rotational magnetic signal of the target, at the given air gap.
Position 5. Running mode calibration corrects the signal gain to an optimal level for the installation air gap.
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Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
gap change between Hall element and target), target eccentricity,
magnet temperature coefficient or a combination thereof.
Characteristic Allowable Signal Amplitude Variation
The colored area in figure 10 shows BSOA, the safe operating
area of allowable magnetic signal amplitude within which the IC
will continue output switching. The output duty cycle is wholly
dependent on the magnetic signature of the target across the air
gap range of movement, and may not always be within specification throughout the entire operating region (to BDIFF(max)).
Signal amplitude changes may be due to deflection (relative air
The axis parameters for the chart in figure 10 are defined in figure 11. As an example, assume the case where the signal changes
from the nominal at the installed air gap (BCAL) within the range
defined by an increase factor of BDIFF(max) / BCAL = 3.0, and a
decrease of BDIFF(lim) / BCAL = 0.75. This case is plotted with an
“x” in figure 10.
0.2
Guard-banded
Nominal
0.3
BDIFF(lim) / BCAL
0.4
0.5
0.6
0.7
x
0.8
Safe Operating
Area
0.9
1.0
1.1
1
2
3
4
5
6
7
8
9
BDIFF(max) / BCAL
Figure 10. Allowable Signal Amplitude Change chart
BDIFF(max)
BCAL
BDIFF(lim)
Figure 11. Illustration of BCAL, BDIFF(max) and BDIFF(lim) for amplitude
variation discussion. BCAL is the magnetic amplitude at the IC during its
calibration cycle BDIFF(max) and BDIFF(lim) are the maximum and minimum
magnetic amplitudes during IC operation.
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13
ATS682LSH
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
Power Derating
The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RJC, is
a relatively small component of RJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN

T = PD × RJA
TJ = TA + ΔT
(1)
Example: Reliability for VCC at TA = 150°C.
Observe the worst-case ratings for the device, specifically:
RJA = 126°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC = 16.8 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
T(max) = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = T(max) ÷ RJA = 15°C ÷ 126 °C/W = 119 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC = 119 mW ÷ 16.8 mA = 7.1V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.
(2)
(3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 7 mA, and RJA = 126 °C/W, then:
PD = VCC × ICC = 12 V × 7 mA = 84 mW

T = PD × RJA = 84 mW × 126 °C/W = 10.6°C
TJ = TA + T = 25°C + 10.6°C = 35.6°C
A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RJA and TA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
Package SH 4-Pin SIP
5.50±0.05
F
0.75
F
E
0.75
B
8.00±0.05
LLLLLLL
NNN
5.80±0.05
E1
E2
YYWW
Branded
Face
1.70±0.10
5.00±0.10
D
4.00±0.10
1
2
3
4
= Supplier emblem
L = Lot identifier
N = Last three numbers of device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
A
0.60±0.10
Standard Branding Reference View
0.71±0.05
For Reference Only, not for tooling use (reference DWG-9003)
Dimensions in millimeters
A Dambar removal protrusion (16X)
24.65±0.10
B Metallic protrusion, electrically connected to pin 4 and substrate (both sides)
C Thermoplastic Molded Lead Bar for alignment during shipment
+0.06
0.38 –0.04
1.00±0.10
13.10±0.10
D Branding scale and appearance at supplier discretion
E Active Area Depth 0.43 mm REF
F
Hall elements (E1, E2); not to scale
A
1.0 REF
1.60±0.10
C
1.27±0.10
0.71±0.10
0.71±0.10
5.50±0.10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
ATS682LSH
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
Copyright ©2009-2013, Allegro MicroSystems, LLC
The products described herein are manufactured under one or more of the following U.S. patents: 5,264,783; 5,389,889; 5,442,283; 5,517,112;
5,581,179; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; 6,091,239; 6,100,680; 6,232,768; 6,242,908; 6,265,865; 6,297,627; 6,525,531;
6,690,155; 6,693,419; 6,919,720; 7,046,000; 7,053,674; 7,138,793; 7,199,579; 7,253,614; 7,365,530; 7,368,904; 7,518,414; 7,548,056; and other
patents pending.
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
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use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
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