Data Sheet

BUK762R0-40C
N-channel TrenchMOS standard level FET
Rev. 02 — 20 August 2007
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using Philips Ultra High-Performance Automotive (UHP) TrenchMOS technology.
This product has been designed and qualified to the appropriate AEC standard for use in
Automotive critical applications.
1.2 Features
„ 175 °C rated
„ Q101 compliant
„ Low on-state resistance
„ Standard level compatible
1.3 Applications
„ 12 V loads
„ General purpose power switching
„ Automotive systems
„ Motors, lamps, solenoids
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
-
-
100
A
ID
drain current
VGS = 10 V; Tmb = 25 °C;
see Figure 1 and 4
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
-
333
W
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 13 and
12
-
1.7
2
mΩ
-
-
1.2
J
[1][2]
Static characteristics
RDSon
drain-source on-state
resistance
Avalanche ruggedness
EDS(AL)S non-repetitive
ID = 100 A; Vsup ≤ 40 V;
drain-source avalanche RGS = 50 Ω; VGS = 10 V;
energy
Tj(init) = 25 °C; inductive load
type unclamped inductive load
[1]
Continuous current is limited by package.
[2]
Refer to document 9397 750 12572 for further information.
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pinning
Pin
Symbol
Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base;
connected to drain
Simplified outline
Graphic Symbol
D
mb
[1]
G
mbb076
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
BUK762R0-40C
Package
Name
Description
Version
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead SOT404
cropped)
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
-
40
V
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
RGS = 20 kΩ
VDGR
drain-gate voltage
VGS
gate-source voltage
ID
drain current
-
40
V
-20
20
V
[1]
-
276
A
Tmb = 100 °C; VGS = 10 V; see Figure 1
[2][3]
-
100
A
Tmb = 25 °C; VGS = 10 V; see Figure 1 and 4
[2][3]
Tmb = 25 °C; VGS = 10 V; see Figure 1 and 4
-
100
A
IDM
peak drain current
Tmb = 25 °C; tp ≤ 10 μs; duty type pulsed;
see Figure 4
-
1104
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
333
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
-
1.2
J
-
-
J
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source avalanche
energy
ID = 100 A; Vsup ≤ 40 V; RGS = 50 Ω;
VGS = 10 V; Tj(init) = 25 °C; inductive load type
unclamped inductive load
EDS(AL)R repetitive drain-source
avalanche energy
see Figure 3
[6][7]
BUK762R0-40C_2
Product data sheet
[4][5]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
2 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
Source-drain diode
source current
IS
peak source current
ISM
Tmb = 25 °C
[1]
-
276
A
Tmb = 25 °C
[2][3]
-
100
A
-
1104
A
tp ≤ 10 μs; duty type pulsed; Tmb = 25 °C
[1]
Current is limited by power dissipation chip rating.
[2]
Continuous current is limited by package.
[3]
Refer to document 9397 750 12572 for further information.
[4]
Maximum value not quoted. Repetitive rating defined in avalanche rating figure.
[5]
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[6]
Repetitive avalanche rating limited by an average junction temperature of 170 °C.
[7]
Refer to application note AN10273 for further information.
003aab004
300
03aa16
120
Pder
(%)
ID
(A)
80
200
40
100
(1)
0
0
0
50
100
150
Tmb (°C)
200
VGS • 10 V
0
P der =
(1) Capped at 100 A due to package.
Fig 1. Continuous drain current as a function of
mounting base temperature
P tot
P tot (25°C )
100
150
Tmb (°C)
200
× 100 %
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
BUK762R0-40C_2
Product data sheet
50
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
3 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab013
103
IAL
(A)
102
(1)
(2)
10
(3)
1
10-3
10-2
10-1
1
tAL (ms)
10
(1) Singleípulse; Tmb = 25 °C.
(2) Singleípulse; Tmb = 150 °C.
(3) Repetitive.
Fig 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time
003aab028
104
ID
(A)
limit RDSon = VDS/ID
103
δ = 10 μs
100 μs
102
(1)
DC
10
1 ms
10 ms
100 ms
1
10−1
10−1
1
102
10
VDS (V)
Tmb = 25 °C; IDM is single pulse
(1) Capped at 100 A due to package.
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK762R0-40C_2
Product data sheet
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Rev. 02 — 20 August 2007
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BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-a)
thermal resistance
from junction to
ambient
mounted on a printed-circuit
board; minimum footprint; vertical
in still air
-
50
-
K/W
Rth(j-mb)
thermal resistance
from junction to
mounting base
see Figure 5
-
-
0.45
K/W
003aab020
1
Zth(j-mb)
(K/W) δ = 0.5
0.2
10−1
0.1
0.05
0.02
10−2
δ=
P
tp
T
single shot
t
tp
T
10−3
10−6
10−5
10−4
10−3
10−2
10−1
tp (s)
1
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ID = 0.25 mA; VGS = 0 V;
Tj = 25 °C
40
-
-
V
ID = 0.25 mA; VGS = 0 V;
Tj = -55 °C
36
-
-
V
2
3
4
V
ID = 1 mA; VDS = VGS;
Tj = -55 °C; see Figure 11
-
-
4.4
V
ID = 1 mA; VDS = VGS;
Tj = 175 °C; see Figure 11
1
-
-
V
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
0.02
1
μA
VDS = 40 V; VGS = 0 V;
Tj = 175 °C
-
-
500
μA
Static characteristics
V(BR)DSS
VGSth
IDSS
drain-source
breakdown voltage
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
voltage
see Figure 10
drain leakage current
BUK762R0-40C_2
Product data sheet
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Rev. 02 — 20 August 2007
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BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IGSS
gate leakage current
VDS = 0 V; VGS = 20 V; Tj = 25 °C
-
2
100
nA
VDS = 0 V; VGS = -20 V;
Tj = 25 °C
-
2
100
nA
VGS = 10 V; ID = 25 A;
Tj = 175 °C; see Figure 12 and
13
-
-
3.75
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 13 and 12
-
1.7
2
mΩ
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 16
-
0.85
1.2
V
RDSon
drain-source on-state
resistance
Source-drain diode
VSD
source-drain voltage
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/μs;
VGS = -10 V; VDS = 30 V;
Tj = 25 °C
-
75
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/μs;
VGS = -10 V; VDS = 30 V;
Tj = 25 °C
-
57
-
nC
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 32 V;
VGS = 10 V; Tj = 25 °C;
see Figure 14
-
175
-
nC
QGS
gate-source charge
ID = 25 A; VDS = 32 V;
VGS = 10 V; Tj = 25 °C;
see Figure 14
-
38
-
nC
QGD
gate-drain charge
ID = 25 A; VDS = 32 V;
VGS = 10 V; Tj = 25 °C;
see Figure 14
-
67
-
nC
Ciss
input capacitance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
-
8492
11323
pF
Coss
output capacitance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
-
1606
1927
pF
Crss
reverse transfer
capacitance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
-
1101
1508
pF
td(on)
turn-on delay time
VDS = 30 V; RL = 1.2 Ω;
VGS = 10 V; RG(ext) = 10 Ω;
Tj = 25 °C
-
65
-
ns
tr
rise time
VDS = 30 V; RL = 1.2 Ω;
VGS = 10 V; RG(ext) = 10 Ω;
Tj = 25 °C
-
133
-
ns
td(off)
turn-off delay time
VDS = 30 V; RL = 1.2 Ω;
VGS = 10 V; RG(ext) = 10 Ω;
Tj = 25 °C
-
146
-
ns
BUK762R0-40C_2
Product data sheet
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Rev. 02 — 20 August 2007
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BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tf
fall time
VDS = 30 V; RL = 1.2 Ω;
VGS = 10 V; RG(ext) = 10 Ω;
Tj = 25 °C
-
119
-
ns
LD
internal drain
inductance
from upper edge of drain
mounting base to centre of die;
Tj = 25 °C
-
2.5
-
nH
LS
internal source
inductance
from source lead 6 mm from
package to source bond pad;
Tj = 25 °C
-
7.5
-
nH
003aab008
180
003aab010
400
ID
(A)
gfs
(S)
300
120
200
60
100
Tj = 175 °C
Tj = 25 °C
0
0
0
20
40
60
ID (A)
80
T j = 25 °C; VDS = 25 V
0
3
4
6
VGS (V)
7
VDS = 25 V
Fig 6. Forward transconductance as a function of
drain current; typical values
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
BUK762R0-40C_2
Product data sheet
1
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
7 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab005
300
20
10
7
6.5
ID
(A)
003aab083
6
RDSon
(mΩ)
VGS (V) = 6
5.5
5
VGS (V) = 6
200
4
5.5
3
7
100
8
5
2
10
20
4.5
1
0
0
2
4
6
8
0
10
VDS (V)
T j = 25 °C
100
200
ID (A)
300
T j = 25 °C
Fig 8. Output characteristics: drain current as a
function of drain-source voltage; typical values
03aa35
10−1
ID
(A)
Fig 9. Drain-source on-state resistance as a function
of drain current; typical values
03aa32
5
VGS(th)
(V)
min
10−2
typ
max
4
10−3
3
10−4
2
10−5
1
10−6
0
2
4
6
0
−60
max
typ
min
0
VGS (V)
T j = 25 °C; VDS = VGS
120
180
Tj (°C)
ID = 1 m A; VDS = VGS
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
Fig 11. Gate-source threshold voltage as a function of
junction temperature
BUK762R0-40C_2
Product data sheet
60
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
8 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab082
3.5
RDSon
(mΩ)
03aa27
2
a
3
1.5
2.5
1
2
0.5
1.5
0
-60
1
5
10
15
VGS (V)
20
T j = 25 °C; ID = 25 A
a=
Fig 12. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aab011
10
VGS
(V)
0
60
120
Tj (°C)
180
R DSon
R DSon (25°C )
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aab009
14000
Ciss
C
(pF)
8
10500
VDD = 14 V
Coss
VDD = 32 V
6
7000
Crss
4
3500
2
0
0
50
100
150
QG (nC)
200
0
10−2
1
102
10
VDS (V)
T j = 25 °C; ID = 25 A
VGS = 0 V ; f = 1 M H z
Fig 14. Gate-source voltage as a function of gate
charge; typical values
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
BUK762R0-40C_2
Product data sheet
10−1
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
9 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab012
200
IS
(A)
150
100
Tj = 175 °C
Tj = 25 °C
50
0
0.0
0.5
1.0
1.5
VSD (V)
2.0
VGS = 0 V
Fig 16. Source current as a function of source-drain voltage; typical values
BUK762R0-40C_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
10 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
7. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 17. Package outline SOT404 (D2PAK)
BUK762R0-40C_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
11 of 15
BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
8. Soldering
10.85
10.60
10.50
1.50
7.50
7.40
1.70
2.25 2.15
8.15
8.275
8.35
1.50
4.60
0.30
4.85
5.40
7.95
8.075
3.00
0.20
1.20
1.30
1.55
solder lands
solder resist
5.08
msd057
occupied area
solder paste
Fig 18. Reflow soldering footprint for SOT404
BUK762R0-40C_2
Product data sheet
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Rev. 02 — 20 August 2007
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BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
9. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK762R0-40C_2
20070820
Product data sheet
-
BUK762R0-40C_1
Modifications:
BUK762R0-40C_1
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
20060810
Product data sheet
BUK762R0-40C_2
Product data sheet
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 20 August 2007
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BUK762R0-40C
NXP Semiconductors
N-channel TrenchMOS standard level FET
10. Legal information
10.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
10.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
10.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
11. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
BUK762R0-40C_2
Product data sheet
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Rev. 02 — 20 August 2007
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BUK762R0-40C
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N-channel TrenchMOS standard level FET
12. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
10.1
10.2
10.3
10.4
11
12
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 August 2007
Document identifier: BUK762R0-40C_2
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