8160Z1836B

GS8160Z18/36BT-250/200/150
250 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8160Z18/36BT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
me
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for
Ne
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De
sig
The GS8160Z18/36BT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
ct
Features
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100-Pin TQFP
Commercial Temp
Industrial Temp
The GS8160Z18/36BT is implemented with GSI's high
performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package.
Parameter Synopsis
Re
co
m
Pipeline
3-1-1-1
-200
-150
Unit
tKQ
tCycle
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Curr (x18)
Curr (x36)
295
345
245
285
200
225
mA
mA
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr (x18)
Curr (x36)
225
255
200
220
185
205
mA
mA
No
t
Flow Through
2-1-1-1
-250
Rev: 1.06 9/2008
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
n—
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A
A
E1
E2
NC
NC
BB
BA
E3
VDD
VSS
CK
W
CKE
G
ADV
A
A
A
A
GS8160Z18BT Pinout
NC
NC
NC
Ne
w
me
nd
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for
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
Re
co
LBO
m
A
No
t
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
De
sig
VDDQ
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.06 9/2008
2/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
n—
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A
A
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
W
CKE
G
ADV
A
A
A
A
GS8160Z36BT Pinout
Rev: 1.06 9/2008
Ne
w
me
nd
ed
for
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
Re
co
LBO
m
A
No
t
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD2
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
De
sig
DQPC
DQC
DQC
VDDQ
3/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
100-Pin TQFP Pin Descriptions
Type
Description
A 0, A 1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
BA
In
Byte Write signal for data inputs DQA; active low
BB
In
Byte Write signal for data inputs DQB; active low
BC
In
Byte Write signal for data inputs DQC; active low
BD
In
Byte Write signal for data inputs DQD; active low
W
In
Write Enable; active low
E1
In
E2
In
Chip Enable; Active High. For self decoded depth expansion
E3
In
Chip Enable; Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
NC
—
No Connect
DQA
I/O
DQB
I/O
DQC
I/O
DQD
I/O
ZZ
In
FT
In
LBO
In
VDD
In
VSS
In
VDDQ
In
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Symbol
Clock Input Signal
De
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Chip Enable; active low
Byte A Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
Core power supply
Ground
Output driver power supply
No
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Ne
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Byte B Data Input and Output pins
Rev: 1.06 9/2008
4/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
Rev: 1.06 9/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5/23
G
CKE
CK
E3
E2
E1
BD
BC
BB
BA
W
ADV
No
t
LBO
A0–An
K
K
Q
K
SA1
SA0
Control Logic
Data Coherency
Read, Write and
Match
Register 1
Write Address
K
SA1’
SA0’
Write Drivers
Sense Amps
K
D
Q
FT
Register 1
Register 2
K
Write Data
Write Data
K
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Memory
Array
De
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FT
Ne
w
Register 2
Write Address
Burst
Counter
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Re
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K
D
ct
DQa–DQn
GS8160Z18/36BT-250/200/150
GS8160Z18/36B NBT SRAM Functional Block Diagram
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Functional Details
ct
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
W
BA
BB
BC
BD
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
De
sig
Function
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Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
H
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for
Ne
w
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Re
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Write operation occurs when the RAM is selected, CKE is asserted low, and the Write input is sampled low at the rising edge of
clock. The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A
write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
No
t
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.06 9/2008
6/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Synchronous Truth Table
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ
External
L-H
L
Read Cycle, Continue Burst
B
Next
L-H
L
NOP/Read, Begin Burst
R
External
L-H
L
Dummy Read, Continue Burst
B
Next
L-H
L
Write Cycle, Begin Burst
W
External
L-H
L
Write Abort, Begin Burst
W
External
L-H
L
Write Cycle, Continue Burst
B
Next
L-H
L
Write Abort, Continue Burst
B
Next
L-H
L
Deselect Cycle, Power Down
D
None
L-H
L
Deselect Cycle, Power Down
D
None
L-H
L
Deselect Cycle, Power Down
D
None
L-H
L
Deselect Cycle, Continue
D
None
L-H
None
X
Current
L-H
Clock Edge Ignore, Stall
H
X
L
H
L
L
L
Q
Notes
H
X
X
X
X
X
L
L
Q
1,10
L
H
X
L
H
L
H
L
High-Z
2
H
X
X
X
X
X
H
L
High-Z
1,2,10
L
L
L
L
H
L
X
L
D
3
L
L
H
L
H
L
X
L
X
2,3
H
X
L
X
X
X
X
L
D
1,3,10
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
L
X
X
H
X
X
X
L
High-Z
L
X
X
X
X
H
X
L
High-Z
L
X
X
X
L
X
X
L
High-Z
Ne
w
Sleep Mode
L
ct
R
DQ
De
sig
Read Cycle, Begin Burst
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Operation
L
H
X
X
X
X
X
X
L
High-Z
X
X
X
X
X
X
X
X
H
High-Z
H
X
X
X
X
X
X
X
L
-
1
4
No
t
Re
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for
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.06 9/2008
7/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Pipeline and Flow Through Read Write Control State Diagram
D
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B
Deselect
R
D
R
D
W
New Read
W
B
R
W
R
ƒ Transition
Current State (n)
No
t
Command
Re
co
m
Clock (CK)
Ne
w
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
n+1
n+2
ƒ
Current State
D
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
Next State (n+1)
n
B
Notes:
me
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Input Command Code
W
Burst Write
De
sig
Burst Read
D
Key
New Write
R
B
B
W
ƒ
n+3
ƒ
ƒ
Next State
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 1.06 9/2008
8/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Pipeline Mode Data I/O State Diagram
R
High Z
(Data In)
D
R B
Intermediate
Data Out
(Q Valid)
W
D
Intermediate
Intermediate
W
Intermediate
ct
B W
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Intermediate
R
High Z
B
D
Key
Ne
w
Input Command Code
ƒ Transition
Transition
Intermediate State (N+1)
me
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for
Current State (n)
n
Next State (n+2)
n+1
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n+2
n+3
Command
ƒ
ƒ
ƒ
No
t
Re
co
m
Clock (CK)
De
sig
Intermediate
Current State
Intermediate
State
Next State
ƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.06 9/2008
9/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Flow Through Mode Data I/O State Diagram
R B
R
High Z
(Data In)
Data Out
(Q Valid)
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Pr
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W
ct
B W
D
D
W
R
High Z
B
Key
Ne
w
Input Command Code
ƒ Transition
Current State (n)
me
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for
Re
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Command
n+1
ƒ
Current State
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Next State (n+1)
n
Clock (CK)
De
sig
D
n+2
ƒ
n+3
ƒ
ƒ
Next State
No
t
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.06 9/2008
10/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
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Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Pin Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
De
sig
Mode Name
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
Ne
w
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Linear Burst Sequence
me
nd
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for
Burst Counter Sequences
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
2nd address
01
10
3rd address
10
11
4th address
11
Re
co
m
1st address
00
A[1:0] A[1:0] A[1:0] A[1:0]
10
11
1st address
00
01
10
11
11
00
2nd address
01
00
11
10
00
01
3rd address
10
11
00
01
01
10
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
No
t
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.06 9/2008
BPR 1999.05.18
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
n—
Di
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Pr
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ct
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
tZZR
tZZS
tZZH
De
sig
ZZ
No
t
Re
co
m
me
nd
ed
for
Ne
w
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.06 9/2008
12/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
VI/O
Voltage on I/O Pins
VIN
Voltage on Other Input Pins
IIN
Input Current on Any Pin
IOUT
Output Current on Any I/O Pin
PD
Package Power Dissipation
TSTG
Storage Temperature
TBIAS
Temperature Under Bias
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
V
–0.5 to VDDQ +0.5
V
–0.5 to VDD +0.5
V
+/–20
mA
+/–20
mA
1.5
W
–55 to 125
o
–55 to 125
o
C
C
De
sig
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Parameter
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
Ne
w
Power Supply Voltage Ranges
VDD3
3.0
3.3
3.6
V
VDD2
2.3
2.5
2.7
V
me
nd
ed
for
2.5 V Supply Voltage
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes
No
t
Re
co
m
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
Rev: 1.06 9/2008
13/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.8
V
1
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1,3
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
ct
VDDQ3 Range Logic Levels
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Parameter
Symbol
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
–0.3
—
0.3*VDD
V
1,3
De
sig
Min.
Ne
w
VDDQ2 Range Logic Levels
VILQ
me
nd
ed
for
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
2
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
°C
2
Re
co
m
Parameter
No
t
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
Rev: 1.06 9/2008
14/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
50% tKC
VDD +1.5 V
VSS
n—
Di
sco
nt
inu
ed
Pr
od
u
50%
ct
50%
VDD
VSS – 2.0 V
50% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
AC Test Conditions
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output load
me
nd
ed
for
Output reference level
Ne
w
Parameter
De
sig
Note:
These parameters are sample tested.
VDDQ/2
Fig. 1
Output Load 1
DQ
No
t
Re
co
m
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Rev: 1.06 9/2008
15/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
DC Electrical Characteristics
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
FT Input Current
IIN2
Output Leakage Current
IOL
Output High Voltage
VOH2
Output High Voltage
VOH3
Output Low Voltage
VOL
ct
Parameter
1 uA
100 uA
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
IOL = 8 mA
—
0.4 V
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
–1 uA
–1 uA
Rev: 1.06 9/2008
16/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Operating Currents
-250
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Operating
Current
Symbol
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Pipeline
IDD
IDDQ
305
40
315
40
255
30
265
30
205
20
215
20
mA
Flow Through
IDD
IDDQ
235
20
245
20
205
15
215
15
190
15
200
15
mA
Pipeline
IDD
IDDQ
275
20
285
20
230
15
240
15
185
15
195
15
mA
Flow Through
IDD
IDDQ
215
10
225
10
190
10
200
10
175
10
185
10
mA
Pipeline
ISB
40
50
40
50
40
50
mA
Flow Through
ISB
40
50
40
50
40
50
mA
Pipeline
IDD
85
90
75
80
60
65
mA
Flow Through
IDD
60
65
50
55
50
55
mA
Mode
(x32/
x36)
(x18)
Standby
Current
ZZ ≥ VDD – 0.2 V
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—
—
ct
Test Conditions
-150
–40
to
85°C
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
-200
0
to
70°C
Unit
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Rev: 1.06 9/2008
17/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
AC Electrical Characteristics
Clock to Output Valid
tKQ
Clock to Output Invalid
tKQX
Clock to Output in Low-Z
tLZ1
Setup time
tS
Hold time
tH
Clock Cycle Time
tKC
Clock to Output Valid
tKQ
Clock to Output Invalid
tKQX
1
Clock to Output in Low-Z
tLZ
Setup time
tS
Hold time
tH
Clock HIGH Time
tKH
-150
Min
Max
Min
Max
Min
Max
4.0
—
5.0
—
ct
tKC
-200
6.7
—
n—
Di
sco
nt
inu
ed
Pr
od
u
Clock Cycle Time
-250
Unit
ns
—
2.5
—
3.0
—
3.8
ns
1.5
—
1.5
—
1.5
—
ns
1.5
—
1.5
—
1.5
—
ns
1.2
—
1.4
—
1.5
—
ns
0.2
—
0.4
—
0.5
—
ns
5.5
—
6.5
—
7.5
—
ns
—
5.5
—
6.5
—
7.5
ns
2.0
—
2.0
—
2.0
—
ns
2.0
—
2.0
—
2.0
—
ns
1.5
—
1.5
—
1.5
—
ns
0.5
—
0.5
—
0.5
—
ns
1.3
—
1.3
—
1.5
—
ns
1.5
—
1.5
—
1.7
—
ns
De
sig
Flow Through
Symbol
1.5
2.5
1.5
3.0
1.5
3.0
ns
Clock LOW Time
tKL
Clock to Output in
High-Z
tHZ1
G to Output Valid
tOE
—
2.5
—
3.0
—
3.8
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
ns
G to output in High-Z
ZZ setup time
tOHZ1
me
nd
ed
for
ZZ hold time
Ne
w
Pipeline
Parameter
ZZ recovery
—
2.5
—
3.0
—
3.8
ns
2
5
—
5
—
5
—
ns
2
1
—
1
—
1
—
ns
tZZR
20
—
20
—
20
—
ns
tZZS
tZZH
No
t
Re
co
m
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.06 9/2008
18/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Pipeline Mode Timing (NBT)
Write A
Read B
Suspend
Read C
tKH
Write D
Suspend1
Write
Read E
Deselect
tKC
ct
tKL
n—
Di
sco
nt
inu
ed
Pr
od
u
CK
tH
tS
CKE
tH
tS
E
tH
tS
ADV
tH
tS
W
tH
tS
Bn
A0–An
A
B
C
D
DQ
Ne
w
tKQ
tH
tS
De
sig
tH
tS
Q(B)
tS
tKQX
tKQ
Q(C)
D(D)
tKQ
tLZ
tHZ
tKQX
Q(E)
No
t
Re
co
m
me
nd
ed
for
D(A)
E
Rev: 1.06 9/2008
19/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Flow Through Mode Timing (NBT)
Write A
Read B
Suspend
Read C
Write D1
Suspend1
Write
Read E
Deselect
tKL
tKC
ct
tKH
tH
tS
CKE
tH
tS
E
tH
tS
ADV
tH
tS
W
tH
tS
Bn
A0–An
A
B
C
D
tH
DQ
tKQ
Q(B)
Q(C)
tHZ
tKQX
tLZ
D(D)
Q(E)
No
t
Re
co
m
me
nd
ed
for
D(A)
E
tHZ
tKQX
Ne
w
tS
De
sig
tH
tS
n—
Di
sco
nt
inu
ed
Pr
od
u
CK
Rev: 1.06 9/2008
20/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
TQFP Package Drawing (Package T)
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity
θ
Lead Angle
n—
Di
sco
nt
inu
ed
Pr
od
u
Min. Nom. Max
e
b
A2
Y
De
sig
A1
0.10
0°
—
7°
E1
E
No
t
Re
co
m
me
nd
ed
for
Ne
w
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
D
D1
Description
c
Pin 1
Symbol
L1
θ
ct
L
Rev: 1.06 9/2008
BPR 1999.05.18
21/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
Ordering Information for GSI Synchronous Burst RAMs
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
1M x 18
GS8160Z18BT-250
NBT Pipeline/Flow Through
TQFP
250/5.5
C
1M x 18
GS8160Z18BT-200
NBT Pipeline/Flow Through
TQFP
200/6.5
C
1M x 18
GS8160Z18BT-150
NBT Pipeline/Flow Through
TQFP
150/7.5
C
512K x 36
GS8160Z36BT-250
NBT Pipeline/Flow Through
TQFP
250/5.5
C
512K x 36
GS8160Z36BT-200
NBT Pipeline/Flow Through
TQFP
200/6.5
C
512K x 36
GS8160Z36BT-150
NBT Pipeline/Flow Through
TQFP
150/7.5
C
1M x 18
GS8160Z18BT-250I
NBT Pipeline/Flow Through
TQFP
250/5.5
I
1M x 18
GS8160Z18BT-200I
NBT Pipeline/Flow Through
TQFP
200/6.5
I
1M x 18
GS8160Z18BT-150I
NBT Pipeline/Flow Through
TQFP
150/7.5
I
512K x 36
GS8160Z36BT-250I
NBT Pipeline/Flow Through
TQFP
250/5.5
I
512K x 36
GS8160Z36BT-200I
NBT Pipeline/Flow Through
TQFP
200/6.5
I
512K x 36
GS8160Z36BT-150I
NBT Pipeline/Flow Through
TQFP
150/7.5
I
1M x 18
GS8160Z18BGT-250
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
C
1M x 18
GS8160Z18BGT-200
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
C
1M x 18
GS8160Z18BGT-150
NBT Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
C
512K x 36
GS8160Z36BGT-250
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
C
512K x 36
GS8160Z36BGT-200
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
C
512K x 36
GS8160Z36BGT-150
NBT Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
C
1M x 18
GS8160Z18BGT-250I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
I
1M x 18
GS8160Z18BGT-200I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
1M x 18
GS8160Z18BGT-150I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
I
512K x 36
GS8160Z36BGT-250I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
I
512K x 36
GS8160Z36BGT-200I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
me
nd
ed
for
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Org
No
t
Re
co
m
512K x 36
GS8160Z36BGT-150I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160Z18B-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.06 9/2008
22/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
ct
8160ZxxB_r1
• Changed Under/overshoot to +1.5 V maximum and 50% tKC
Content
8160ZxxB_r_01;
8160ZxxB_r1_02
Content
8160ZxxB_r_02;
8160ZxxB_r1_03
Content
8160ZxxB_r_03;
8160ZxxB_r1_04
Content
• Removed 300 MHz speed bin
• Changed Pb-Free to RoHS-compliant
• Added Status column to Ordering Information table
8160ZxxB_r_04;
8160ZxxB_r1_05
Content
• Corrected pin description table
• Added missing Abs Max section
8160ZxxB_r_05;
8160ZxxB_r1_06
Content
n—
Di
sco
nt
inu
ed
Pr
od
u
8160ZxxB_r1;
8160ZxxB_r1_01
• Added 300 MHz speed bin
• Added Pb-free information
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
• Updated for MP status
Rev: 1.06 9/2008
23/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
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