Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays,

Circuit-Level Benchmarking of Access Devices for
Resistive Nonvolatile Memory Arrays
P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B. Kurdi
IBM Research – Almaden, 650 Harry Road, San Jose, CA 95120, Tel: (408) 927–2920, E-mail: [email protected]
Abstract
NVM Parameters
NVM Parameters
Access Devices (1AD) for crossbar resistive (1R) memories
are compared via circuit-level analysis. We show that in addition
to intrinsic properties, AD suitability for 1AD+1R memories is
strongly dependent upon (a) nonvolatile memory (NVM) and (b)
circuit parameters. We find that (1) building large arrays (≥1Mb)
with ≥10uA NVM current would require MIEC ADs and moderate NVM switching voltage (≤1.2V). (2) For all ADs high NVM
voltages (>2V) are supported only at sub-5uA currents. AD improvements to expand this design space are discussed.
Keywords: 1AD1R, Selector, Access Device, Nonvolatile memory
Partially (WL) Selected Cells
Selected Cell
Partially (BL) Seleccted Cells
((N-1) Unse
elect Rowss (Wordline
es)
VW
VR
VR
VR
VB
Fig. 1 Crossbar memory array with selected, partially (WL) selected, partially
(BL) selected and unselected 1AD+1R cells.
(VHRS , IHRS)
 RHRS
RHRS-PF
Vh
Series Resistance
R
it
(Rs)
10uA
1uA
100nA
Vm
1nA
100pA
10pA
‐3
‐2
‐1
0
1
2
3
Voltage[V]
Fig. 3 IV characteristics of Diode-type ADs (D-ADs): AD parameters –
Voltage Margin (Vm – voltage range for current≤10nA), turn-on slope S
(voltage for 10× current increase during AD turn-on) and series resistance Rs
are indicated.
Diode‐Type ADs
I(selected NVM)
(VLRS , ILRS)
INF
100uA
1 A
1pA
Simulation Framework
We use a generic NVM model (Fig.2) that transitions between
Low- and High-Resistance States (LRS, HRS – can be PooleFrenkel (PF) or Ohmic) as a function of applied voltage (default
(VHRS , IHRS)
1Mb
2.215Ω
parameters in Table 1). Inner voltages VC and VR for unselected
bitlines/wordlines are chosen for an aggregate unselect leakage
of 10uA (e.g. for 1Mb array, 10pA/device). Total array power
to force a worst-case selected NVM through HRS–to–LRS and
LRS–to–HRS transitions is estimated.
We consider 4 bipolar Diode-type ADs (D-ADs - MIEC [1],
Varistor [5], Metal-amorphous Si-Metal [3] and Silicon NPN [7]
- Fig.3). D-ADs are modeled as back-to-back diodes with a noise
floor (Fig. 2, top left inset). For all ADs, if IV data is not at
scale (∼32nm CD) or if only current-density data is available, we
estimate currents assuming constant current-density.
Voltage Margin (Vm – defined as voltage range over which
current≤10nA), Turn-on Slope (S ) and Series Resistance (Rs )
parameters are extracted (Table 2). High Vm provides a wide lowleakage zone to accomodate partial-select cells in large arrays. Low
S and Rs ensure low Voltage-across-AD (VAD ), and consequently
low total switching voltage (VSW ) to be applied at the edge of the
10nA
VC
(M-1) Unselect Columns (Bitlines)
Rseries
1.2V, 3uA
0.8V, 30uA
0 35V
0.35V
26.7kΩ, 400kΩ
10MΩ
Circuit Parameters Parameters
Array Size
N × M
Interconnect R/cell Rint
Currrent
Desirable AD properties for 3D resistive crossbar memories
(1AD+1R - Fig. 1) include BEOL compatibility, bipolar operation for RRAM/MRAM and large ON/OFF ratios to support high
ON- current density through selected cells with ultra-low leakage
in unselect and partial select cells. Beyond these basic properties, determining whether an AD is suitable for an NVM requires
circuit-level analyses that capture complex interactions between
AD, NVM and circuit parameters. We explore capabilities and
limitations of ADs in this design space by quantifying key figures
of merit such as total power consumption, maximum achievable
array size, and ranges of NVM voltages, currents supported.
VC
VHRS, IHRS
VLRS, ILRS
Vh
RLRS, RHRS
RHRS‐PF
Table. 1 Default NVM and Circuit Simulation parameters.
Introduction
VC
SET Switching
RESET Switching
Holding V (SET)
V (SET)
Resistance States
PF [email protected]
V(selected NVM)
(VLRS , ILRS)
Fig. 2 Generic NVM model for SPICE, with switching between an ohmic
LRS and an HRS exhibiting Poole-Frenkel conduction. Inset shows equivalent
circuit for SPICE modeling of bipolar diode-type ADs. Total array power to
write worst-case selected cell (Fig.1) must be estimated.
MaSiM
MIEC
NPN
Varistor
Vm(V) Slope(mV/dec)
19
1.9
454 333
454, 333
1.54
85, 85
2.56
219, 430
2.4
416, 282
416, 282
Rs(kΩ)
3 17
3, 17
2.8, 2.8
80, 70
19, 14
19, 14
Threshold Switching ADs
Vth (V), Ith (uA)
CTS
1 67 6 2
1.67, 6.2
TVS
1.37, 0.87
Vh
1.41
1
41
0
Ron
1
1.8
Table. 2 Default Access Device Simulation parameters – among D-ADs,
MIEC has the best turn-on slope and series resistance. Varistor and NPN have
better voltage margin but slope and/or series resistance are also significantly
higher and high voltages are required to drive high currents (Fig.3).
0.4
0.8
1.2
Partially (WL) Selected Cells
Selected Cell
VW
VP<10nA
VP>100nA!!
100nA
10nA
2.0
VAD
10uA
1uA
1.6
1/2Vm
VR
1nA
100pA
VUN
10 A
10pA
VC
1pA
VB
Fig. 4 MIEC, Varistor operating points for selected, unselected and partially
selected ADs under default NVM, circuit parameters. Large Varistor VAD
causes increased total switching voltage VSW , thereby causing high partial
select leakage. MIEC operating conditions are within manageable limits.
Currrent
I2+I1+INVM I1+INVM
VK,IIK
100uA
10 A
10uA
Fig. 7 Combining
all
unselect cells
into a single
aggregate
Diode+NVM
significantly
reduces number of nodes,
simplifying
circuit
analysis of
large scale
crossbar
arrays.
Partiallyy (BL) Sele
ected Cellss
Current
Voltage[V]
0.0
V2,II2
INVM
V1,II1
Vh
R
Ron
Rint
i t
Vxpt
+
Vinner
1uA
—
100nA
V1,I1
Vth, Ith 10nA
V2,II2
1nA
100pA
1pA
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Voltage[V]
Fig. 5 I–V characteristics of Threshold-switching ADs(T-ADs): Off-state current is modeled as a Poole-Frenkel characteristic. V th, Ith represents threshold switching condition of AD. Vh represents holding voltage after switching,
RON is threshold device ON-state resistance.
array to induce NVM switching (Fig.4, inset). AD operating points
under default NVM, circuit parameters are marked on MIEC and
Varistor DC IV curves in Fig.4.
Threshold switching ADs (T-ADs, e.g. Threshold Vacuum
Switch (TVS) [4] and Chalcogenide Threshold Switch (CTS) [6],
Fig. 5) can ‘snapback’ to low holding voltage above a current
threshold, thereby reducing VAD and VSW at NVM switching. This
may seem an ‘unfair’ advantage for T-ADs over D-ADs, especially
when Vh ∼0 (TVS). However, array design can still be constrained
by total switching voltage, power to induce AD thresholding as
opposed to NVM switching (Fig.6), and must be included in circuit
Ixptt
NVM SET Current NVM
SET Current
Threshold > AD Switching Threshold
Fig. 8 A hybrid circuit-simulation/analytical approach for analysis crossbar
array conditions – by iterating currents and voltages outwards from the selected
cell, one can estimate the voltage/current/power conditions at the edge of the
array to induce NVM switching.
100
Pow
wer [[milli-W
Watts]
10pA
Iterative Method
10
1
SPICE Full Circuit
Full
Circuit
0.1
VHRS 1 2V
VHRS = 1.2V
4Kb
16Kb
64Kb
SPICE Reduced
256Kb
1Mb
4Mb
Array Size
Fig. 9 Power consumption vs. Array size for 1MIEC+1NVM crossbar arrays:
plot shows near-identical correspondence between full-SPICE simulations and
approximate methods described in Figs. 7 and 8 for 2 different NVM VHRS
conditions.
analysis.
To evaluate ∼Mb arrays, number of circuit nodes is reduced
by replacing all unselect cells by a single aggregate device (Fig.7).
Given operating conditions at selected cell, iterating outwards can
determine voltage/current/power at the edge of the array to induce
switching (Fig. 8). Fig. 9 shows excellent agreement in power for
1MIEC+1NVM using iterative, reduced SPICE and full simulation.
Design Space Exploration of ADs
VXPT VXPT @SET @SET Start End
VXPT to Switch AD
Vxpt
Fig. 6 Maximum voltage required at selected cell, and consequently worstcase power consumption in the array, can occur at the threshold condition of
T-ADs (Fig. 5), as opposed to NVM switching conditions – illustrated in this
diagram, with a representative T-AD IV and varying load lines representing
instantaneous resistances of NVM.
Write power poses the most stringent constraint for 1AD+1R
designs [2]. Design points become unfavorable if total array power
far exceeds baseline power to switch AD+NVM. Fig. 10 plots a
color map of total power for MIEC+NVM arrays when varying
VHRS and array size. At favorable design points (blue) most of
the applied power is consumed at the selected cell; at unfavorable
1.89Mb
30
1.57Mb
1.26Mb
5mW
% Change
in VHRS
784Kb
576Kb
6 b
400Kb
256Kb
56 b
-50%
50%
from nominal
VHRS=1.2V
-30%
30%
-10%
10%
+10%
10%
+30%
30%
1mW
Arra
ay Size
e
1Mb
256Kb
MaSiM
NPN
16Kb
CTS
1.5
2
2.5
VHRS
3.0
[V]
Fig. 11 Write power consumption contours at 1mW vs. NVM VHRS and
array size demarcating favorable (left and down) and unfavorable (right and
up) design points for D-ADs and T-ADs. MIEC ADs can support array sizes
≥1Mb at moderate switching voltages. The star marks MIEC + nominal NVM
parameters.
64Kb
06
0.6
1.8
VHRS
2.0
[V]
50
40
Array Size = 256Kb
VLRS=2/3×VHRS
IHRS=0.1×ILRS
30
20
10
1
0.6
1
1.5
2
2.5
3.0
VHRS [V]
Fig. 14 At constant array size (256Kb), NVM switching voltage supported
trades-off against switching current. D-ADs follow their DC IV – linear segments are limited by series resistance: current trades-off in proportion to voltage, exponential segments indicate large increases in supported current for
small reduction in voltage.
50
Array Size = 1Mb
VLRS=2/3×VHRS
IHRS=0.1×ILRS
40
30
20
10
CTS
1
06
0.6
16Kb
4Kb
1.6
than what they can support.
Figs.14, 15 plot I vs. V design space for array sizes of 256Kb
and 1Mb, assuming VLRS =2/3VHRS and ILRS =10×IHRS . DADs follow their device I-V (e.g. Varistor contour). In linear
segments, D-ADs are limited by Rs – VAD trades off in proportion
to VHRS ; exponential segments show diode action (large change in
current for small change in voltage) which implies that lower NVM
switching voltage is an extremely important design consideration.
NPN follows a nearly linear contour, given high Rs . At lower ILRS ,
IHRS (10uA, 1uA - may be required for interconnect scaling), NPN
ADs can support 256Kb arrays with a relatively high VHRS of 2.5V.
Vm can be doubled by stacking two ADs in series; VHRS up
to 2.5V, and array size of 1Mb can be supported by double MIEC
(Fig.16). Stacking is not as effective on other D-ADs with poor S ,
Rs , since Vm benefits are offset by large increase in VAD .
At ILRS ≤10uA, TVS is constrained by NVM switching whereas
at higher currents, worst-case power occurs at Vth , Ith (Fig.17). If
AD switching is orders of magnitude faster than NVM, instantaneous power for AD threshold can be ignored and TVS ADs can
[uA]]
256Kb
1.4
Fig. 13 Increasing NVM non-linearity moderately improves voltage ranges
supported by certain ADs since partial select leakage can be reduced. Yet,
switching voltages ≥2V are not supported. NVM non-linearity also has no
impact on ADs that were already unsustainable at 1Mb in Fig.12.
ILLRS C
Curren
nt
1Mb
1.2
MIE
EC
A
Array
Size
VLRS=2/3×VHRS
1.0
TVS
S
16Mb
0.8
MIE
EC
points (red), partial select ADs allow significant sneak path currents
that can dominate power consumption.
Fig.11 shows 1mW power contours used to delineate favorable
(left, down) vs. unfavorable (top, right) regions for all ADs. The
graphs validate that AD suitability is coupled strongly to extrinsic
parameters - MIEC ADs can support array sizes up to 2Mb at lowto-moderate switching voltages≤1.2V, whereas Varistor is better
at VHRS ≥1.5V but only on much smaller arrays. No AD can
support high NVM switching voltage and large array sizes at default
current values. CTS can support only small arrays, since leakage
is relatively high, even at low bias. Contour ‘plateaus’ indicate
regions where array power is limited by constant VLRS ,ILRS . An
extreme case is NPN, which shows no dependence on VHRS –
high series resistance implies large VAD to deliver 30uA. Fig. 12
assumes VLRS scales as 2/3VHRS . Trends are similar, but MIEC
can support larger array sizes (4Mb) at low switching voltage, as
VAD reduces. Fig.13 shows that moderate increase in NVM voltage
supported is achieved with LRS non-linearity for MIEC, TVS and
Varistor. Other ADs do not appear since array size (1Mb) is larger
4Mb
NPN, MaSiM,
CTS
0.6
VLRS=0.8V
1
90
+50%
50%
4Mb
0.6
[email protected][email protected]
70
Fig. 10 Colormap of write power vs. VHRS and array size for MIEC ADs
from[2]: blue regions represent favorable design points with power consumption dominated by selected cell switching, red regions represent unfavorable
design points with extreme sneak path leakage through partial-select cells.
4Kb
Array Size: 1Mb
y
50 LRS Non‐Linearity= [uA]]
1Mb
64Kb
1
10
NV
VM LR
RS Non
n-Line
earity
≥10mW
Array size
ILLRS C
Curren
nt
2.25Mb
1
15
1.5
2
25
2.5
VHRS
30
3.0
[V]
Fig. 12 Varying VHRS and VLRS simultaneously removes ‘plateau’ contours
limited by constant VLRS assumption. Moderate expansion in supported
design space observed for MIEC and Varistor.
1
15
1.5
2
25
2.5
VHRS
30
3.0
[V]
Fig. 15 1mW contours for Write power showing range of Voltages and Currents
supported for an array size of 1Mb. MIEC ADs can support large arrays at high
currents and moderate switching voltage. NPN can support large switching
voltage at extremely low currents.
Array Size = 1Mb
VLRS=2/3×VHRS
IHRS 0 1×ILRS
IHRS=0.1×ILRS
40
1mW
Powe
er
[uA]]
ILLRS C
Curren
nt
50
30
20
100uW
10
CTS
1
0.6
1
1.5
2
2.5
3.0
VHRS [V]
ILLRS C
Curren
nt
[uA]]
Fig. 16 Voltage-current design space at 1Mb for a composite series stack of
two diode-like ADs: Significant gains are seen for MIEC, with a doubling in
NVM switching voltage supported at 1Mb array size. Diminished gains for
other D-ADs, given doubling in already large slope and series resistance values.
50
40
30
Constrained only by NVM conditions if
conditions if
tAD << tNVM
Constrained by AD transition
20
10
1
06
0.6
Constrained by NVM conditions
1
15
1.5
2
25
2.5
VHRS
30
3.0
[V]
Fig. 17 At currents>10uA, power consumption of TVS+1R arrays is constrained by T-AD threshold point. If AD switching time is much less than NVM
switching time, instantaneous power to switch AD can be ignored and larger
NVM voltages (2V for 1Mb arrays) supported.
support a much wider range of NVM V and I (2V at 1Mb in Fig.17).
These gains are enabled by low Vh – negligible VAD implies VSW
and consequently, power can be low. TVS design space can also
be expanded if Ith can be reduced (thereby reducing NVM voltage
at Ith ) while maintaining Vth (Fig.18).
ADs were also compared against low-current, non-linear, ‘selfselect’ RRAM [8]. While series AD increases VSW , this can be
offset by improved leakage mitigation on partial select cells – e.g.
in Fig.19 MIEC, NPN show >4× improved array size for the same
power, CTS shows degradation and TVS has little impact.
Conclusions
64Kb
256Kb
1Mb
4Mb
16Mb
Array Size
most suitable for larger switching voltages and low currents <5uA –
MIEC, TVS, Varistor can support low-current/high voltage NVMs
if supplemented by NVM non-linearity. Table 3 summarizes the
design space. Table 4 identifies key parameters to be improved for
the ADs studied.
256Kb
Low V, All, Low I CTS<5uA
512Kb
1Mb
2Mb
All, CTS<5uA
All except CTS
MIEC, NPN, Varistor
(MaSiM, (MaSiM
[email protected])
MIEC
Low V, V TVS
TVS, MIEC, MIEC TVS, MIEC
TVS MIEC TVS, MIEC
TVS MIEC
High I Varistor
Varistor
High V, High
V [email protected],
[email protected]
[email protected]
[email protected],
NPN<5uA, [email protected], NPN<5uA
[email protected]
Low I [email protected] [email protected] others+ MIEC, non‐linear
non
linear Varistor non
non‐
NVM
linear NVM
High V,
High
V, None
High I
None
None
None
Table. 3 Design Space Summary
Diode Type ADs
Diode‐Type
MaSiM
MIEC
NPN
Varistor
Voltage Margin, Slope
Voltage Margin
S ope, Se es es sta ce
Slope, Series Resistance
Slope
Th h ld AD
Threshold ADs
40
CTS
TVS
20
0.1X
30
Low‐bias leakage, Ith
Ith
Table. 4 AD improvements to expand supported design space
References
10
1
06
0.6
16Kb
Fig. 19 Integrating D-ADs with low ON-current, high non-linearity NVMs [8]
can enable ≥ 4× increase in array size vs. a selector-less array. TVS devices
do not show any benefit with this NVM, as switching threshold of the AD is
higher than the NVM.
50
0.2X
0
ILLRS C
Curren
nt
[uA]]
AD suitability was shown to be dependent upon AD, NVM and
circuit parameters. MIEC ADs were shown to be the best choice
for NVMs with low-to-moderate switching voltages. NPN ADs are
10uW
4Kb
1
15
1.5
2
25
2.5
VHRS
30
3.0
[V]
Fig. 18 TVS design space can also be expanded if threshold current can
be reduced while maintaining threshold voltage. This considerably reduces
voltage across NVM at AD threshold, thereby reducing total crosspoint voltage
needed (refer Fig.6).
[1] K. Virwani et al., IEDM Tech. Digest, 2.7 (2012).
[2] P. Narayanan et al., DRC, V.A-5 (2014).
[3] L. Zhang et al., IEEE EDL, 35(2) 2014).
[4] C-H. Ho et al. IEDM Tech. Digest, 2.8 (2012).
[5] J. Woo et al. VLSI Tech. Digest, 12-4 (2013).
[6] M-J. Lee et al. IEDM Tech. Digest, 2.6 (2012).
[7] V.S.S. Srinivasan et al. IEEE EDL, 33(10) (2012).
[8] S-G. Park et al., IEDM Tech. Digest, 20.8 (2012).
[9] ITRS Interconnect Tables (2011).
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