Exploring the Design Space for Resistive Nonvolatile Memory Crossbar Arrays with Mixed Ionic-Electronic-Conduction (MIEC)–based Access Devices P. Narayanan, G. W. Burr, R. S. Shenoy, S. Stephens, K. Virwani, A. Padilla, B. Kurdi, and K. Gopalakrishnan‡ IBM Research – Almaden, 650 Harry Road, San Jose, CA 95120 (‡ IBM T. J. Watson Research Center, Yorktown Heights, NY 10598) Tel: (408) 927–2920, Fax: (408) 927–2100, E-mail: [email protected] Abstract Using circuit-level SPICE simulations, we explore the design constraints on crossbar arrays composed of a nonvolatile memory (NVM) (+1R) and a highly nonlinear Access Device (AD) enabled by Cu-containing Mixed Ionic-Electronic Conduction (MIEC) materials [1-5]. Such ADs must maintain ultra-low leakage through a large number of unselected and partially selected 1AD+1R cells, while delivering high currents to the few cells selected for either read or write. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays, with NVM switching voltage VN V M and selector voltage margin Vm being much more critical than write current. We show that scaled MIEC devices (Vm ∼ 1.54V [4]) can support 1Mb arrays for VN V M up to 1.2V. Stacking two MIEC devices enables VN V M ∼ 2.4V . A 20% improvement in Vm can either enable a 4× increase in array size or counteract a 5× increase in interconnect line resistance. Keywords: Access device, MIEC, crossbar array, NVM selectors Introduction MIEC-based ADs [1–5] exhibit ideal characteristics for 3Dstacking of large crossbar arrays of any resistive NVM in the BEOL, including bipolar diode-like characteristics (Fig.1), large ON/OFF ratios, high voltage margin Vm (for which leakage stays below 10 nA), ultra-low leakage (< 10 pA), and high ON current densities. Even with such attractive characteristics, however, the design of a large crossbar array of 1AD+1R devices (Fig. 2) — within which writes and reads must be reliable yet leakage through non-selected devices low — requires careful choice of selected & unselected wordline (VW & VR ) and bitline (VB & VC ) voltages. We quantify the design-space enabled by scaled MIEC-based ADs (Vm ∼ 1.54V [4]) in terms of achievable array size, excess required power during write, and read margin. Simulation framework We assume an NVM device that transitions between an ohmic Low Resistance State (LRS) and a High Resistance State (HRS) exhibiting Poole-Frenkel (PF) conduction (Fig. 3). The equivalent circuit for the MIEC AD (Fig. 3, inset) is carefully fit to experimental data (Fig. 1). Before each SPICE simulation, the inner voltages VC , VR (Fig.4(b)) are chosen for an aggregate unselected leakage of 10uA (e.g., for a 1Mb array, 10pA/device). As outer voltages VB , VW are swept apart, the voltage across the worst-case selected 1AD+1R device(s) (Fig. 4(a)) increases. After the simulation completes, the NVM switching event (Fig. 5) identifies the external voltages (VB , VW ) required for a successful write. Default NVM, MIEC AD, and array parameters are shown in Table.1. Total required power is examined just before and just after switching for both the LRS-to-HRS and HRS-to-LRS transitions. Design space for NVM write In our approach, only voltage choices which trigger a successful write are even considered. A design point becomes unfavorable when the total applied power becomes much larger than the base 1AD+1R write power. For instance, even a 10% increase in VHRS causes applied power to increase by two orders of magnitude (Fig. 6). This extra applied voltage at the far-edge selected device (Fig. 4(a)) exponentially increases leakage in nearby half-selected devices (Fig.4(b)). The resulting larger voltage drops in the wiring then exacerbate voltage stress at near-edge half-selected devices. While this positive feedback effect is roughly the same for the worst-case (all LRS) and for random stored data patterns, it can be suppressed by the high resistance of the HRS state (Fig. 6, inset). Like VHRS , there is a VLRS threshold, beyond which write power grows dramatically. However, the array design is quite robust to increases in switching currents IHRS , ILRS (Fig.6). Fig.7 shows that small increases in VHRS dramatically reduce achievable array size. When the design works (blue region at left), almost all the externally applied power reaches the selected device, opening up opportunities for parallel writes; when the design fails, almost all external power is dissipated in half-selected 1AD+1R devices. Figs. 8 and 9 show that, similar to NVM voltage VHRS , maintaining a sufficiently large AD voltage margin Vm is critical to successful array design. Degradations in AD slope S lead to excess power (Fig.8), yet can be offset by Vm improvements (Fig.9). For a given NVM, improvements in either the slope S or the voltage margin Vm of the MIEC-based AD can enable significant increases in the achievable array size (Fig. 10), or can be used to accommodate the increases in line resistances expected at scaled technology nodes (Fig. 11). Fig. 12 shows the achievable array size for both the scaled MIEC AD (Vm ∼ 1.54V) and a stacked combination of two MIEC ADs. The larger voltage margin far outweighs the degradation in AD slope and series resistance, allowing a stacked MIEC diode to support 1Mb arrays for NVM switching voltages as large as 2.4V. Note that large SPICE simulations are enabled by modeling all unselected 1AD+1R device pairs with a single aggregate device (Fig.13). Design space for NVM read Read margin is the change in voltage across a peripheral load resistor RLOAD (Fig.13) when the selected device moves between the HRS and LRS states. The applied read voltage is determined based on avoiding a disturb (Fig. 13(A)) on the near-edge cell, the two reads are performed with a true V/2 scheme and data patterns shown in Fig.13(B,C)) (other schemes/patterns showed similar performance, not shown). The load resistance is chosen to increase read margin (Fig. 14, inset) without excessive RC timing issues. While read margin degrades with lower read voltage/disturb condition (Fig. 14), and higher interconnect resistance (Fig. 15, inset), NVM resistance contrast has the most significant impact (Fig. 15). Read margin does depend upon AD parameters (Fig.16), but write power considerations are clearly far more stringent (Figs.8,9). Conclusions We have explored the design of 1AD+1R crossbar arrays using highly nonlinear Access Devices (AD) based on Mixed IonicElectronic Conduction (MIEC) [1-5]. Circuit-level SPICE simulations were used to show that achievable array size and excess required power during write depends strongly on careful matching between the turn-on voltage Vm of the AD and the switching voltage VN V M of the NVM. This implies that research in this field should be directed towards NVMs with lower VN V M (and ADs with higher Vm ), as opposed to decreases in raw NVM switching current. Scaled MIEC devices (Vm ∼ 1.54V [4]) are shown to support VN V M up to 1.2V (for 1Mb arrays), and two stacked MIEC devices enable VN V M ∼ 2.4V . References [1] K. Gopalakrishnan et. al., VLSI Tech. Symp., 19.4 (2010). [2] R. S. Shenoy et. al., VLSI Tech. Symp., 5B.1 (2011). [3] G. W. Burr et. al., VLSI Tech. Symp., T5.4 (2012). [4] K. Virwani et. al., IEDM Tech. Digest, 2.7 (2012). [5] G. W. Burr et. al., VLSI Tech. Symp., T6.4 (2013). [6] ITRS 2011 Interconnect tables (www.itrs.net). Partially (WL) Selected Cells DC IV 10pA 1pA -1.5 -1.0 -0.5 0 0.5 1.0 1.5 Voltage [V] VR SET Switching RESET Switching Holding V during SET Read Disturb Voltage Resistance States PF HRS @ 0.1V NVM “SET” snapback Current 1uA LRS HRS Selected device Half-selected Half selected devices 10nA Un-selected devices 100pA 1pA 0.5 1.0 1.5 2.0 Vh VDIS RLRS , RHRS RHRS−P F 1.2V, 3µA 0.8V, 30µA 0.5V 0.25×VHRS 26.67kΩ, 400kΩ 10MΩ 1.89Mb 1.57Mb 1.26Mb 5mW 1Mb % Change in VHRS 784Kb 576Kb 6 b 400Kb 256Kb 56 b -50% 50% from nominal VHRS=1.2V -30% 30% -10% 10% +10% 10% +30% 30% +50% 50% VB drop across wiring + Voltage drop across NVM VR VC VW S Rs IN F Fig. 4 Total applied voltage at switching is a) NVM voltage VN V M + AD voltage + wiring IR-drop, identified by b) sweeping select-lines VW and VB at fixed unselect bias (and leakage). VHRS ((1.2V)) VLRS (0.8V) ILRS (30uA) 1 IHRS (3uA) 0.1 -50% -30% -10% +10% +30% +50% % Change in Individual Parameters +50% Vm (1.54V) +40% Fig. 6 Switching voltages (VHRS , VLRS ) are much more critical to low power 1AD+1R crossbar design than switching currents (IHRS , ILRS ). Inset: impact of data patterns. ≥10mW % Change in S from nominal +30% S = 85mV/dec S (85mV/dec) 1 +20% +10% 0 5mW -10% 10% Rs (2850Ω) -20% -30% 30% 0.1 1mW b) 10 1.54V 85mV/dec 2850Ω 3pA Vm 10 Pow wer [m milli-W Watts] ≥10mW Array size …+ (VLRS , ILRS) Fig. 5 Cell currents vs. total applied voltage Array Size N ×M 1Mb (1024×1024) for the HRS-to-LRS (“SET”) operation on a Interconnect R/cell[6] Rint 2.215Ω 64×64 array, exhibiting NVM transition. Table. 1 Default simulation parameters. 2.25Mb V(selected NVM) Vh Fig. 3 Generic NVM model for SPICE, with switching between an ohmic LRS and an HRS exhibiting Poole-Frenkel conduction. Inset shows equivalent circuit for SPICE modeling of the bipolar, highly non-linear MIEC AD. VHRS , IHRS VLRS , ILRS Voltage Margin Turn-on Slope V lt Voltage [V] Series Resistance 2.5 3.0 3.5 Noise Floor RHRS-PF (VHRS , IHRS) Fig. 1 Scaled MIEC access deVR vices exhibit voltage margins Vm (at 10nA) of ∼1.54V, ON-OFF conVC VC VC VB trast in excess of 107 and ultra-low (M-1) Unselect Columns (Bitlines) leakage at low bias [1-5], suitable Fig. 2 Crossbar array with selected, parfor large arrays with many unse- tially (WL) selected, partially (BL) selected devices. lected, and unselected 1AD+1R cells. 100uA (VHRS , IHRS) RHRS INF Log I VR Total Voltage to Switch NVM Voltage drop across AD Log I 100pA Vm~1.53V 1.53V Slope S ~ 85mV/dec a) I(selected NVM) (VLRS , ILRS) Pow wer [m milli-W Watts] 10nA Rseries Partially (BL) Seleccted Cells Currrent [uA] (300ns) 1uA 100nA ((N-1) Unse elect Rowss (Wordline es) pulsed IV 10uA 1nA Selected Cell VW 100uA % Change in Vm -40% -50% -30% -10% +10% +30% +50% from nominal -50% 50% -50% 1mW Vm = 1.54V +10% Vm Vm (1.54V) S 60mV/dec 1 +20% Vm 0.1 10 Power [milli-W Watts] Pow wer [m milli-W Watts] 10 +10% Vm (1.54V) (1 54V) 1 1Mb b 1.57Mb b 2.25Mb 22 b 3 3.14Mb b 16Mb 4Mb 1Mb 256Kb S 60mV/dec +20% Vm 01 0.1 2 6 b 256Kb Vm Ma aximu um Arrray S Size -30% -10% +10% +30% +50% Fig. 7 Write power vs. VHRS and array size: small % Change in Individual Parameters changes in VHRS dramatically reduce achievable ar- Fig. 8 Voltage margin V (at 10nA) is the most Fig. 9 Write power as a function of voltage margin Vm m and AD slope S. ray size. critical AD parameter in 1AD+1R crossbar Design. (Vm 3.08V, S 170mV/dec) 64Kb Full SPICE model 16Kb Approximate, iterative model 4Kb 0.72 4Mb b Stacked MIEC MIEC (Vm 1.54V, S 85mV/dec) 0.96 1.20 1.44 1.68 1.92 2.16 2.40 NVM Switching Voltage [V] (2.215 Ω/cell) Change in Line Resistance Fig. 12 Maximum achievable array size vs. VN V M . For two Fig. 10 Any improvement in AD parameters Fig. 11 Alternatively, improved AD parameters stacked MIEC ADs, V improvement outweighs degradation m permits significantly larger size arrays. can be used to accommodate the higher line resis- in turn-on slope and series resistance. A simple model, iterating tances of scaled technology nodes. out from the selected device, is close to SPICE in accuracy. Partially (WL) Selected Cells Selected Cell HRS HRS VR B. Read HRS C. Read LRS LRS HRS LRS LRS LRS LRS HRS HRS VC RLOAD VREAD VB = -V VA/2 Fig. 13 One aggregate 1AD+1R can model the combined leakage of all unselected crosspoints; read operation adds RLOAD at array periphery. Insets show assumed patterns of stored data. 150 RHRS (400kΩ) -50% RLRS (26.67kΩ) 180 160 140 120 100 80 60 50 0 6X 180 VDIS (0.3V) 200 100 5X [mV] HRS Partiallyy (BL) Sele ected Cellss HRS Re ead M Marg gin [m mV] 250 A. Worst-case Read Disturb 4X Rea ad Marrgin [m mV] VW = VA/2 3X Rea ad Ma argin Array Size 2X 1X % Change in Individual Parameters -30% -10% +10% +30% +50% Fig. 14 Sensitivity of read margin to VDIS , RHRS and RLRS . Inset: Read margin is maximized when RLOAD approaches RHRS−P F . Default value of √ RLOAD = RLRS RHRS ∼ 103kΩ. 40 15X 12X 9X 6X 3X 1.5X S (85mV/dec) 160 140 Vm (1.54V) 120 100 Resistance Contrast 80 -50% % Change in Individual Parameters Fig. 15 Read margin deteriorates sig-30% -10% +10% +30% +50% nificantly with loss of resistance contrast Fig. 16 The impact of V and S changes m (LRS resistance approaches ohmic HRS), on read margin is significantly less critiand (inset) decreases linearly as intercon- cal than their write power impact (Fig.8). nect resistance increases.