Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint-Memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials,

5B-1
Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint-Memory
based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials
R. S. Shenoy, K. Gopalakrishnan, B. Jackson, K. Virwani, G. W. Burr, C. T. Rettner,
A. Padilla, D. S. Bethune, R. M. Shelby, A. J. Kellock, M. Breitwisch† , E. A. Joseph† , R. Dasaka† ,
R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi
IBM Almaden Research Center, 650 Harry Road, San Jose, CA 95120 († IBM T. J. Watson Research Center, Yorktown Heights, NY 10598)
Tel: (408) 927{–2362, –3721}, Fax: (408) 927–2100, E-mail: {rsshenoy, [email protected]
Abstract
We demonstrate compact integrated arrays of BEOL-friendly
novel access devices (AD) based on Cu-containing MIEC materials[1-3]. In addition to the high current densities and large ON/OFF
ratios needed for Phase Change Memory (PCM), scaled-down ADs
also exhibit larger voltage margin Vm , ultra-low leakage (<10pA),
and much higher endurance (>108 ) at high current densities. Using
CMP, all–good 5×10 AD arrays with Vm > 1.1V are demonstrated
in a simplified CMOS-compatible diode-in-via (DIV) process.
Keywords: Access device, MIEC, PCM, NVM, MRAM, RRAM
Introduction
For PCM or any other nonvolatile memory (NVM) to be as
cost-effective as NAND FLASH (≤4F2 /3), 3D-stacking of large
crosspoint arrays in the BEOL is essential [4-5]. MIEC materials
offer the requisite high ON current densities, low OFF current, and
<400◦ processing temperatures[1]. However, large arrays mandate
a wide voltage margin (to avoid excessive leakage through both
half– and un-selected devices), and the AD characteristics must not
degrade during memory operation, even as PCM current densities
steadily increase with scaling (Fig.1)[1,6].
MIEC device fabrication and characteristics
In the first of three prototype AD designs that have been fabricated (Fig. 2(a)), our Cu-containing MIEC material and a nonionizable, wide-area TEC ( BEC) are sputter-deposited into an
e-beam-defined via. In the second (Fig.2(b)), the TEC is patterned
with e-beam and ion-milling, which enables bipolar operation (inset). For both wide-area- and confined-TEC ADs, a polysilicon
resistor allows current measurement during high-speed pulsing.
Fig. 3 shows cycling of a PCM pore device through an overlying
confined–TEC AD. The 33nm pore-cell PCM, not just near the
AD [1] but immediately beneath it, was successfully cycled with
>104 high-current pulses, with no AD degradation.
Novel ADs were also fabricated on 8” wafers containing arrays
of 180nm FETs, using sputter-deposition of MIEC material into
tapered vias followed by an optimized CMP process (Fig. 2(c)).
Fig.4(a) shows a top-down view of the metal- and MIEC-vias for a
5×10 array, after CMP; Fig.4(b) shows a cross–section of a finished
Diode-In-Via (DIV) AD, with planarized MIEC material capped
by the TEC. Such device arrays, tested using the integrated FETs,
repeatedly exhibit 100% yield (Fig.5), with tightly-distributed voltage margins Vm ∼ 1.1V (as measured at 10nA).
These MIEC-based ADs offer the highly-desirable combination of high ON current and very low OFF-current. In fact, Fig. 6
shows that the lowest currents in Figs. 3 and 5 are inflated by the
noise inherent in rapid measurements; leakage currents near zero
bias are in fact ultra-low (<10pA), even for large CDs.
MIEC device endurance
At low-current (< 10 µA), these favorable AD characteristics
persist for 1010 switching cycles [1]. At high currents, Vm degrades slowly and then eventually falls abruptly as the AD becomes
nearly-shorted (Fig.7). The effects of device (MIEC thickness and
CD) and electrical (currents and pulse-width) parameters on endurance have been investigated.
MIEC-based ADs with two significantly different BEC CDs
show identical dependence of endurance on pulse-current (Fig.8),
despite the nearly 3-fold difference in current density J . This
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978-4-86348-164-0
suggests that endurance failure arises from Cu-ions, displaced from
their original lattice sites in quantities proportional to total current
but not to J , that slowly accumulate within the cycled AD. This
strong dependence of endurance on current is observed across
ADs with different structures and MIEC-thicknesses (Fig.9). The
improved endurance for thinner ADs and the CD independence
bode extremely well for PCM scaling: as PCM devices shrink,
the AD will pass less current and can be made thinner, so that
AD endurance can be expected to rise (beyond even the 108 cycles
shown here) despite the higher current densities. While long pulses
impact AD endurance (Fig. 10) with a linear (1:1) dependence
suggestive of an electromigration-like failure mode, short pulses
consistent with PCM and other NVM candidates are beneficial.
Cross-sectional TEM analysis of heavily-cycled ADs reveal
noticeable changes in local stoichiometry (Fig. 11). The observed
accumulation of Cu near the TEC (biased negative during cycling)
presumably occurs more slowly with current and thickness reductions, as the number of displaced ions drops. Encouragingly, arrays
of DIV ADs damaged by excessive cycling can be recovered with
a simple thermal anneal (Fig.12(a)); initial results with single DIV
ADs, partially degraded by high-currents of one polarity, show similar recovery upon brief exposure to high current in the opposite
direction (Fig.12(b)).
Scaling, new materials and voltage margin
Voltage margin Vm must be high to enable large arrays of crosspoint memory devices[1]. Fig.13 reaffirms[1] that as MIEC-based
ADs are scaled in TEC area (and thus in MIEC volume), the Vm of
confined ADs increases markedly. DIV access devices fabricated
with CMP show even higher voltage margins (1.1V), and extend
a universal trend of Vm with TEC CD (Fig. 13). This strong dependency, together with Conductive-AFM (C-AFM) observations
on MIEC thin films that Vm is independent of thickness down to
20 nm, indicates that the AD scaling called for by Fig. 1 will inherently improve Vm . New materials have also been explored with
C-AFM to further improve the voltage margins (Fig.14).
Conclusions
We have demonstrated compact integrated arrays of BEOLfriendly novel access devices (AD) based on MIEC materials. Significant improvement in the endurance was achieved through reductions in film thicknesses and currents. Endurance was also shown
to be CD-independent, leading to > 108 cycles of endurance for
currents corresponding to PCM programming at sub-45 nm technology nodes. Using a simple 1-mask BEOL-compatible CMP
process, all-good 5×10 AD arrays with Vm > 1.1V and ultra-low
leakages were demonstrated. Sizeable further Vm improvements
are anticipated from device scaling and new materials.
Acknowledgements
Expert analytical and processing support from D. Pearson, N.
Arellano, E. Delenia, and L. Krupp is gratefully acknowledged.
References
[1] K. Gopalakrishnan, VLSI 2010, T19-4 (2010).
[2] I. Yokota, J. Phys. Soc. Japan, 8(5), 595 (1953).
[3] I. Riess, Solid State Ionics, 157, 1 (2003).
[4] Y. Sasago, VLSI 2009, T2B-1 (2009).
[5] D. C. Kau, IEDM 2009, 27.1 (2009).
[6] Int’l Technology Roadmap for Semiconductors, www.itrs.net (2008).
[7] A. Padilla, IEDM 2010, 29.4 (2010).
2011 Symposium on VLSI Technology Digest of Technical Papers
28
20
14
200uA
10
8
a)
[nm]
5
AD current
density
20
IBM PCM
pore devices
ITRS
MIEC
10
aggressive
100uA
65
45
32
22
16
(PCM CD = 0.5F)
20uA
12
65
45
32
22
16
12
1mA
100uA
10uA
1uA
100nA
10nA
1nA
100pA
10pA
Current
100nA
10nA
100pA
AD
AD TEC
Pulses
100
poly-Si
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
10nA
Single device, rapid
(Average of 20 measurements
at 160sec integration)
1nA
100uA
1uA
100pA
Wide-area TEC, 80nm BEC
100pA
-0.4V
(20x 16ms integration)
1pA
Single device
20 devices
25 devices
45 devices
Voltage [V]
100fA
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
22 32
40
45 65
0.3
0.4
-0.2V
Vb
Endurance
40nm
50nm
70nm
70nm
1e6
1e3
180nm TEC, 80nm BEC,
145nm thick MIEC
100
1uA
100k
Pulses
1e6
-0.6
-0.4
-0.2
Current
10nA
100pA
1e7
1e8
Endurance
1e6
nominal
40nm ILD
40nm ILD
20nm ILD
40nm ILD
1e9
1.0V
0.8V
0.6V
0.4V
0.2V
0V
50
100
150
200
185nm TEC, 95nm BEC,
115nm thick MIEC
250
300
350
Current
50
a)
1uA
b)
Initial
degraded by cycling
recovered
by anneal
10
0
-0.6 -0.4 -0.2
100nA
0
0.2
TEC
voltage
0.4
0.6
(wide-area TECs)
1e5
pulse
leakage
Vm
100
-Vb
1e4
failure criteria: 200mV shift (18% Vm )
1k
Va
10k
Pulses
100k
47 nm BEC
80 nm BEC
1e6
1e6
1e7
Current [uA]
1e3
100
200
300
400
Fig. 8 MIEC-based AD endurance
depends on current, but is independent of BEC CD, despite the nearly
3-fold change in current density.
Wide-area TEC ADs with
70nm-thick MIEC in 40nm ILD,
cycled negative on TEC
a)
1e4
95nm BEC
DIV AD, cycled
positive on
b)
Cu-poor
nominal
Cu-rich
Fig. 11 Local stoichiometry from TEM/EELS of widearea TEC, 80nm BEC ADs a) as-fabricated, and b) after
100ns
1us
10us
100us
1ms
Fig. 10 For both wide-area TEC and DIV ADs, 425,000 cycles at 325µA. Regions near the TEC (biased
endurance improves as pulse duration is reduced. negative for cycling) have become markedly Cu-rich.
Pulse Duration
400
1.2
After repeated
high-current,
negative-on-TEC
pulses
1.1
185nm TEC
Vm [V]
1
10nA
Current
POR
MIEC
[a.u.]
material
40nm BEC
0.9
80nm
BEC
0.8
1nA
TEC
Material
voltage 0.7
0.2 0.4 0.6 100pA
TEC voltage for 10nA leakage [V]
0
Endurance
1e7
40nm BEC
80nm BEC, < 200uA
80nm BEC, > 300uA
Current [uA]
Fig. 9 ADs show better endurance as the thickness,
and thus the volume from which Cu+ is accumulated
during cycling (see Fig.11) , becomes smaller.
Number of devices
100uA
DIV: 185nm TEC, 95nm BEC
1e5
DIV ADs, cycled
positive on TEC
1e4
20
1nA
Fig. 7 Both a) wide-area TEC and b) DIV MIEC-based ADs
can operate without degradation for many high-current pulses, but
eventually a change from low- to high-leakage occurs. This change
is abrupt in all but the thickest ADs.
1e5
30
0
failure criteria: 100mV shift (16% Vm )
10k
0.5
in
in
in
in
-0.1
pulse
(left half of Vm )
0V
80nm BEC ADs, cycled
negative on Wide-area TEC
MIEC thickness:
1e7
40
-0.2
1uA
100nA
10nA
1nA
100pA
leakage
F (PCM RESET current)
1e8
10
-0.3
Current
Fig. 6 Slow measurements, performed on single
or multiple all–good devices, reveal that leakage
currents in MIEC-based ADs near 0V are <10pA.
1e9
TEC voltage [V]
-0.4
10nA
Slow measurements
10pA
-0.5
0
0.5
1.0
TEC voltage for 10nA leakage
Fig. 4
a) Top-down view of metal- and
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
MIEC-vias for a 5×10 array (w/ dummy
TEC voltage [V]
rows/columns), after CMP; (b) TEM cross– Fig. 5 Measured i-v characteristics for a 5×10 array of
section of a Diode-In-Via (DIV) AD, with pla- DIV ADs, tested with integrated FETs, showing large
narized MIEC material capped by the TEC.
voltage margin (Vm ∼ 1.1V) and tight distributions.
Current
Current [per device]
1uA
100nA
10nA
1nA
100pA
Diode-in-Via (TEC: 180nm, BEC: 80nm)
0
-1.0
100pA
1
Fig. 3 Cycling of a 33nm pore-cell PCM, with SET,
RESET, and read performed through an overlying AD
(80nm BEC), which showed no degradation despite the
> 104 high-current pulses. The 200nm TEC allowed
“good polarity” (positive-on-TEC) PCM operation[7].
100nA
10
BEC
TEC
voltage [V]
GST
33 nm
Vm = 1.1V
25
10nA
80nm
PCM TEC = AD BEC
40
100nA
MIEC
80 nm MIEC
50
80 nm BEC / 180 nm TEC
1uA
180nm
200 nm
TiN
10pA
Current
TEC
10k
1k
via
ILD
b)
>10x
RESET
RESET
PCM
1nA
SET
a)
SET
Current
FET
Fig. 2 MIEC-based ADs with non-ionizable electrodes are fabricated on 4” wafers with a) widearea TECs ( BEC), b) TECs patterned to enable bipolar operation (inset) with ion-milling,
and c) on 8” wafers with integrated FETs using Chemical-Mechanical Polishing (CMP).
8
Fig. 1 PCM requires large Access Device (AD) current densities, yet absolute RESET current will decrease with scaling.
1uA
ILD
BEC
via
BEC
poly-Si
Technology node F [nm]
10uA
via
MIEC
ITRS
roadmap
MIEC
TEC
b)
8
TEC
M1
ILD
BEC
poly-Si
Technology node F [nm]
5
w/ aggressive
PCM scaling
40uA
c)
TEC
[MA/cm2]
Current
PCM RESET current
400uA
Number of devices
PCM CD: 41
-0.5V
0V
0.5V
Fig. 12 Low-leakage i-v characteristics that have been degraded by endurance failure or high-current pulses can be
recovered by either a) thermal annealing, or b) high-current
pulses of the opposite polarity. This implies that local accumulations of Cu shown in Fig.11 can be successfully redistributed.
0.6
0.5
100nm
TEC CD
1um
C
Material
B
Tip bias [a.u.]
10um
Fig. 13 Wide-area-TEC, confined-TEC, and
DIV ADs exhibit a common trend: Vm increases sharply as TEC CD is scaled down.
Fig. 14 Conductive-AFM measurements (small-area
tip on various MIEC materials on unpatterned BEC)
provide early guidance on the Vm (but not on leakage
current) to be expected from wide-area TEC ADs.
2011 Symposium on VLSI Technology Digest of Technical Papers
95
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