A3982 Datasheet

A3982
DMOS Stepper Motor Driver with Translator
Features and Benefits
Description
▪ Low RDS(on) outputs
▪ Automatic current decay mode detection/selection
▪ Mixed and Slow current decay modes
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
The A3982 is a complete stepper motor driver with builtin translator for easy operation. It is designed to operate
bipolar stepper motors in full- and half-step modes, with an
output drive capacity of up to 35 V and ±2 A. The A3982
includes a fixed off-time current regulator which has the
ability to operate in Slow or Mixed decay modes.
The translator is the key to the easy implementation of the
A3982. Simply inputting one pulse on the STEP input drives
the motor one step. There are no phase sequence tables, high
frequency control lines, or complex interfaces to program.
The A3982 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A3982 automatically selects
the current decay mode (Slow or Mixed). When a signal
occurs at the STEP input pin, the A3982 determines if
that step results in a higher or lower current in each of the
motor phases. If the change is to a higher current, then the
decay mode is set to Slow decay. If the change is to a lower
current, then the current decay is set to Mixed (set initially
to a fast decay for a period amounting to 31.25% of the
Package: 24 pin SOICW with internally
fused leads (suffix LB)
Continued on the next page…
Not to scale
Pin-out Diagram
OUT2A
1
24 OUT1A
SENSE2
2
23 SENSE1
22 VBB1
4
21 OUT1B
ENABLE
5
20 DIR
PGND
6
PGND
7
CP1
8
CP2
9
MS1 12
26184.28C
19 PGND
18 PGND
17 REF
16 STEP
15 VDD
OSC
VREG 11
Reg
VCP 10
Translator
& Control Logic
3
Charge
Pump
VBB2
OUT2B
14 ROSC
13 RESET
A3982
DMOS Stepper Motor Driver with Translator
Description (continued)
fixed off-time, then to a slow decay for the remainder of the
off-time). This current decay control scheme results in reduced
audible motor noise, increased step accuracy, and reduced power
dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with
hysteresis, undervoltage lockout (UVLO), and crossover-current
protection. Special power-on sequencing is not required.
The A3982 is supplied in a 24-pin wide-body SOIC
(package LB) with internally-fused power ground leads for
enhanced thermal dissipation. It is lead (Pb) free, with 100%
matte tin plated leadframe.
Selection Guide
Part Number
Packing*
A3982SLB-T
31 pieces per tube
A3982SLBTR-T
1000 pieces per reel
Package
24-pin Wide SOIC with pins 6 and 7, and 18
and 19, fused internally
*Contact Allegro for additional packing options
Absolute Maximum Ratings
Rating
Units
Load Supply Voltage
Characteristic
VBB
35
V
Logic Input Voltage
VIN
–0.3 to 7
V
Sense Voltage
Symbol
Notes
VSENSE
0.5
V
Reference Voltage
VREF
4
V
Output Current
IOUT
±2
A
–20 to 85
ºC
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
Range S
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
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A3982
DMOS Stepper Motor Driver with Translator
Functional Block Diagram
0.1 μF
0.22 μF
VREG
VDD
Current
Regulator
ROSC
CP1
CP2
Charge
Pump
OSC
VCP
0.1 μF
REF
DMOS Full Bridge
DAC
VBB1
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
STEP
DIR
RESET
SENSE1
Gate
Drive
Translator
MS1
Control
Logic
DMOS Full Bridge
RS1
VBB2
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
ENABLE
SENSE2
RS2
DAC
VREF
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A3982
DMOS Stepper Motor Driver with Translator
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics
Output Drivers
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
Min.
Typ.2
Max.
Units
8
3.0
–
–
–
–
–
–
–
–
–
–
0.370
0.330
–
–
–
–
–
–
35
5.5
0.460
0.380
1.2
1.2
4
2
8
5
V
V
Ω
Ω
V
V
mA
mA
mA
mA
VIN(1)
VDD0.7
–
–
V
VIN(0)
–
–
V
μA
Symbol
VBB
VDD
RDSON
Body Diode Forward Voltage
VF
Motor Supply Current
IBB
Logic Supply Current
IDD
Test Conditions
Operating
Operating
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
Operating, outputs disabled
fPWM < 50 kHz
Outputs off
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
Blank Time
IIN(1)
IIN(0)
VIN = VDD0.7
VIN = VDD0.3
VHYS(IN)
tBLANK
Fixed Off-Time
tOFF
Reference Input Voltage Range
Reference Input Current
VREF
IREF
Current Trip-Level Error3
errI
Crossover Dead Time
Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
tDT
OSC > 3 V
ROSC = 25 kΩ
VREF = 2 V, %ITripMAX = 70.71%
VREF = 2 V, %ITripMAX = 100.00%
TJ
TJHYS
UVLO
UVHYS
VDD rising
–20
<1.0
VDD0.3
20
–20
<1.0
20
μA
150
0.7
20
23
0
–3
–
–
100
300
1
30
30
–
0
–
–
475
500
1.3
40
37
4
3
±5
±5
800
mV
μs
μs
μs
V
μA
%
%
ns
–
–
2.35
0.05
165
15
2.7
0.10
–
–
3
–
°C
°C
V
V
1Negative current is defined as coming out of (sourcing from) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
I = (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX ITripMAX.
3err

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115 Northeast Cutoff
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A3982
DMOS Stepper Motor Driver with Translator
THERMAL CHARACTERISTICS
Characteristic
Symbol
RθJA
Package Thermal Resistance
Test Conditions*
Value Units
One-layer PCB, one-sided with copper limited to solder pads
77
ºC/W
One-layer PCB, two-sided with copper limited to solder pads and
3.57 in.2 of copper area on each side, connected to PGND pins
45
ºC/W
Four-layer PCB, based on JEDEC standard
35
ºC/W
*Additional thermal information available on Allegro Web site.
Power Dissipation versus Ambient Temperature
4.00
Power Dissipation, PD (W)
3.50
3.00
R
θJ
2.50
A
=
35
R
θJ
2.00
1.50
A
R
θJA
1.00
=
45
=7
ºC
/W
ºC
/W
7 ºC
/W
0.50
0
20
40
60
80
100
120
Temperature, TA (°C)
140
160
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115 Northeast Cutoff
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A3982
DMOS Stepper Motor Driver with Translator
tA
tB
STEP
tC
tD
MS1,
RESET, or DIR
Time Duration
Symbol
Typ.
Unit
STEP minimum, HIGH pulse width
tA
1
μs
STEP minimum, LOW pulse width
tB
1
μs
Setup time, input change to STEP
tC
200
ns
Hold time, input change to STEP
tD
200
ns
Figure 1. Logic Interface Timing Diagram
Table 1. Stepping Resolution Truth Table
MS1
Step Resolution
Excitation Mode
L
Full Step
2 Phase
H
Half Step
1-2 Phase
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A3982
DMOS Stepper Motor Driver with Translator
Functional Description
Device Operation. The A3982 is a complete stepper
motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full- and half-step modes. The currents in
each of the two output full-bridges and all of the N-channel
DMOS FETs are regulated with fixed off-time PMW (pulse
width modulated) control circuitry. At each step, the current
for each full-bridge is set by the value of its external currentsense resistor (RS1 or RS2), a reference voltage (VREF), and
the output voltage of its DAC (which in turn is controlled by
the output of the translator).
At power-on or reset, the translator sets the DACs and the
phase current polarity to the initial Home state (shown in
figures 2 and 3), and the current regulator to Mixed Decay
Mode for both phases. When a step command signal occurs
on the STEP input, the translator automatically sequences
the DACs to the next level and current polarity. (See table 2
for the current-level sequence.) The step resolution is set by
input MS1, as shown in table 1.
When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
for the active full-bridge is set to Mixed. If the new output
levels of the DACs are higher than or equal to their previous
levels, then the decay mode for the active full-bridge is set to
Slow. This automatic current decay selection improves stepping performance by reducing the distortion of the current
waveform that results from the back EMF of the motor.
RESET Input (RESET). The RESET input sets the
translator to a predefined Home state (shown in figures 2
and 3), and turns off all of the DMOS outputs. All STEP
inputs are ignored until the RESET input is set to high.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of the
increment is determined by input MS1, as shown in table 1.
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clockwise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and
the current sense resistor, RSx. When the voltage across RSx
equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off either the
source DMOS FET (when in Slow Decay Mode) or the sink
and source DMOS FETs (when in Mixed Decay Mode).
The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of
current limiting, ITripMAX (A), which is set by
ITripMAX = VREF / ( 8
 RS)
where RS is the resistance of the sense resistor (Ω) and VREF
is the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
Itrip = (%ITripMAX / 100)
× ITripMAX
(See table 2 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1
and SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time
that the DMOS FETs remain off. The one shot off-time, tOFF,
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A3982
DMOS Stepper Motor Driver with Translator
is determined by the selection of an external resistor connected from the ROSC timing pin to ground. If the ROSC
pin is tied to an external voltage > 3 V, then tOFF defaults to
30 μs. The ROSC pin can be safely connected to the VDD
pin for this purpose. The value of tOFF (μs) is approximately
tOFF ≈ ROSC ⁄ 825
Blanking. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs
are blanked to prevent false overcurrent detection due to
reverse recovery currents of the clamp diodes, and switching
transients related to the capacitance of the load. The blank
time, tBLANK (μs), is approximately
tBLANK ≈ 1 μs
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB
for driving the source-side DMOS gates. A 0.1 μF ceramic
capacitor, should be connected between CP1 and CP2. In
addition, a 0.1 μF ceramic capacitor is required between
VCP and VBB, to act as a reservoir for operating the
high-side DMOS gates.
VREG (VREG). This internally-generated voltage is
used to operate the sink-side DMOS outputs. The VREG
pin must be decoupled with a 0.22 μF ceramic capacitor to
ground. VREG is internally monitored. In the case of a fault
condition, the DMOS outputs of the A3982 are disabled.
Enable Input (ENABLE). This input turns on or off all
of the DMOS outputs. When set to a logic high, the outputs
are disabled. When set to a logic low, the internal control
enables the outputs as required. The translator inputs STEP,
DIR, and MS1, as well as the internal sequencing logic, all
remain active, independent of the ENABLE input state.
Shutdown. In the event of a fault, overtemperature
(excess TJ) or an undervoltage (on VCP), the DMOS outputs of the A3982 are disabled until the fault condition is
removed. At power-on, the UVLO (undervoltage lockout)
circuit disables the DMOS outputs and resets the translator
to the Home state.
Mixed Decay Operation. The bridge can operate in
Mixed Decay Mode, depending on the step sequence, as
shown in figures 3 thru 5. As the trip point is reached, the
A3982 initially goes into a fast decay mode for 31.25%
of the off-time, tOFF. After that, it switches to Slow Decay
Mode for the remainder of tOFF.
Synchronous Rectification. When a PWM-off cycle
is triggered by an internal fixed–off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. This synchronous rectification feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS RDSON. This
reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications.
Turning off synchronous rectification prevents the reversal of
the load current when a zero-current level is detected.
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A3982
DMOS Stepper Motor Driver with Translator
STEP
STEP
100.00
100.00
70.71
70.71
Slow
Phase 1
IOUT1A
Direction = H
(%)
100.00
Phase 2
IOUT2A
Direction = H
(%)
–100.00
100.00
70.71
Phase 2
IOUT2A
Direction = H
(%)
0.00
Slow
Slow Slow
Mixed
Mixed
Slow
Slow
Mixed
0.00
–70.71
–70.71
–100.00
–100.00
Figure 2. Decay Mode for Full-Step Increments
Mixed
0.00
–70.71
70.71
Slow
Mixed
Home Microstep Position
–100.00
Slow
Mixed
Home Microstep Position
–70.71
Home Microstep Position
0.00
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
Slow
Figure 3. Decay Modes for Half-Step Increments
Table 2. Step Sequencing Settings
Home step position at Step Angle 45º; DIR = H
Phase 1
Current
Phase 2
Current
[% ItripMax]
[% ItripMax]
(%)
100.00
(%)
0.00
Step
Angle
(º)
0.0
70.71
70.71
45.0
0.00
100.00
90.0
4
–70.71
70.71
135.0
5
–100.00
0.00
180.0
3
6
–70.71
–70.71
225.0
7
0.00
–100.00
270.0
4
8
70.71
–70.71
315.0
Full
Step
#
Half
Step
#
1
1
2
3
2
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A3982
DMOS Stepper Motor Driver with Translator
Pin List Table
Name
OUT2A
Description
Number
DMOS Full Bridge 2 Output A
1
Sense resistor for Bridge 2
2
Load supply
3
DMOS Full Bridge 2 Output B
4
Logic input
5
PGND
Power ground
6
PGND
Power ground
7
CP1
Charge pump capacitor 1
8
CP2
Charge pump capacitor 2
9
VCP
Reservoir capacitor
10
Regulator decoupling
11
MS1
Logic input
12
RESET
Logic input
13
SENSE2
VBB2
OUT2B
ENABLE
VREG
ROSC
Timing set
14
VDD
Logic supply
15
STEP
Logic input
16
Current trip reference voltage input
17
PGND
Power ground
18
PGND
Power ground
19
Logic input
20
DMOS Full Bridge 1 Output B
21
Load supply
22
Sense resistor for Bridge 1
23
DMOS Full Bridge 1 Output A
24
REF
DIR
1OUT1B
VBB1
SENSE1
OUT1A
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A3982
DMOS Stepper Motor Driver with Translator
LB Package, 24-Pin Wide Body SOIC
15.40±0.20
4° ±4
24
+0.07
0.27 –0.06
2.20
10.30±0.33
7.50±0.10
A
1
24
9.60
+0.44
0.84 –0.43
2
1
2
0.65
0.25
24X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
SEATING PLANE
GAUGE PLANE
1.27
B PCB Layout Reference View
2.65 MAX
0.20 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
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Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
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use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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