EBC timing Tool for XC16x microcontrollers - description

Application Note, V 1.0, Dec. 2004
AP16088
XC16x
EBC ti m ing T oo l for XC1 6x
micr ocon tro l lers
Micr ocon tro l lers
N e v e r
s t o p
t h i n k i n g .
XC16x
Revision History:
2004-12
Previous Version:
Page
Subjects (major changes since last revision)
V 1.0
Controller Area Network (CAN): License of Robert Bosch GmbH
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Edition 2004-12
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
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AP16088
EBC timing Tool for XC16x microcontrollers
Table of Contents
Table of Contents
Page
1
Introduction ................................................................................................... 4
2
2.1
2.2
2.3
2.4
EBC Timing Basics ....................................................................................... 5
The External Bus Controller (EBC) ............................................................... 5
Basic Timing Principles (simplified)............................................................... 5
XC166 Basic Bus Cycle Protocols ................................................................ 7
XC166 Principle of Bus Cycle Wait States Distribution ................................. 8
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.3
Timing Calculations Using DEMUX mode ................................................... 10
Access Times and Delays in DEMUX Mode (Ideal case)............................ 10
Address Valid to Data Output Valid Delay............................................... 10
Output Enable to Output Data Valid Delay .............................................. 11
Input Setup Time Delay........................................................................... 11
Output Hold Time Delay .......................................................................... 11
Access Times and Delays in DEMUX Mode (Real case) ............................ 12
Access and Delay Calculations in DEMUX Mode ....................................... 14
4
4.1
4.2
4.3
The EBC Timing Calculation Tool ............................................................... 15
How to work with the Timing Calculation Tool............................................. 15
Sheet Input Data ......................................................................................... 16
Sheet Output Data ...................................................................................... 18
5
5.1
5.2
Using MUX mode ........................................................................................ 20
Sheet input Data ......................................................................................... 20
Sheet Output Data ...................................................................................... 20
6
Last words… ............................................................................................... 21
Application Note
3
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Introduction
1
Introduction
The EBC Timing Calculation Tool is an Excel based tool, which offers an easy way of
evaluation the timing conditions on the bus between an Infineon XC166 microcontroller
derivative and an external device (e g an external memory). Just the most essential
parameters are viewed and the tool will guide the user in his first determination of the
timing capabilities of his design.
It is assumed that the user has the accurate Data Sheets available – for the XC166
device in question as well as for the external devices he or she intend to connect to the
microcontroller EBC (External Bus Controller).
The tool has futhermore not the ambition to generate SFR programming code. For
such purposes the Infineon Dave Tool can be used.
The main objective is to support the designer’s first steps in performance evaluation
and optimization of the targetted design.
The way of working with the sheets is itterative – in the sense that the user will find out
the appropriate clock frequency and parameter conditions by testing different settings
‘by his own head’ and check for ‘acceptance” from the tool. The tool is able to consider
all conditions that have to be taken care of – even for an application that is using a mix
of different memories with different timing qualities, e g a mix of Flash and SRAM.
Note: This application note cannot cover all relevant topics. It can only give hints
for a success EBC Timing Calculation by the aid of the dedicated ‘Timing
Calc XLS Sheet. The intention of this document is to give a structured
guideline on how to handle timing issues and should help to avoid general
mistakes.
Application Note
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AP16088
EBC timing Tool for XC16x microcontrollers
EBC Timing Basics
2
EBC Timing Basics
2.1
The External Bus Controller (EBC)
External accesses are performed by the External Bus Controller (EBC) dynamically,
depending on the selected Address Range and chosen Chip Select Line to one of four
possible Addressing Modes:
•
•
•
•
16- up to 24-Bit Addresses, 16-Bit data, Demultiplexed (DEMUX)
16- up to 24-Bit Addresses, 16-Bit data, Multiplexed (MUX)
16- up to 24-Bit Addresses, 8-Bit data, Demultiplexed (DEMUX)
16- up to 24-Bit Addresses, 8-Bit data, Multiplexed (MUX)
2.2
Basic Timing Principles (simplified)
XC!66
Memory
CS#
CS#
ADDRESS
ADDRESS
RD#
OE#
RD
RD
WR
WR
DATA
DATA
WR#
Figure 1
WE#
The basic, Intel style DEMUX protocol to External Memory
CS#
Chip Select (Active Low)
ADDRESS
Address Bus (16..24 Bit), see above
RD#
Read strobe (Active Low) for every read access.
DATA
Data Bus (8-/16-Bit)
WR#
Write strobe (Active Low) for every write access
Application Note
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AP16088
EBC timing Tool for XC16x microcontrollers
EBC Timing Basics
ALE
Address Latch Enable for MUX access (is not shown here)
XC!66
Data Read
Valid
CS#
Memory
CS#
ADDRESS
ADDRESS
RD#
OE#
RD
RD
WR
WR
DATA
DATA
WR#
Figure 2
WE#
Example: Read Cycle – Data Read Valid
Read Command is performed by the internal Master Clock (fCM) at that edge by which
it ends the Read Strobe (RD#) output signal.
Application Note
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AP16088
EBC timing Tool for XC16x microcontrollers
EBC Timing Basics
2.3
XC166 Basic Bus Cycle Protocols
XC!66
B
C
D
E
F
CS#
A
Memory
CS#
ADDRESS
ADDRESS
RD#
OE#
RD
RD
WR
WR
DATA
DATA
WR#
Figure 3
WE#
The XC166 External Bus Timing Phases (A-F)
The external bus timing of the XC166 devices consists of 6 Phases (A to F), which in
turn are derived from the Master Clock (fMC) in time slot lengths of 0 TCM up to
individually programmable lengths of TCM (TCM=Master Clock Period). By these
means the designer can adjust lengths and positions of the wait states in each Bus
Cycle Protocol appropriately to the timing characteristics of the external devices in his
application.
Phase A is only used to tri-state the output bus drivers during a chip select switch - to
ensure that no conflicts will occur on the data bus lines by the data from a previously
addressed device before any next device is accessed! From the ‘next device’ point of
view the Phase A is the first phase of its bus cycle – and the addressing lines A23..0,
CS#n, BHE# etc (depending on design) will go active at the beginning of its phase A.
However, Phase A has to be regarded as the last phase in a bus cycle when
calculating the time width – because the calculation is depending on the timing
parameters of the device that was accessed before a chip select switch! (See next
figure).
Application Note
7
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
EBC Timing Basics
2.4
XC166 Principle of Bus Cycle Wait States Distribution
CLKOUT
PHASES
B
(1..2 clocks)
C
(0..3 clock)
D
E
F
(0..1 clock) (1..32 clocks) (0..3 clocks)
A
0..3 clocks
CS#
A=1..3
A=0
ADDRESS
RD#
RD
DATA
WR
WR#
BUS CYCLE
Figure 4
Clock Out (CLKOUT) and adjustable lengths of the phases A..F.
A phase:
Addresses valid, (ALE high),
no Command. CS switch (tri-state wait states)
B phase:
Addresses valid, (ALE high),
no Command. ALE length
C phase:
Addresses valid, (ALE low),
no Command. R/W delay
D phase:
Write data valid, (ALE low),.
no Command, Data valid for Write cycles
E phase:
Command (read or write) active. Access time
Application Note
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V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
EBC Timing Basics
F phase:
Command inactive, Address hold.
Read data tristate time,
Write data hold time
Chip “x” is accessed
PHASES
B
C
D
E
Chip “y” is accessed
A=1..3
F
A
CSy=1 CSx=1
B
C
D
E
A=0
F
B
CS#
CSx=0 CSy=0
ADDRESS
RD#
RD
DATA
WR
WR#
BUS CYCLE n
Figure 5
BUS CYCLE n+1
Demo example showing implementation of Phase A at a CS switch.
Application Note
9
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Timing Calculations Using DEMUX mode
3
Timing Calculations Using DEMUX mode
The time base for all AC characteristics in the XC166 EBC system and control buses
are not referred to the internal CPU Clock but to the Clock Output signal (CLKOUT),
which makes test measurements with externally connected analyzers adequate.
Clock Out (CLKOUT) is derived form the internal Master Clock (fMC), so the period
length of CLKOUT is = 1 TCM. That defines the resolution in positioning and length
setting of wait states in the Bus Cycle Protocol.
3.1
Access Times and Delays in DEMUX Mode (Ideal case)
PHASES
B
(1 clock)
C=0
D=0
A=0
E
(1 clock)
B
(1 clock)
C=0
D=0
A=0
E
(1 clock)
B
(1 clock)
C=0
D=0
A=0
E
(1 clock)
CS#
ADDRESS
Addr to data valid
for the Chip has a
maximum
RD# value to
be considered...
Output Enable Delay
from the Chip has a
maximum value to be
considered...
RD
DATA
WR
Input Setup Time
for the CPU has a
minimum value to
be considered...
At this time
data is read
by the CPU.
WR#
BUS CYCLE n
Figure 6
3.1.1
BUS CYCLE n+1
BUS CYCLE n+2
Address Access and Data Read Delays
Address Valid to Data Output Valid Delay
There’s a certain time the address has to be hold valid by the CPU before the external
device recognizes the address. This time parameter (tacc) is specified by the data sheet
of the external device.
Application Note
10
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Timing Calculations Using DEMUX mode
3.1.2
Output Enable to Output Data Valid Delay
There’s a certain time the read strobe has to be hold active (low) by the CPU before
the external device will recognize the read command and deliver the data on the bus.
This delay (toe) is specified by the data sheet of the external device.
3.1.3
Input Setup Time Delay
There’s a certain time the data has to be hold valid by the external device before the
CPU is prepared to recognize the data by its read command. This delay (tc30) is
specified by the data sheet of the CPU.
PHASES
B
(1 clock)
C=0
D=0
A=0
E
(1 clock)
B
(1 clock)
C=0
D=0
A=0
E
(1 clock)
B
(1 clock)
C=0
D=0
A=0
E
(1 clock)
CS#
ADDRESS
RD#
>0
RD
DATA
Output Hold Time
from the Chip has
a maximum value
to be considered.
WR
WR#
BUS CYCLE n
Figure 7
3.1.4
BUS CYCLE n+1
BUS CYCLE n+2
Output Hold Time to Tristate Delay by the External Device.
Output Hold Time Delay
There’s a certain time (thoz) the external device will need to tristate its data output
drivers after the the disable command from the read strobe. This delay is specified by
the data sheet of the external device.
Application Note
11
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Timing Calculations Using DEMUX mode
3.2
Access Times and Delays in DEMUX Mode (Real case)
In the real case even the rise and fall times for all signal level shifts within the bus
protocol have to be taken into account when calculating the timings on the bus lines..
In addition to that even the jitter caused by the PLL, if used, has to be considered!
CLKOUT
JITTER
A=0
Phases
B
(1 clock)
C=0
D=0
E
(1 clock)
F=0
A=0
B
(1 clock)
C=0
D=0
E
(1 clock)
F=0
A=0
B
(1 clock)
C=0
D=0
E
(1 clock)
F=0
A=0
CS#
ADDRESS
RD#
RD
DATA
WR
WR#
BUS CYCLE n
Figure 8
BUS CYCLE n+1
BUS CYCLE n+2
Impact on Timings by Rise and Fall Times and Jitter (if PLL is used).
The jitter amplitude [in ns] can be of the same magnitude as the AC parameters! Jitter
is normally irrelevant for longer time periods, say around 100 master clock periods or
more – but for a few periods, as is the case within the Bus Cycle, jitter may have
significance.
Note: Read Users Manual chapter “PLL Operation” or in the Data Sheet chapter about
“Timing Parameters” and the section “Phase Locked Loop (PLL)”!
Application Note
12
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AP16088
EBC timing Tool for XC16x microcontrollers
Timing Calculations Using DEMUX mode
A=0
PHASES
B
(1 clock)
C=0
D=0
E
(1 clock)
F=0
A=0
B
(1 clock)
C=0
D=0
E
(1 clock)
F=0
A=0
B
(1 clock)
C=0
D=0
E
(1 clock)
F=0
A=0
CS#
ADDRESS
Addr to data valid
for the Chip has a
maximum
RD# value to
be considered...
Output Enable Delay
from the Chip has a
maximum value to be
considered...
>0
RD
DATA
WR
Input Setup Time
for the CPU has a
minimum value to
be considered...
Output Hold Time
from the Chip has
a maximum value
to be considered.
WR#
BUS CYCLE n
Figure 9
BUS CYCLE n+1
BUS CYCLE n+2
Timing in DEMUX Mode when considering all AC components
Application Note
13
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Timing Calculations Using DEMUX mode
3.3
Access and Delay Calculations in DEMUX Mode
tc12(Max) + tacc + tc30(Min) + tjitter(Max) < T(End_of_E-Phase) – T(Start_of_BUS_Cycle
ADDRESS
RD#
tc12:
Output valid delay for:
A23..A16, A15..A0
(on PORT1)
tc30:
Input setup time for:
READY, D15..D0 (RD data)
tc10:
Output valid delay for:
RD#, WR#(H/L)
tacc:
Adress valid to output
data valid delay
toe:
Output enable to output
data valid delay
t jitter
1,5 + 6,32*N/fMC
RD
DATA
tc10(Max)
+ toe(Max)
+ tc30(Min)
+ tjitter < T(Width_of_E-Phase)
Figure 10
fMC= Master Clock freq.
N=Number of TCM within
phase A to E for Addr acc.
N=Number of TCM within
phase E for RD# strobe
Access and Delay formulas for DEMUX Mode timing calculations
Application Note
14
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AP16088
EBC timing Tool for XC16x microcontrollers
The EBC Timing Calculation Tool
4
The EBC Timing Calculation Tool
The EBC Timing Calculation Tool is an XLS-sheet, which offers an easy way of
evalution the timing conditions on the bus between an XC166 derivative and the
external device. Just the most essential parameters are viewed and the tool will guide
the user in his first determination of the timing capabilities of his design.
DEMUX
CLKOUT
BUS CYCLE PHASE
B
B= 1
ABSOLUTE TIME 0
Jitter [ns] 0
ALE
16
A23-0, BHE#,CSx#
RD# , WR#(L/H)
Abs Time Next Cycle 250,0
DATA (RD)
READ parameters:
Minimal Lenght of
RD sampling Window
(OE-to-Data-valid)max
(ADDR-to-Data-v)max
DATA (RD) to Tristate
WRITE parameters:
(ADDR-to-eof-WR)min
(WR-pulse-width)min
DATA (WR)
Figure 11
16
16
C
C= 0
50,0
-1,8 1,8
XC161CJ-16FF
Bus Cycle Phase Config.
CLKOUT
CSx switch Phase
Fc
20 MHz
Ph-cycles
D
E
A
F
0
Tc
50,0
ns
[y / n]? n A: (0 .. 3)
TRUE B:
A= 0
(1 .. 2)
1
|Jitter|
3,1
ns
D= 1
E= 2
F= 1
TRUE C:
50,0
100,0
200,0
250,0
250,0
(0 .. 3)
0
AC parameters
-1,8 1,8
-2,1 2,13
-2,8 2,76
-3,1 3,08
-3,1 3
TRUE D:
(0 .. 1)
1
tcMin tcMax
TRUE E:
(1 ..32)
2
tc10
1
13
TRUE F:
16
(0 .. 3)
1
tc11
-1
7
OK
total
5
tc12
1
16
min width:
1 254,1
Bus cyc. [ns]:
250,0 tc13
3
16
Memory & parameters:
81,9
tc14
1
14
13
3 205,8
tc15
3
17
Am29F040B-55
tacc
55 tc16
3
17
1 101,0
-3 194,2
toe
30 tc17
319,1
348,9
thoz
18 tc18
thz
18 tc19
tdh
0 tc20
-3
3
RD
twp
30 tc21
0
8
Sampl.
taw
45 tc22
tdw or tds
30 tc23
1
13
tc24
-3
3
CSx by
READ Condition
24,0
Addr? n
tc25
1
13
tc26
13
30,0
OE-to-Data valid OK? TRUE
55,0
tc27
Addr-to-Data valid OK? TRUE
tc28
223,8
RD-data Tristate OK? TRUE
WR
18
tc29
WRITE Condition
Sampl.
tc30
24
tc31
-5
55,0
45
116,0
Addr-v-to-eof-WR# OK? TRUE
17 67,0
30
WR# Pulse Width OK? TRUE
127,2
Data-write-Overlap OK? TRUE
3
1
WR-Data-hold-time OK? TRUE
Sheet Layout for Timing Calculations in DEMUX Mode.
There’s one worksheet for applications working in DEMUX (Demultiplex) Mode and
another one that can deal with MUX (Multiplex) Mode is a similar way.
4.1
How to work with the Timing Calculation Tool
You will have to type in all the essential data into the Sheet Input Data boxes, as for
example Clock Out frequency, CS switch condition, Phase lenghts and AC parameters
of all the devices.
Note: You can only manipulate cells with yellow bottom color!
Output data is comments such as ‘TRUE’, ‘FALSE’, ‘OK’, ‘NOT OK’ reflecting how
successful you have been in your approach of setting the data in the input data boxes.
Application Note
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AP16088
EBC timing Tool for XC16x microcontrollers
The EBC Timing Calculation Tool
4.2
Sheet Input Data
• Fill in Clock Out Frequency (CLKOUT), which is equal to the internal Master Clock.
Fc
Tc
|Jitter|
Figure 12
CLKOUT
20 MHz
50,0
ns
3,1
ns
Where you put in CLKOUT frequency
• Fill in all the Phase B..F values, which will set the respective number of Master
Clock periods (TCM) for each phase. The values have to be within the respective
ranges that are hinted within brackets for each phase. Extending any range will be
indicated with a “FALSE” sign and a “NOT OK” sign for the total bus cycle length.
• Phase A=0 and can not be filled in by the user. It will be calculated by the sheet
automatically, if the user wants that a Chip Select switch should be considered. This
mode can be selected by filling in “y” (=yes). Default is “n” (=”no”).
Bus Cycle Phase Config.
CSx switch Phase
Ph-cycles
[y / n]? n A: (0 .. 3)
0
TRUE B:
(1 .. 2)
1
TRUE C:
(0 .. 3)
0
3
TRUE D:
(0 .. 1)
1
TRUE E:
(1 ..32)
2
TRUE F:
(0 .. 3)
1
total
5
OK
Bus cyc. [ns]:
250,0
Figure 13
Where you put in the Phase lengths
Application Note
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AP16088
EBC timing Tool for XC16x microcontrollers
The EBC Timing Calculation Tool
• Fill in the relevant AC Parameters of the External Device (e g Memory)
Memory & parameters:
Am29F040B-55
tacc
55
toe
30
thoz
18
thz
18
tdh
0
twp
30
taw
45
tdw or tds
30
Figure 14
Where you put in External Device AC Parameters
Application Note
17
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
The EBC Timing Calculation Tool
Fill in the relevant AC Parameters of the XC166 derivative (e g XC161CJ-16FF)
tc10
tc11
tc12
tc13
tc14
tc15
tc16
tc17
tc18
tc19
tc20
tc21
tc22
tc23
tc24
tc25
tc26
tc27
tc28
tc29
tc30
tc31
Figure 15
AC parameters
tcMin tcMax
1
13
-1
7
1
16
3
16
1
14
3
17
3
17
-3
0
3
8
1
-3
1
13
3
13
24
-5
Where you put in Microcontroller AC Parameters
All parameters listed in the XLS worksheet are explained by comments in the
respective cells – but can also, of course, be found and clarified in the Data Sheets.
4.3
Sheet Output Data
In the Outpot Box of the XLS Sheet, the success from setting up the the different
timing conditions in the Sheet Input Data boxes is disclosed by simple ‘TRUE’ or
‘FALSE’ statements.
Application Note
18
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
The EBC Timing Calculation Tool
CSx by
Addr? n
READ Condition
OE-to-Data valid OK? TRUE
Addr-to-Data valid OK? TRUE
RD-data Tristate OK? TRUE
WRITE Condition
Addr-v-to-eof-WR# OK? TRUE
WR# Pulse Width OK? TRUE
Data-write-Overlap OK? TRUE
WR-Data-hold-time OK? TRUE
Figure 16
Output Data
Note that even an additional option can to be found in the Sheet Ouput Box; namely
using an Address Line as Chip Select line in the user application! If the user has
implemented such an opportunity, he should mark this condition by writing “y” (=yes)
where this question appears in the output box. (Default setting is “n” (=no).
Application Note
19
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Using MUX mode
5
Using MUX mode
The worksheet for MUX Mode timing evaluations looks quite similar to the one for the
DEMUX mode – except for the AC parameter for the Adress Latch that is used to store
the Low Address during each bus cycle (and the ALE strobe AC parameters, of
course)
MUX
CLKOUT
BUS CYCLE PHASE
B
B= 1
ABSOLUTE TIME 0
Jitter [ns]
ALE
C
D
C= 2
50,0
-1,8 1,8
16
E
D= 1
F
E= 2
150,0
F= 1
200,0
-2,4 2,4
300,0
-2,8 2,76
A=
350,0
-3,4 3,4
-3,7 3,71
8
16
A23-16, BHE#,CSx#
min width:
1
84,0
13
RD# , WR#(L/H)
Abs Time Next Cycle 400,0
A15-A0 Latch Output
tld= 5
16
569,8
3 306,4
1 598,2
-3 293,6
13
AD15-AD0 (RD)
RD
Sampl.
READ parameters:
Minimal Lenght of
RD sampling Window
(OE-to-Data-valid)max
(ADDR-to-Data-v)max
DATA (RD) to Tristate
24,0
13
59,8
5
30,0
70,0
326,4
WR
WRITE parameters:
(ADDR-to-eof-WR)min
(WR-pulse-width)min
AD15-AD0 (WR)
20
Sampl.
59,8
5
70,0
45
17
179,8
35
124,2
3
Figure 17
5.1
1
Microcontroller:
XC161CJ-16FF
Bus Cycle Phase Config.
CLKOUT
CSx switch Phase
Ph-cycles
Fc
20 MHz
A
[y / n]? y A: (0 .. 3)
1
Tc
50,0
ns
TRUE B:
1
(1 .. 2)
1
|Jitter|
4,0
ns
TRUE C:
AC parameters
400,0
(0 .. 3)
2
-4,0 4
TRUE D:
(0 .. 1)
1
tcMin tcMax
TRUE E:
(1 ..32)
2
tc10
1
13
TRUE F:
(0 .. 3)
1
tc11
-1
7
OK tot
7
tc12
1
16
354,7
Bus cyc. ns:
350,0 tc13
3
16
Memory and parameters tc14
1
14
Am29F040B-70
tc15
3
17
tacc
70 tc16
3
17
toe
30 tc17
thoz
20 tc18
thz
20 tc19
tdh
0 tc20
-3
3
twp
35 tc21
0
8
taw
45 tc22
tdw or tds
30 tc23
1
13
tc24
-3
3
CSx by
READ Condition
Addr? n
tc25
1
13
tc26
OE-to-Data valid OK? TRUE
tc27
Addr-to-Data valid OK? TRUE
tc28
RD-Data Tristate OK? TRUE
tc29
WRITE Condition
tc30
24
Addr-v-to-eof-WR# OK? TRUE
tc31
-5
WR# Pulse Width OK? TRUE
Latch <addr. latch>
Data-write-Overlap OK? TRUE
tld
5
WR-Data-hold-time OK? TRUE
Sheet Layout for Timing Calculations in MUX Mode.
Sheet input Data
• Fill in accordingly to the description shown for the DEMUX Mode
• Fill in appropriate ALE length by the number of Clock Cycles for Phase B
• Fill in Address Latch Output Valid Delay (tld)
5.2
Sheet Output Data
The success from setting all relevant input data is shown by ‘TRUE’ or ‘FALSE’ in the
Sheet Output Box (similar to the description for the DEMUX Mode).
Application Note
20
V 1.0, 2004-12
AP16088
EBC timing Tool for XC16x microcontrollers
Last words…
6
Last words…
Note: All documents like datasheets, user’s manuals or addendums for the
selected device should be crosschecked in all aspects regarding new
functions or deviations to former versions and the latest documents
should always be used.
The latest XC16x related documents can be found by the following link:
http://www.infineon.com/XC166-Family
In case for any reason this link does not work you can find such information by the
links:
Infineon home page: http://www.infineon.com
Infineon microcontroller home page: http://www.infineon.com/microcontrollers
Application Note
21
V 1.0, 2004-12
http://www.infineon.com
Published by Infineon Technologies AG
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