Understanding the TC1765 Bootstrap-Loader

A pplica tion N ote , V 1.0, M arch 2002
AP3263
TC1765
U n d e rs t a n d i n g t h e T C 1 7 6 5
B o o t S tr a p L o a d e r s
This document describes the functionality of the ASC (asynchronous serial channel), SSC
(synchronous serial channel) and CAN (Controller Area Network) bootstrap loader available
for TC1765 - Infineon 32-bit Microcontroller.
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
Edition 2002-03
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
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AP3263
Understanding the TC1765 BootStrap Loaders
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
Common BSL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entering the Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TC1765 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.5
2.6
ASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
The ASC Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Entering the ASC Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Exiting the ASC Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ASC Boot Algorithm for the Internal ROM Program Flow . . . . . . . . . . . . . . 8
ASC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Synchronous Serial Channel (SSC) Bootstrap Loader . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entering the SSC Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud rate generation for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exiting the SSC Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Boot Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC BSL Data Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
12
15
15
16
18
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The CAN Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TC1765 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement of dominant CAN bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements of the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Detection using the Analyzing mode . . . . . . . . . . . . . . . . . . . . .
Loading the Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exiting the Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Choosing the Baud rate for the Bootstrap Loader . . . . . . . . . . . . . . . . . . .
TwinCAN Boot Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
21
21
22
22
23
23
25
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Understanding the TC1765 BootStrap Loaders
Common BSL Configuration
1
Common BSL Configuration
The section describes the common features of all of the bootstrap loaders.
1.1
Booting Scheme
The bootstrap loader is an integrated mechanism that can be selected via a port
configuration during a system start after reset. If the bootstrap loader mode is selected
during reset, program execution is started from the Internal Boot ROM.
1.2
Hardware Booting Scheme
The hardware booting scheme uses the state of a number of external pins, sampled and
latched with a power-on-reset, to determine the start configuration of the chip. The state
of these pins is latched into the Reset Status Register (RST_SR) when the power-onreset signal (pin PORST) is released and transitions to a high level (while PORST is
active the latches are transparent). The hardware configuration is determined by the
value of bits OCDS_E, BRK_IN and CFG[2:0]. The latched values can only be changed
by another power-on-reset and are used for all hardware-invoked reset options (poweron, hard, watchdog and wake-up reset). Table 1 shows the Available BootStrap Loaders
(BSL) options available in the TC1765.
Table 1
Available Bootstrap Loader ROM Selection
OCDSE BRKIN CFG[2:0] Type of Boot
Boot Source PC Start Value
1
1
000B
ASC Bootstrap Loader Boot ROM
BFFF FFFCH
1
1
001B
SSC Bootstrap Loader Boot ROM
BFFF FFFCH
1
1
010B
CAN Bootstrap Loader Boot ROM
BFFF FFFCH
1.3
Entering the Bootstrap Loader Mode
If the selection matches the configuration for the bootstrap loader as shown in Table 1.
Then program execution begins in the internal 8 KByte boot ROM memory (BFFF FFFFH
- BFFF E000H). The particular BSL routine that runs is determined by the main boot
software reading the value of the CFG[2:0] bits and jumping to the respective routine.
1.4
Interrupts
The bootstrap loader software is very simplistic and does not use interrupts. The user
should take this into account when attempting to use very high baud rates when
connecting to the serial ports.
Note: The user should locate their code assuming a start address of C000 0004H.
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Understanding the TC1765 BootStrap Loaders
Common BSL Configuration
1.5
Internal Register Settings
When the TC1765 has entered BSL mode, the following configuration is automatically
set.
Table 2
CPU Register Settings1)
Register
Setting
Register
Setting
Watchdog Timer
Disabled
BTV
BFFF E200H
ENDINIT Protection
Enabled
ISP
D000 3740H
LCX
000D 000EH
FCX
000D 004CH
BIV
BFFF E000H
1)
All other registers TBD.
Note: The main bootstrap loader routine has configured 64 CSAs.
1.6
TC1765 Operating Frequency
The user must be aware that the TC1765 has no way of determining at what frequency
it is operating at. Therefore, the user must have some system knowledge and
understanding of the possible communication baud rates can be generated by the
TC1765.
The ASC0, SSC0, and TwinCAN modules are all clocked at the same frequency as the
fSystemClk and assume the base crystal frequency is 16 MHz.
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Understanding the TC1765 BootStrap Loaders
Common BSL Configuration
1.6.1
PLL Factors
The following equation defines the relationship between the fOSC and fSystenClk. The PLL
“K” factor is controlled via the PLLDIVCLK field in register PLLCLC.
The system clock fSystemClk is:
f SystemClk = ( 10 • f OSC ) ⁄ K
An example of a typical clock configuration setting would be as follows:
Table 3
Clock Parameters
PLLDIVCLK
111B
Unchanged from Reset value, “K” factor is equal to 10
BYPASS
0B
is at a logic level low, i.e. fSystemClk is supplied from the PLL
fOSC
16 MHz
Base Crystal Frequency
This results in a fSystemClk of 16 MHz.
Note: For more information regarding the clock settings please refer to the TC1765
Users Manual.
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Understanding the TC1765 BootStrap Loaders
ASC
2
ASC
2.1
The ASC Bootstrap Loader
The built-in ASC bootstrap loader of the TC1765 provides a mechanism to load the
startup program, which is executed after reset, via the asynchronous serial interface. In
this case no external (ROM) memory is required for the initialization code. The bootstrap
loader moves 128 bytes of code/ data into the internal SPRAM starting at
address C000 0004H.
Most probably the initially loaded routine will load additional code or data. This second
receive loop may directly use the pre-initialized ASC interface to receive data and store
it to arbitrary user-defined locations.
PORST
Port Pin Selection
for ASC Boot
1
2
3
5
RxD0
4
TxD0
6
PC
7
Figure 1
2.2
Int. Boot ROM BSL -SSC Routine
User Code
1
BSL initialization and selection time, 100 us @ fCPU = 16 MHz
2
Zero byte (1start Bit, eight ’0’ data Bits, 1 stop Bit), sent by host
3
Receiver is disabled during the transmitting of the Identification byte
4
Identifcation byte, sent by the TC1775B
5
128 bytes of code/data, sent by host
6
There is ~1.5 msec time lap between the reception of the zero byte and the transmission of the ID byte
7
Internal Boot ROM
ASC Bootstrap Loader Sequence
Initialization
The ASC BSL initializes the ASC0 in the following way:
• Receive data pointer is initialized to address C000 0004H
• baud rate depends on host (auto baud rate detection)
• 8 data bits
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Understanding the TC1765 BootStrap Loaders
ASC
• one start/stop bit
• ASC0 interface is selected via port pins
– P0.7 RxD0
– P0.8 TxD0
2.3
Entering the ASC Bootstrap Loader
The ASC bootstrap loader code is a routine contained within the boot ROM of the
TC1765. TC1765 enters SSC BSL mode when the pin configuration shown in Table 4
Table 4
ASC Bootstrap ROM Selection
OCDSE BRKIN CFG [2:0] Type of Boot
1
1
000B
Boot Source PC Start Value
ASC Bootstrap Loader Boot ROM
BFFF FFFCH
The first task ASC0 needs to perform is to determine the baud rate at which the host is
communicating at. This is done by capturing the time period of a zero byte (one start bit
and eight “0” data bits) transmitted by the host and received at the ASC0 receive pin.
Therefore, a software polling loop begins by first waiting for the ASC0 receive pin to
remain at a high level. Once a high level has been detected the software now begins
looking for a falling edge. After a falling edge has been detected the system timer is read
and the software now looks for a rising edge.
When the rising edge is found the system timer is read again and the difference between
the two readings is calculated. This value represents the time period for one zero byte
transmitted by the host and is the basis for calculating the host baud rate with respect to
the fSYSCLK clock.
The next step is to enable the ASC clock generator. This requires a password unlock
sequence to be performed to the WDT to gain write access to the ASC CLC Control
register (fSYSCLK = fASC). After writing the ASC CLC register the WDT is then locked
again.
The ASC boot loader continues by initializing the serial port pins and calculating the baud
rate. The baud rate is calculated by searching for the best values for the Fraction Divide
Value (FDV) and Baud rate Generator (BG) registers.
Figure 2, represents the block diagram of the ASC Baud Rate Generator.
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Understanding the TC1765 BootStrap Loaders
ASC
ASC Baud-Rate Generator Circuitry for Boot Mode Asynchronous Operation
FDV
BG
13-bit Reload Register
16
Fractional
Divider
fASC
fDIV
fBR
13-bit Baud Rate Timer
Baud Rate Clock
Sample Clock
fBRT
Figure 2
ASC Baud Rate Generator
The software must now determine the values to be written in the Fractional Divide Value
register and the Baud rate Generator register. The Baud rate is found by using min/max
boundaries to find the best fit value for BG as shown in the following formulas.
Timer Value = Measured system timer tick for a zero byte transmission
EDXG _ UDWH$6& =
Application Note
6
9 ⋅ I $6&
7LPHU9DOXH
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Understanding the TC1765 BootStrap Loaders
ASC
Therefore substituting for baud_bateASC in the equations and solving for BG:
9
)'9
=
7LPHU9DOXH (512 ⋅ 16 ⋅ (%* + 1))
9 ⋅ 512 ⋅ 16
)'9
=
7LPHU9DOXH %* + 1
)'9 =
73728 ⋅ %*
73728
+
7LPHU9DOXH 7LPHU9DOXH
73728 ⋅ %*
73728
= )'9 −
7LPHU9DOXH
7LPHU9DOXH
73728 ⋅ %* = )'9 ⋅ 7LPHU9DOXH − 73728
%* =
)'9 ⋅ 7LPHU9DOXH
−1
73728
Next the ASC0 is initialized (receive pin remains disabled) to the baud rate of the host,
an identification byte (D5H) is returned to the host indicating the device is ready to accept
a data transfer from the host of exactly 128 bytes. The ASC0 receive pin is enabled after
the identification byte has been transmitted.
The software now enters two receive loops. The inner loop is waiting until it has received
four bytes. The outer loop will write (word) the word access to the program memory. This
process repeats until 128 bytes have been received.
Note: The ASC bootstrap loader expects a block size of exactly 128 bytes (32 words).
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Understanding the TC1765 BootStrap Loaders
ASC
2.4
Exiting the ASC Bootstrap Loader
Once 128 bytes have been received and written to program memory a “Jump Indirect”
command (JI) is performed to the memory location C000 0004H and program execution
begins at this point (user program).
2.5
ASC Boot Algorithm for the Internal ROM Program Flow
Figure 3 shows a flowchart of the ASC boot algorithm.
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Understanding the TC1765 BootStrap Loaders
ASC
Start
No
Wait for Rx Pin high
Yes
No
Wait for falling edge on
Rx pin
Yes
Read system timer
No
Wait for rising edge on
Rx pin
No
Yes
Data byte
received ?
Read system timer
Calculate timer value
Yes
Unlock WDT
Enable ASC Clock
Lock WDT
Initialize ASC port pins
No
Clear Receive Flag
Store data byte to temp
RAM buffer
Calculate baud rate
(search for best values for
FDV and BG)
No
Decrement receive counter
Initialize ASC
Set Fractional divider and BG
Word receive
counter = 0?
Transmit Acknowledge byte
Yes
No
Write Data word to Memory
Increment Receive Data pointer
Decrement Data receive counter
Ack. byte sent ?
Yes
All program data
words loaded ?
Enable Receiver
Init. Receive Data pointer
Set Word receive counter = 4
Set Data receive counter = 32
Yes
Jump to RAM_START
(0xC0000004)
End
Figure 3
ASC Boot Algorithm
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Understanding the TC1765 BootStrap Loaders
ASC
2.6
ASC Timing
Figure 4
Logic Analyzer Trace of the actual data transfer
Typical Timing (Bus Clock 16 KHz, 9600 Baud)
Boot Initialization (Host must wait before sending the zero byte from the rising edge of
PORST)
~ 100 µsec
From rising edge of RxD (host last data bit) to the falling edge of TxD (Start bit from the
TC1765 sending the ID byte).
~ 1.5 msec
Delay from the reception of the ID byte to the host downloading data
~ 100 µsec
Between byte transfers: at high baud rate the user may need to add inter-byte delays
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Understanding the TC1765 BootStrap Loaders
SSC
3
SSC
3.1
The Synchronous Serial Channel (SSC) Bootstrap Loader
The built-in Synchronous Serial Channel bootstrap loader of the TC1765 provides a
mechanism to load a user defined program via the SSC0 interface. The bootstrap loader
moves code/data into the internal Scratch Pad RAM (SPRAM) starting at
location “C000 0004H”.
The default SSC BSL configuration is assumed to have an SPI compatible EEPROM
(25xxx series) connected to the TC1765’s SSC0 port. The SSC BSL supports memory
devices with 8-bit or 16-bit addressing and any other possibility can be assumed by the
user if they understand this default configuration.
PORST
Port Pin Selection
for SSC Boot
4
1
3
2
SSC CS
5
PC
6
Int. Boot ROM BSL -SSC Routine
User Code
1 BSL initialization and selection time
2 Initial SSC BSL read for ID and Length codes
3 Length calculation
4 If read failure ([ID != A5h; CS 2 toggles], [Length == 0; CS 3 toggles])
5 Data read action
6 Internal Boot ROM
Figure 5
SSC Bootstrap Loader Sequence
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Understanding the TC1765 BootStrap Loaders
SSC
3.2
Initialization
The SSC BSL initializes the SSC0 in the following way:
•
•
•
•
•
•
•
CPU is master for master mode
SPI mode 0 (0,0)
1 MHz clock rate (16 MHz external clock)
Data length 8 bits
Port pin assignment (4 pins)
Receive data pointer set to address C000 0004H
SPI memory chip-select via port pin
– P0.9
SCLK
– P0.10
MRST
– P0.11
MTSR
– P4.0
CS
3.3
Entering the SSC Bootstrap Loader
The SSC bootstrap loader code is stored in and is part of the TC1765 boot ROM. The
TC1765 enters SSC BSL mode when the pin configuration shown in Table 5 following a
PORST.
Table 5
SSC Bootstrap ROM Selection
OCDSE BRKIN CFG [2:0] Type of Boot
1
3.4
1
001B
Boot Source PC Start Value
SSC Bootstrap Loader Boot ROM
BFFF FFFCH
Loading the Startup Code
The port pins for the SSC0 and CS are setup along with the SSC operating parameters.
The boot software attempts to set the SSC clock frequency to a nominal rate of 1 MHz
(assuming a base crystal frequency of 16 MHz).
The SSC BSL will basically perform two read accesses (see Figure 7 and Figure 8).
The first read access is to determine the addressing mode and the number of bytes to
read. The second access is to actually load the user program into its internal program
RAM. There is also the possibility of detecting two data format errors. The errors are
either for an incorrect Identification byte or zero data length. The user is notified of an
error on the CS line. The toggling of the CS line between the two read access would
indicate that an error occurred during the initial read access.
Both read access begin by the SSC sending a read command (data value = 3) with a
memory start address of zero. The SSC BSL determines the type of memory (8- or /16bit addressing) by checking at which position the memory identifier byte is located. An
example of the memory map of an EEPROM device is shown in Table 6. For memory
types with 8-bit addressing this will happen after the first address byte, for memory types
with 16-bit addressing this happens after the second address byte is read. If the correct
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Understanding the TC1765 BootStrap Loaders
SSC
memory identifier byte is not equal to 5AH then the CS line is quickly toggled twice and
then the software enters an endless loop. Assuming there was not an error the data byte
following the memory identifier is assumed to be the size index byte. The size index
informs the bootstrap loader of the number of bytes multiplies by 16 that are to be
received. This allows block of up to 2040 (32-bit) or 4080 (16-bit) instructions can be
loaded into memory. This process continues until all bytes have been read from the
serial memory.
Table 6
Content of the EEPROM
EEPROM Address
Data value
Meaning
0x0000
0x5A
Memory Identifier (ID)
0x0001
0x01...0xFF
Size Index (Number of bytes to load * 16)
0x0002...0x1FE2
0x00...0xFF
User Code/Data
1
2
b
3
4
5
6
7
8
MSB
6
5
4
3
2
1
LSB
SCK Cycle #
a
SCK
MTSR
CS
Figure 6
a
data latched
b
data shifted
Example of SPI Mode 0
Note: The SSC BSL uses mode 0 to communicate thereby bit PH is set to “1” and bit PO
is set to ”0” in register SSCx_CON.
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Understanding the TC1765 BootStrap Loaders
SSC
CS
CLK
READ
Command
SO
Address Byte
High
Address Byte
Low
Transfer Byte
Transfer Byte
Transfer Byte
ID Byte
Count Byte
Data Byte 1
Data Byte 2
8-bit type
Data Byte 1
16-bit type
SI
ID Byte
Byte 1
Figure 7
Byte 2
Byte 3
Byte 4
Count Byte
Byte 5
Byte 6
Initial SSC BSL data transfer
CS
CLK
SO
READ
Command
Address Byte
High
Address Byte
Low
Transfer Byte
Transfer Byte
Transfer Byte
Transfer Byte
Transfer Byte
ID Byte
Count Byte
Data Byte n
Data Byte
n+1
Data Byte
n+2
Data Byte
n = size * 16
Data Byte 1
Data Byte 1
Data Byte
n = (size*16) -1
Byte 6
Byte 7
Transfer Byte
8-bit type
SI
ID Byte
Byte 1
Figure 8
Byte 2
Byte 3
Byte 4
Count Byte
Byte 5
Last Byte
8-bit
Data Byte
n=size*16
16-bit type
Last Byte
16-bit
Second SSC BSL data transfer
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Understanding the TC1765 BootStrap Loaders
SSC
3.5
Baud rate generation for the BSL
The BSL has no way to determine its base clock frequency and therefore assumes that
this is 16 MHz. Additionally, the K factor of the PLL is not modified by the BSL so it
remains at its default value of seven. The BSL will automatically enable the SSC clock
and the set the value of the SSC Clock divider to 1 (unity) so that the SSC clock
frequency is equal to the system clock frequency fSYSCLK. The system clock frequency
for TC1765 is determined from the following formula:
I 6<6&/. =
10
•
.
I
26&
The calculation of the reload value is done by:


I 66&
 −1
< %5 > = 

 2 ⋅ EDXG _ UDWH66& 
The actual baud_rateSSC value must be determined from the following formula:
EDXG _ UDWH66& =
3.6
I 66&
2 ⋅ (< %5 > + 1)
Exiting the SSC Bootstrap Loader
Once all bytes (size index * 16) have been read and written to program memory a “Jump
Indirect” command (JI) is performed to the memory location C000 0004H and program
execution begins at this point (user program).
Note: The user should locate their program to a start address of C000 0004H.
Application Note
15
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AP3263
Understanding the TC1765 BootStrap Loaders
SSC
3.7
SSC Boot Algorithm
Figure 9 and Figure 10 show a flowchart of the SSC boot algorithm.
Start
Calculate Operating Freqency
Initialize SSC
(port, mode, baud rate)
Initialize Serial EEPROM /CS pin
Jump to ReadEEPROM Function
(read 6 bytes, discard first two bytes)
A
B
RxData[0]
=
ID_OK
Yes
No
No
RxData[1]
=
ID_OK
CS_TOG = 2
Yes
RxData[1] is size_index
Byte count =
(size_index * 16)
RxData[2] is size_index
Byte_count = (size_index * 16)
CS_TOG = 3
Yes
size_index = 0 ?
No
Toggle /CS
Call ReadEEPROM Function
according to CS_TOG
(read EEPROM bytes = byte_count, discard first 4 or 5
bytes)
A
Endless
Loop
B
Jump to RAM_START
(0xC0000004)
Figure 9
SSC Boot Algorithm (Sheet 1/2)
Application Note
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AP3263
Understanding the TC1765 BootStrap Loaders
SSC
A
Parameters
Data pointer, RxCount and ByPass
Select EEPROM (/CS to ’0’)
Send Read Command
7UDQVPLW/RRS
Tx buffer
clear?
Yes
No
No
TxCount > 0
Yes
Clear TxSRR bit
Transmit one byte
Decrement TxCount
Received Rx
Byte?
5HFHLYH/RRS
Yes
Clear TxSRR bit
Even byte?
Yes
Read SSC_RB
No
Read SSC_RB
ByPass > 0
Yes
No
Write halfword to
Program memory
No
Keep reading even
Look for an odd byte
Decrement ByPass
Decrement RxCount
All bytes
received?
No
Yes
Deselect EEPROM
(/CS to ’1’)
B
Figure 10
SSC Boot Algorithm (Sheet 2/2)
Application Note
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AP3263
Understanding the TC1765 BootStrap Loaders
SSC
3.8
SSC BSL Data Transfer Timing
Figure 11
Logic Trace of the start of the SSC BSL data sequence.
Typical SSC BSL Timing (Bus Clock 16 kHz)
Boot Initialization (rising edge of HDRST and the falling edge of CS)
~ 60 µsec
From rising edge CS to the first rising edge of SCLK.
~ 15 µsec
Delay between byte transfers
~ 12 µsec
Time from the falling edge of the last SCLK and the rising edge of CS.
~ 4 µsec
CS high time between the first and second read assesses.
~ 3 µsec
SPI Mode Definitions:
Clock Polarity is defined by symbols CPOL and PO.
Clock Phase is defined by symbols CPHA and PH. Please note that Infineon defines the
value of the clock phase to be inverted to the normally accepted industry standard
(see Figure 12).
Application Note
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V1.0, 2002-03
AP3263
Understanding the TC1765 BootStrap Loaders
SSC
S P I m o de 0 :
C P O L= 0 , C P H A = 0
PO =0, PH=1
CS
C LK
SI
S P I M o de 1 :
D7
D6
D5
D4
D3
D2
C P O L= 0 , C P H A = 1
D1
D0
PO =0, PH=0
CS
C LK
D7
SI
S P I M o de 2 :
D6
D5
D4
D3
C P O L= 1 , C P H A = 0
D2
D1
D0
PO =1, PH=1
CS
C LK
SI
S P I M o de 3 :
D7
D6
D5
D4
D3
D2
C P O L= 1 , C P H A = 1
D1
D0
PO =1, PH=0
CS
C LK
SI
Figure 12
D7
D6
D5
D4
D3
D2
D1
D0
Industry accepted SPI transfer modes and settings compared to
Infineon’s definition
Application Note
19
V1.0, 2002-03
AP3263
Understanding the TC1765 BootStrap Loaders
CAN
4
CAN
4.1
The CAN Bootstrap Loader
The built-in CAN bootstrap loader of the TC1765 provides a mechanism to load a
program via the TwinCAN module (port pins P0[12:13]). The bootstrap loader is an
integrated mechanism that can be selected via a port configuration during a system start
after reset. If the bootstrap loader mode is selected during reset, program execution is
started from the Internal Boot ROM. The bootstrap loader program will configure its CAN
module to the baud rate of the Host in order for communications to transpire. Once
communication has been established, the bootstrap loader receives a Host defined
variable number of messages for downloading of the code/data. The received code/data
is sequentially written to the on-board Local Code Scratch Pad RAM (SPRAM). In the
TC1765, there are 16 Kbytes of SPRAM available for program execution. After the
download has been completed, the program execution continues by jumping to the start
of the SPRAM (C000 0004H).
The bootstrap loader mechanism may be used for standard system startup as well as for
special occasions like system maintenance (firmware update), end-of-line programming
or testing.
4.2
TC1765 Operating Frequency
The user must be aware that the TC1765 has no way of determining at what frequency
it is operating at. Therefore, the user must have some system knowledge and
understanding of what CAN baud rates can be detected from the Host.
A PC based software executable is provided which determines what baud rates the
TC1765 is capable of receiving based on its system clock frequency (fSystemClk).
4.3
Initialization
The CAN BSL initializes the TwinCAN in the following way:
• The CAN module 0 is used but not initialized until a message is detected
• Message Object 0 is configured to receive a standard CAN frame with a message
identifier of 555H.
• Receive data pointer set to address C000 0004H
• CAN port pins
–P0.12
RxCAN0
–P0.13
TxCAN0
Note: It is recommend that Port0 have no floating inputs or any of its pins changing
states other than P0.12. The CAN BSL software determines the bit timing by
reading the entire port and using it for sampling time calculations.
Application Note
20
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AP3263
Understanding the TC1765 BootStrap Loaders
CAN
4.4
Measurement of dominant CAN bits
The System Timer is used for the measurement of a dominant bit on the CAN bus. The
System Timer is running at the same frequency as the CPU and thus supports the
highest possible resolution.
During this time the CAN module is disabled and the TC1765 software is polling the
RxCAN0 (P0.12) pin to detect pulse bus periods (capturing the time between any edge).
This process will continue until 100 pulses have been measured. Then, a software
algorithm will analyze the data to determine the smallest pulse. From this, the data is
further analyzed to obtain an average of the smallest pulses. This time period is
assumed to be one CAN bit time and, therefore, it is used for the initial setting for
detecting the correct baud rate.
4.5
Requirements of the Host
The host will initiate communication with the TC1765 by transmitting a standard CAN
message (11-bit Identifier). However, for the TC1765 to properly determine the message
baud rate, certain restrictions are imposed on the Host.
•
•
•
•
There is a Point-to-Point connection between the Host and TC1765
The sample point of a CAN bit is at 80%
A baud rate is used which the TC1765 is capable of detecting
The first message the Host sends is of the format below
–The identifier for the standard message is 555H
–The data length code is set to 6
–Data bytes 0 and 1 are the values for the TC1765's Bit Timing Register (BTR)
–Data bytes 2 and 3 contain the identifier for an acknowledge message that the
TC1765 sends back to the Host.
–Data bytes 4 and 5 make up the 16-bit value for the number of messages to
receive
Arbitration
Field
Control
Field
0x555
0x68
Data
Field
CRC
Field
ACK End of
INT
Field Frame
Bus
Idle
Data 7 = Don’t care
Data 6 = Don’t care
Data 5 = Number of Messages to receive High Byte
Data 4 = Number of Messages to receive Low Byte
Data 3 = Ack Identifier High Byte
Data 2 = Ack Identifier Low Byte
Data 1 = BTR High Byte
Data 0 = BTR Low Byte
Figure 13
Format of the first message transmitted by the Master
Application Note
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AP3263
Understanding the TC1765 BootStrap Loaders
CAN
The Host will transmit this message and wait for the TC1765 to acknowledge it. Since
there are no other nodes (Point-to-Point) on the bus, the CAN controller of the Host will
continually repeat the transmission of the message. This is because the TC1765 has not
responded with a dominant bit in the Acknowledge Slot of the transmitted message from
the Host. After the first message the Host’s CAN error management logic will send error
frames until its internal error state changes from error active to error passive. After a
short period of time the TC1765 should be able to detect the Host’s baud rate and
acknowledge the Host’s message.
4.6
Message Detection using the Analyzing mode
There is a CAN Analyzer Mode available on the TwinCAN which provides the means to
monitor CAN bus traffic without participating in the CAN protocol itself. This mode is used
in conjunction with the bit measurement to determine non-destructively (without errors)
the baud rate at which the Host is transmitting its message. The TC1765 will attempt to
recognize the message being broadcast by the Master in analyzer mode. Once the
TC1765 can detect the Master’s message without errors, the TC1765 will enable its CAN
module. The CAN module on the TC1765 will now acknowledge the Master’s message.
This signals the Master that communication has been established with the TC1765. If the
message cannot be detected within a time-out period, the process will be restarted by
recapturing dominant bits and repeating these steps until a message can be found.
4.7
Loading the Code
The first message transmitted by the Host contains three variables necessary to load the
code/data. Data bytes 0 and 1 contain the information for the TC1765's Bit Timing
Register (BTR). This provides the Host the ability to change these protocol parameters
to suit the individual user’s needs. However, the user must insure that the correct value
is sent; otherwise, communication could be halted. The TC1765 will re-initialize its CAN
module to these parameters and transmit a data frame with the identifier (data bytes 2
and 3) sent from the Host.
Data bytes 4 and 5 tells the TC1765 the number of code/data messages to receive. All
messages received from this point on will have their data bytes sequentially written into
the internal SPRAM starting at location C000 0004H. Since data bytes 4 and 5 are
defined by the Host, the Host has the ability to decide on how large of a program to load.
Therefore, the theoretical maximum number of code/data bytes that can be received is
equal to 524,280 (65535 * 8 code/data bytes). However, the size of the internal SPRAM
is 16 Kbytes which results in a maximum of 8,191 16-bit instructions.
Note: The bootstrap loader assumes all message data is valid. The Host should send its
code/data sequentially in multiples of 8 code/data bytes. The user is limited to
sending a maximum of 2047 messages.
Application Note
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AP3263
Understanding the TC1765 BootStrap Loaders
CAN
4.8
Exiting the Bootstrap Loader Mode
Once all messages have been received, the bootstrap loader will transfer program
execution to the user code by jumping to location C000 0004H (i.e. the first loaded
instruction). The Bootstrap Loader sequence is now terminated and the program that
was loaded from the Host is now executing.
While in bootstrap loader mode, it is also possible to execute normal user mode. This is
because the boot ROM is located in its own memory space.
4.9
Choosing the Baud rate for the Bootstrap Loader
When choosing a baud rate, the Master must determine what CAN baud rate is possible
for the TC1765 to detect. The major consideration in this determination is the operating
frequency of the TC1765. In general, it is recommended to select the slowest possible
baud rate for the initial message with a Sample Point (SP) at 80%. Once communication
has been established, the baud rate can be changed to a higher rate.
The bootstrap loader software is polling the CAN receive pin to determine the amount of
time that is required for a bit to be transmitted. The higher the ratio of CPU frequency to
CAN bit time, the greater the likelihood for early baud rate detection.
Once the bit time has been determined as described in Section 4.4, the algorithm for
determining the Host baud rate is started. The baud rate is determined by performing an
iterative loop using the parameters in Table 7, along with equations [2] and [3]. The first
objective of the algorithm is to find a solution that uses the maximum number of time
quanta (Ntq). This is done by looping through the three possibilities in Table 7 to get the
calculated timer value result for each possibility. If an exact match between the
calculated timer value and the measured timer value is found, then the loop will exit with
the current parameters. However, if an exact match is not found, then a search is made
to select the closest calculated value to the measured value. The process continues from
this point on as described in Section 4.6.
Table 7
Time Quanta Parameters for 80% Sample Point
Item
Ntq
Tseg1
Tseg2
SP
1
20
15
4
80.0%
2
15
11
3
80.0%
3
10
7
2
80.0%
Application Note
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Understanding the TC1765 BootStrap Loaders
CAN
The dependency between the system timer ticks and one CAN bit time (one Time
Quantum) is calculated with the following equations:
t CANbit
N tq = TimerValue = -----------------------f SystemClk
TimerValue
BPR =  -------------------------------- – 1


N tq
CalTimerValue = ( BPR + 1 ) • N tq
N tq = Sync + Tseg1 + Tseg2
[1]
[2]
[3]
[4]
Where:
BPR
Baud rate prescaler value
TimerValue
Number of System Timer ticks
Ntq
Number of time quanta per bit period
tCANbit
One CAN bit time
Tseg1
Number of time quanta before the sample point
Tseg2
Number of time quanta after the sample point
Sync
Synchronization segment (always equal to 1)
fSystemClk
CPU operating frequency
From the ISO-DIS 11898 standard, the following assumptions about the bit timing
parameters can be made.
8 ≤ t q ≤ 25
3 ≤ TSeg1 ≤ 16
2 ≤ TSeg2 ≤ 8
1 ≤ SJW ≤ 4
The value for SJW is always assumed to be one.
Application Note
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V1.0, 2002-03
AP3263
Understanding the TC1765 BootStrap Loaders
CAN
4.10
TwinCAN Boot Algorithm
Figure 14 shows a flowchart of the TC1765 frequency detection.
Figure 15 shows the Host / TC1765 Bootstrap Loader flow.
0DVWHU1RGH
6ODYH1RGH
VWDUWFRPPXQLFDWLRQ
7ZLQ&$1
CAN module is disabled
prepare CAN
communication
must know slave
parameters
Prepare to detect pulses
transmit message
(standard frame)
ID = 555H
Data0 = BTR_L
Data1 = BTR_H
Data2 = ID_L
Data3 = ID_H
Data4 = MES_CNT_L
Data5 = MES_CNT_H
Data6:7= 0x00
continuing transmission
until acknowledge is
successfully received by
Master Node
measure 100 dominate bus
periods (timer)
detect smallest timer value
No
Check to make sure there are
at least 5 smallest values
wait for successful
transmission
enough samples
Yes
CAN communication ready
YES
detect bit time
caculate baud rate
End
initialize TwinCAN in analyzing
mode with detected bit timing
(16R x MO, 1T x MO)
enable TwinCAN
CAN errors detected
No
disable analyzing mode
CAN communication ready
End
Figure 14
TC1765 Frequency Detection
Application Note
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V1.0, 2002-03
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Understanding the TC1765 BootStrap Loaders
CAN
Start
Host:
Chooses a baud rate that the Slave can determine with SP equal to 80%
Host:
Sends the appropriate standard CAN message
Slave:
CFG[3:0] pins are configured to enter TwinCAN bootstrap loader mode
CLKSEL[2:0] pins are configured to select the Slave’s system clock (PLL enabled)
Host:
Waits until CAN error state has changed to error passive
Releases PORST pin of the Slave (startup configuration is latched)
Slave:
Enters TwinCAN bootstrap loader mode
Slave:
Measures CAN bit timing and uses Analyzer Mode to detect the Host’s baud rate
No
Slave
has acknowledged the
message transmitted by the
Host?
Yes
Slave:
Transmits acknowledge message using Host specified Identifier
Host:
Transmits data/code information to slave
No
All messages
received?
Yes
Slave is
executing
downloaded
code
Figure 15
Host Boot Flow
Application Note
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V1.0, 2002-03
AP3263
Understanding the TC1765 BootStrap Loaders
CAN
Host message (error active)
Host message (error passive)
TC1765 TwinCAN module acknowledges the host message
TC1765 TwinCAN module transmits response to the host
Overview of the CAN Tx/Rx Sequence
Figure 16
CAN Plots of Data Sequences
Application Note
27
V1.0, 2002-03
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