Analog Aspects of Analog / Digital Converters

A pp l ic a ti on No te , V 1.0 , M ay 2 00 1
AP2428.01
A/D Converter
C500 and C166
Microcontroller Families
Analog Aspects
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
A/D Converter
Revision History:
2001-05
Previous Version:
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Page
V 1.0
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH
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Edition 2001-05
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AP2428.01
C500 / C166 Microcontroller Families
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
2.1
2.2
2.3
2.4
2.5
Transfer Characteristic and Error Definition . . . . . . . . . . . . . . . . . . . . . . 6
Ideal Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Differential Nonlinearity Error (DNLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Integral Nonlinearity Error (INLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
3.1
3.2
3.3
3.4
Principle of Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge-Redistribution Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Back Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
13
13
4
4.1
4.2
4.3
4.4
Calibration Mechanism (Error Correction) . . . . . . . . . . . . . . . . . . . . . .
Calibration Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disturbance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
16
5
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.3
5.4.3.1
5.4.3.2
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.6.1
5.6.2
5.6.3
Analog Input AN0 ... ANy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Model of the A/D Converter Input . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy at Sample Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Flow during Sample Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Balance between CAIN and CEXT . . . . . . . . . . . . . . . . . . . . . . .
Charge of CAIN and CEXT via RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . .
RASRC Calculation with (0 pF < CEXT < (2r - 1) * CAIN) . . . . . . . . . . . . . . .
Charge-Redistribution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation Example with (0 pF < CEXT < (2r -1) * CAIN) . . . . . . . . . . . .
Resistance of the Analog Source RASRC . . . . . . . . . . . . . . . . . . . . . .
Cycle Time tCYCLEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RASRC Calculation with (CEXT > (2r -1) * CAIN) . . . . . . . . . . . . . . . . . . . . .
External Capacitance CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Time tCYCLEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cutoff Frequency fC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation Example with (CEXT > (2r - 1) * CAIN) . . . . . . . . . . . . . . . . .
RASRC Calculation with (CEXT = 0pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistance of the Analog Source RASRC . . . . . . . . . . . . . . . . . . . . . . . .
Calculation Example with (CEXT = 0pF) . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation Example with the Formula in the Data Sheet . . . . . . . . . . .
17
17
19
20
20
22
23
25
26
27
27
27
28
28
28
30
30
32
32
33
34
Application Note
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6
6.1
6.1.1
6.1.2
6.2
6.2.1
6.3
6.3.1
6.4
Reference Voltage VAREF and VAGND . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sources for the Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage of the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . .
External Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAREF Calculation Including an External Capacitance . . . . . . . . . . . . . . .
Calculation Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAREF Calculation based on the Formula in the Data Sheet . . . . . . . . . . .
Calculation Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ratiometric Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
36
37
38
40
41
43
44
7
7.1
7.1.1
7.2
7.2.1
7.2.1.1
7.2.2
7.2.2.1
Overload and Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Current and Absolute Maximum Ratings . . . . . . . . . . . . . . . .
Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Current and Operating Conditions . . . . . . . . . . . . . . . . . . . . .
Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
47
47
47
48
48
8
8.1
8.2
8.3
8.4
8.5
PCB and Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component Placing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
49
49
49
50
50
9
Used Short Cuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Application Note
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AP2428.01
C500 / C166 Microcontroller Families
Introduction
1
Introduction
For analog signal measurement on most members of the C500 and C166 microcontroller
families, an A/D (Analog/Digital) converter with multiplexed input channels and a sample
and hold circuit has been integrated on-chip. Depending on the device type of the
C500/C166 Family, an 8-bit or 10-bit A/D converter with 4, 8, 10, 12, 15, 16 or 24
multiplexed input channels, is integrated. The A/D converter uses the method of
successive approximation.
In principle, the A/D converter can be divided in two parts, the analog interface (including
the converter with sample and hold circuit) and the digital part, which contains different
registers and the digital control unit. This Application Note provides basic information
and recommendations concerning the analog part of the A/D converter. Please refer to
the corresponding User’s manual for the description concerning the digital part of the A/D
converter.
Based on the history and evolution of the microcontrollers, there are different
implementations of the A/D converter available. This Application Note is referred to the
actual status of A/D converters, which are implemented in the C500/C166 Family. The
differences of the analog part concern mainly the values in the A/D converter
characteristics specified in the Data Sheet. For details, please use the corresponding
Data Sheet.
The resolution (r) of the A/D converter refers to the number of quantization levels, an
analog input voltage can be determined to. This number of smallest levels is given in bits
and one of them is an LSB. Figure 1 shows an example of an A/D converter with 1024
quantization levels. This A/D converter has a 10-bit resolution. An input voltage of 5 V is
quantized with a step size of 5 V / 2 10 = 4,88 mV.
This theoretical accuracy of an A/D converter is degraded by inaccuracies of the A/D
converter itself (total unadjusted error). Further the accuracy of the total A/D conversion
system is degraded by the involved external elements which are connected to the analog
input ANx and to the reference voltage VAREF.
It is the task of the system designer to keep the inaccuracies caused by the external
circuits as low as possible. This application note provides the necessary basic
information to optimize the external circuits of the A/D converter.
Application Note
5
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AP2428.01
C500 / C166 Microcontroller Families
Transfer Characteristic and Error Definition
2
Transfer Characteristic and Error Definition
The following diagrams show the ideal transfer characteristic of an A/D converter and the
error definition for the different kind of errors:
•
•
•
•
Offset error
Gain error
Differential nonlinearity error (DNLE)
Integral nonlinearity error (INLE)
The total unadjusted error (TUE) is specified in the Data Sheets of the C500 and C166
microcontrollers.
2.1
Ideal Transfer Characteristic
Figure 1 defines the ideal transfer characteristic for an A/D converter. The Ideal Transfer
Curve (1) transfers each input to an output.
The Ideal ADC Transfer Curve (2) includes a quantization error, since all analog input
values are presumed to exist, they must be quantized by partitioning the continuum into
discrete digital values. All analog values within a given range (quantization step) are
represented by the same digital value, which corresponds to the nominal mid- range
value. That is the reason for the quantization uncertainty of +/- 0.5 LSB, which is a
natural error and inherent to each A/D converter.
The quantization step size is 1 LSB = VAREF / 2r. According to the Ideal Transfer Curve
(1) the first digital transition, from 0 to 1, occurs at the analog value of 0.5 LSB. That is
why the first step width of the Ideal ADC Transfer Curve (2) is 0.5 LSB and the last step
width is 1.5 LSB. The inherent quantization error in relation to the analog input voltage
is shown in Figure 2
The total unadjusted error includes all A/D converter related inaccuracies like production
process deviations and internal noise.
The TUE consists of offset error, gain error, DNLE and INLE but it is not simply the sum
of individually measured errors. Since some errors of the ADC, like offset and gain error,
can compensate each other, the TUE can be far less than the absolute sum of all
individual errors. Figure 1 shows the definition of the TUE in relation to the Ideal ADC
Transfer Curve (1).
The real result of the A/D converter is in the range of Ideal ADC Transfer Curve (2) +/TUE. This area is shaded in Figure 1 and is between both TUE related to ideal ADC
Transfer Curves (3) and (4).
Application Note
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Transfer Characteristic and Error Definition
Digital Output
Ideal Transfer Curve
(1)
TUE related to ideal
Transfer Curve
3FF
(2)
Ideal ADC Transfer Curve
(3)
TUE related to ideal
ADC Transfer Curve
3FE
(4)
10 Bit Resolution
5
4
3
TUE related to ideal
Transfer Curve
+|TUE|
-|TUE|
TUE related to ideal
ADC Transfer Curve
2
1
0
0 0.5 1
2
3
4
5
1023
1024
Analog Input Voltage [LSB]
0.5 LSB Inherent
Quantization Error
Figure 1
1022
Ideal Transfer Characteristic
Quantization Error [LSB]
0.5
0
1
2
3
4
5
-0.5
1022
1023
1024
Analog
Input
Voltage
[LSB]
-1.0
Figure 2
Quantization Error
Application Note
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Transfer Characteristic and Error Definition
2.2
Offset Error
The offset error is the deviation from the Ideal ADC Transfer Curve at the lowest
transition level on the Real ADC Transfer Curve. It is the input voltage required to bring
the digital output to zero and can be measured by determining the first digital transition,
from 0 to 1, of the A/D converter. The offset error affects all codes by the same amount..
For the consideration in the figure below, all other kinds of errors (gain, DNLE, INLE) are
excluded.
Digital Output
Ideal Transfer Curve
3FF
3FE
Ideal ADC Transfer Curve
10 Bit Resolution
5
Real ADC Transfer Curve
including the Offset Error
4
3
2
1
0
0
1
2
3
4
5
1023
1024
Analog Input Voltage [LSB]
Offset Error
Figure 3
1022
Offset Error
Application Note
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Transfer Characteristic and Error Definition
2.3
Gain Error
The gain error is the difference between the slopes of the real ADC Transfer Curve and
the Ideal ADC Transfer Curve at the maximum digital out value. For the consideration in
the figure below, all other kinds of errors (offset, DNLE, INLE) are excluded.
Digital Output
Gain Error
3FF
Ideal Transfer Curve
3FE
Ideal ADC Transfer Curve
10 Bit Resolution
5
Real ADC Transfer Curve
4
3
2
1
0
0
1
2
3
4
5
1022
1023
1024
Analog Input Voltage [LSB]
Figure 4
Gain Error
Application Note
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Transfer Characteristic and Error Definition
2.4
Differential Nonlinearity Error (DNLE)
The differential nonlinearity error describes variations in the analog value between
adjacent pairs of digital numbers, over the full range of the digital output. If each
transition step width is exactly 1 LSB, the differential nonlinearity error is zero. If the
transitions are 1 LSB +/- 1 LSB, then there is the possibility of a missing codes. If a
missing code occurs then one value of the digital output is missing, e.g. the digital output
might jump from 0011 to 0101 and missing out 0100; See figure below.
If the differential nonlinearity error is less than 1 LSB, then a missing code is
automatically excluded. For the consideration in the figure below, all other kinds of errors
(offset, gain, INLE) are excluded.
Ideal Transfer Curve
Digital Output
3FF
Ideal Transfer Curve
ADC Transfer Curve
3FE
Real ADC Transfer Curve
10 Bit Resolution
5
Ideal ADC Transfer Curve
Missing Code
4
3
2
1
0
0 0.5 1
2
3
4
5
1022
1023
1024
Analog Input Voltage [LSB]
DNLE = 1 LSB
Figure 5
Differential Nonlinearity Error
Application Note
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Transfer Characteristic and Error Definition
2.5
Integral Nonlinearity Error (INLE)
The integral nonlinearity error is the maximum difference between the Ideal ADC
Transfer Curve and the adjusted Real ADC Transfer Curve (without offset- and gain
error). For the consideration in the figure below, DNLE is also excluded.
Digital Output
Ideal Transfer Curve
3FF
3FE
Ideal ADC Transfer Curve
10 Bit Resolution
5
Real ADC Transfer Curve
4
3
2
1
0
0 0.5 1
2
3
4
5
1022
1023
1024
Analog Input Voltage [LSB]
INLE = 1 LSB
Figure 6
Integral Nonlinearity Error
Application Note
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Principle of Conversion
3
Principle of Conversion
The A/D converter is based on the principle of successive approximation. It uses a
capacitor network in order to compare the analog input voltage with the actual digital
approximation of this voltage. The capacitor network is also used for the sample and hold
function. The conversion is performed in several steps. A total conversion consists of:
•
•
•
•
Sample phase
Charge-redistribution phase (conversion phase)
Calibration phase
Write back phase
The sequence of the different phases is shown in Figure 7. The total ADC conversion
time can be controlled via register ADCON (C166 Family). The block diagram in
Figure 8 is related to an A/D converter with 10 bit resolution and represents the principle
connections between the analog input ANx, conversion C-net, comparator and the result
register ADDAT.
Start of
Conversion
End of
Conversion
MSB
Sample
Phase
LSB
Charge-Redistribution Phase
Calibration
Phase
Write back
Phase
ADC Conversion Time
Figure 7
3.1
A/D Converter Timing
Sample Phase
During the sample phase, the conversion control unit connects the capacitors of the
conversion C-net to one of the analog input channels via a multiplexer. The capacitor
network is thus charged/discharged to the voltage level of the connected analog input
channel. The hold capacitor CHOLD at the comparator holds the analog input voltage
after sample phase.
Application Note
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Principle of Conversion
3.2
Charge-Redistribution Phase
At the end of the sample phase and with the start of the charge-redistribution phase, the
conversion C-net is disconnected from the analog input. The goal now is to reconstruct
the voltage level stored in the hold capacitor CHOLD by connecting the capacitors C9 to
C0 individually to VAREF or VAGND. As the capacitor network (conversion C-net) is binary
weighted (i.e. Cn = 2*Cn-1), the charge of the capacitors C9 to C0, corresponds directly
to the voltage level of the connected analog input channel. The digital value is found
successively starting from the most significant bit down to the least significant bit. The
comparator is used to decide whether the actual voltage of the capacitor Cn is below or
above the voltage stored in the hold capacitance. The charge-redistribution phase is
finished after 10 steps of successive approximation.
The conversion C-net for a 12-bit A/D converter consists of C11 to C0 and 12 steps are
required. The conversion C-net for a 8-bit A/D converter consists of C7 to C0 and 12
steps are required.
3.3
Calibration Phase
The conversion accuracy depends on the precision of the conversion C-net and the
offset voltage of the comparator. In order to correct the errors that are introduced through
process variations and offset voltage, an additional C-net (the calibration C-net) is used
together with a calibration control logic. A detailed description of the calibration phase is
shown in the chapter 4, Calibration Mechanism.
3.4
Write Back Phase
During the write back phase, the result of the successive approximation is copied to the
result register ADDAT. The duration of the write back phase is 4 TCL.
During the write back phase, the conversion C-net is precharged with approximately
VAREF / 2.
Note: Because of parasitic capacitances caused by the pads and the analog multiplexer,
the precharge voltage at the pins can differ from VAREF / 2.
Application Note
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Principle of Conversion
Comparator
ADDAT
CHOLD
Calibration C-Net
C7’
C6’
C5’
C4’
C3’
C2’
RAM
C1’
C0’
Calibration
Control
Conversion C-Net
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Conversion
Control
ANx
VAREF
VAGND
Figure 8
Block Diagram for the analog Part of a 10-bit A/D Converter with
Calibration and Conversion C-Nets
Application Note
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Calibration Mechanism (Error Correction)
4
Calibration Mechanism (Error Correction)
An automatic self-calibration mechanism is implemented in the A/D-converter in order to
compensate the offset error and to balance differences in the capacitive network. This is
due to production variations, which can cause linearity deviations of the A/D conversion.
The self-calibration mechanism consists of the calibration capacitor-net, the calibration
RAM and the calibration control unit; See Figure 8. The self-calibration includes two
kinds of calibrations:
• Offset Calibration is the adjustment of the offset error.
• Linearity Calibration is the binary weight adjustment between the capacitors of the
conversion capacitor-net.
4.1
Calibration Principle
The additional correction capacitor-net (calibration C-net) is used to add/subtract a
capacitive charge to the comparator input of the A/D converter. This correction C-net
allows an adjustment in the range of ± 4 LSB with a resolution of 1/32 LSB within ± 128
steps.
The same calibration C-net is used for both the offset and the linearity calibrations.
During offset calibration, the corrective charge, in order to zero-adjust the comparator, is
determined. During linearity calibration, for each of the binary weighted capacitors of the
conversion C-net, a correction value (with respect to the sum of the remaining
capacitors) is determined.
The results of the calibration are stored in the calibration RAM. During normal
conversion, the stored values are used to correct the measurement. For this purpose,
the calibration control unit is used to calculate the appropriate combination of the
calibration capacitors.
4.2
Reset Calibration
After a reset, the contents of the calibration RAM is cleared and the A/D converter
automatically starts an initial full calibration sequence (power-up calibration). Both the
offset and the linearity deviations are adjusted. This calibration sequence has a duration
of 3328*tBC (0.66 msec @ fCPU = 20 MHz with the reset values of register ADCON).
During the first quarter of this calibration sequence, a coarse adjustment with steps from
0.5 LSB down to 0.1 LSB is performed, which becomes more precise during the
following three quarters of the sequence with calibration steps of 0.03 LSB. This scheme,
guarantees a very fast reduction of the offset and linearity error.
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Calibration Mechanism (Error Correction)
Note: After reset the positive and negative analog reference voltages (VAREF and
VAGND) have to be stable and within the specified range, in order to perform a
correct reset calibration.
Note: The reset calibration can be interrupted by any conversion. In this case, the reset
calibration is lengthened by the conversion time. The calibration sequence is
performed with the actual values of register ADCON. A change of bit field ADCTC
(A/D Conversion Time Control) also changes the duration of the calibration
sequence.
During the reset calibration sequence the specified maximum TUE can be
exceeded.
Note: When entering IDLE or Slow Down Mode, before reset calibration is finished, the
reset calibration continues until it is finished. In this case, the Power Down current
increases. It is recommended to wait until reset calibration is finished, before
entering IDLE or Slow Down Mode.
4.3
Normal Calibration
During A/D converter operation, a re-calibration is performed after each conversion, in
order to perform an adaptation to changing operation conditions, e.g. temperature. This
re-calibration is performed in single steps, where a maximum change of ± 1/32 LSB of
the calibration value is possible.
4.4
Disturbance Filtering
Due to the way the calibration operation is implemented, a filtering of disturbances during
the calibration is achieved. For example noise on VAREF or VAGND can disturb
calibration, but instead of performing a full correction of a detected deviation (either
offset or linearity) in one cycle, the calibration circuit performs a step-by-step reduction
of the deviation. Thus, if during one calibration cycle a deviation caused by a disturbance
is detected, the last correction value will only be incremented or decremented by one
(1/32 LSB). As an example, if the disturbance would cause an offset deviation of 1 LSB,
then 32 calibration steps would be necessary to correct for this error. If, however, a
deviation occurs during one calibration cycle, but has vanished during the next
calibration cycle, the previous change of the correction value will be cancelled again. In
other words, a wrong calibration caused by disturbances can only occur if the
disturbance lasts for a long time.
Also, disturbances occurring during the reset calibration will be eliminated due to the
long calibration sequence and the re-calibration after each conversion.
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5
Analog Input AN0 ... ANy
Each application, where an analog voltage has to be measured, needs an accurate
calculation of the involved external elements. This is fundamental to ensure the
sufficiently charging of the A/D converter input capacitance CAIN to the same potential of
the analog source, during the sample time. An insufficient charging of CAIN causes an
additional inaccuracy (ErrorANx) to the TUE of the A/D converter.
This chapter shows how to calculate the external circuits for the analog inputs. The
derivation of the necessary formulas is followed by calculation examples.
Because of the different phases of a total conversion (sample- and charge-redistribution
time) the calculation examples are shared into different electrical models which fit best
to the values of the used external circuits.
The basis for the way of proceeding is the voltage waveform of analog input ANx which
can be observed during a conversion.
Note: A detailed solution of the calculation without a simplified electrical model leads to
a 2nd order differential equation and will not be discussed in the ApNote.
5.1
Electrical Model of the A/D Converter Input
Figure 9 is a strongly simplified block diagram of the A/D converter. The block diagram
includes only the relevant elements necessary for a calculation of the external circuits.
The A/D converter input capacitance CAIN contains the capacitors of the conversion Cnet and all parasitic capacitors which have to be considered for the calculation. The A/D
converter input capacitance CAIN is specified in the A/D converter characteristics in the
Data Sheet. The value of the actual design steps is CAIN_max = 33 pF. Please refer to the
Data Sheet for the exact value of the used microcontroller.
RAIN is the internal series resistance of the A/D converter. The value is RAIN = 250 Ω.
This value is not explicitly in the Data Sheet, but implicitly in the formula for the
calculation of the internal resistance of the analog source RASRC. The sample switch
represents an analog switch closed only during sample time. The multiplexer connects
the selected analog input ANx with the internal conversion C-net.
The external capacitance CEXT can be a real external capacitor for noise reduction or
only the parasitic capacitance caused by the signal line between analog source and A/D
converter input.
The analog voltage source is represented by an ideal voltage source V0 and a series
resistance RASRC.
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A/D Converter
Analog Source
AN0
ANx
VAINx
V0
RAIN Comparator
MUX
RASRC
Sample
ANy
CAIN
CEXT
VAGND
Central Analog Ground
Figure 9
Block Diagram of A/D Converter and Analog Source
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5.2
Accuracy at Sample Time
As already described in chapter "Principle of Conversion", a total conversion is divided
in two phases: the sample phase and the charge-redistribution phase. The total accuracy
of the A/D converter result depends on the TUE, the accuracy of VAREF and the voltage
level difference between analog source V0 and VCAIN (ErrorANx) at the end of the sample
phase. A detailed consideration of the voltage level at CAIN (or ANx, respectively) is the
condition to determine the correct values for RASRC, CEXT, sample time and cycle time
of a system.
The worst case voltage deviation for the system is the maximum voltage difference
between the precharge voltage of CAIN (approximately VAREF / 2) and V0 at the
beginning of the sample phase. This case is given for V0 = VAREF or V0 = VAGND.
Figure 10 shows the absolute voltage difference between V0 and CAIN (|V0 - VAREF / 2|)
at the beginning of the sample phase.
The formulas in this ApNote are all related to the possible absolute maximum
V0 = VAREF. The result can also be transformed to V0 = VAGND. Voltages used in the
calculations are all referred to VAGND.
|V0 - VAREF/2|
VAREF/2
VAREF/2
VAGND
Figure 10
V0
VAREF
Voltage Difference between V0 and CAIN (|V0 - VAREF / 2|) at the Start
of the Sample Time
Note: The assumed error (ErrorANx) used in this chapter (“Analog Input AN0 ... ANy”) for
the calculation examples is referred to the allowed maximum input voltage at ANx
(VAINx = VAREF). For input voltages at ANx smaller than VAREF the additional
inaccuracy at VAINx is proportional less than the value of ErrorANx used in the
example calculations. The real additional inaccuracy at VAINx is:
ErrorANx_real = (VAINx / VAREF) * ErrorANx
with the condition VAGND ≤ VAINx ≤ VAREF
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5.3
Charge Flow during Sample Time
The input impedance of the A/D converter is mainly capacitive (CAIN) with a small
resistive (RAIN) part. This capacitance, however, applies only to the selected analog
input pin ANx during the sample time. During the remaining time, the inputs are
extremely high impendance (e.g. typical leakage currents are in the range of some
10 nA). See specification in the Data Sheet: Input leakage current of the ADC.
During the sample phase, two different sequential processes are running. First, CAIN is
charged from CEXT and the voltages at CAIN and CEXT get the same value. Secondly,
the common voltage at CAIN and CEXT is adjusted to V0 via the resistance of the analog
source RASRC. Depending on the performed phases of the A/D converter different time
constants τ=have to be considered:
τ1 :
Time constant at the beginning of the sample time.
It contains CAIN, CEXT and RAIN
• τ2 : Time constant during sample time. It contains CAIN, CEXT and RASRC
• τ3 : Time constant during and after charge-redistribution phase.
It contains CEXT and RASRC
•
5.3.1
Charge Balance between CAIN and CEXT
The electrical model for τ1 is shown in Figure 11. The voltage at CAIN before switch
Sample is closed, is approximately VAREF/2 because of precharging CAIN at the end of
conversion. The voltage at CEXT is nearly V0 depending on the cycle time of the
conversion.
Sample
VAINx
Figure 11
CEXT
RAIN
VCAIN ~ VAREF/2
CAIN
Electrical Model of the A/D Converter during τ1
When switch Sample is closed, then a charge balance between CAIN and CEXT is done
with the time constant τ1; See Figure 11. Figure 13 presents the corresponding
waveform at ANx.
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τ1
C AIN ⋅ C EXT = R AIN ⋅ ------------------------------ C AIN + C EXT
The possible maximum value is τ1 = 8.25 ns @ CAIN = 33 pF and CEXT = infinite,
because RAIN and CAIN are fixed values of the A/D converter. For the calculation of the
sample time, which is in the range of some µs, the duration of time constant τ1 is in most
cases negligible (after 7.6*τ=the voltage error is less than 0.5 LSB). For typical values of
7.6*τ1 see Table 1.
Table 1
CEXT
7.6*τ1
Values for 7.6*τ1 @ CAIN = 33 pF and RAIN = 250 Ω
1 pF
10 pF
100 pF
1 nF
10 nF
100 nF
1 µF
1.84 ns
14.58 ns
47.14 ns
60.70 ns
62.49 ns
62.68 ns
62.70ns
The charge balance between CAIN and CEXT causes a voltage jump V∆= at the analog
input ANx. Depending on the voltage on ANx when the sample phase starts, the voltage
can be increased or decreased. The example of Figure 13 uses the worst case
V0 = VAREF. At the end of 7.6*τ1 the voltage at ANx is reduced (or increased) by the
value V∆ with an accuracy of 0.5 LSB. The charge balance between CEXT and CAIN
results in the formula for V∆:
C AIN ⋅ ( V 0 – V CAIN )
V ∆ = ------------------------------------------------C AIN + C EXT
Table 2
Typical Values for the Voltage Jump V∆=@ CAIN = 33 pF,
Precharge: V0 - VCAIN = 2.5 V and V0 = VAREF
CEXT
1 pF
10 pF
100 pF
1 nF
10 nF
100 nF
1 µF
V∆
2.4 V
1.9 V
0.6 V
80 mV
8.2 mV
0.8 mV
0.08 mV
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5.3.2
Charge of CAIN and CEXT via RASRC
The electrical model during sample time with τ2 is shown in Figure 12. In this electrical
model RAIN is neglected because in typical systems RASRC >> RAIN. The voltage at
CAIN and CEXT is defined by V0 and V∆ at the beginning of the second phase (’startvoltage’ = V0 - V∆).
RASRC
V0
CEXT
Figure 12
CAIN
Electrical Model of the A/D Converter during τ2
After V∆= has reached the absolute maximum value, CEXT and CAIN are charged via
RASRC from V0 with the time constant τ2.
τ2
Application Note
= R ASRC ⋅ ( C AIN + C EXT )
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5.4
RASRC Calculation with (0 pF < CEXT < (2r - 1) * CAIN)
For reliable results it must be assured that during the sample time the input capacitance
CAIN is completely charged to the desired value, which is then digitized by the converter.
Under worst case conditions this capacity must be charged or discharged by the half
input voltage when V0 = VAREF or V0 = VAGND.
The input capacitance CAIN of the A/D converter, the external capacitance CEXT and the
resistance of the analog source RASRC form an RC lowpass filter, which has the charging
function VS(t). In normal systems, the sample time tS >> τ1, therefore τ1 is neglected in
the formula for VS(t). The waveform is shown in Figure 13.
V S (t) = V AREF – V ∆ ⋅ e
-t
------τ2
The voltage on ANx at the end of the sample time can also be described with the formula
VS(tS). The ErrorANx describes the maximum allowed deviation between the voltage on
ANx and V0 when the sample time is finished. An assumed ErrorANx of 0.5 LSB is
equivalent to 9.76 mV / 2.44 mV / 0.61 mV @ VAREF = 5 V and 8-bit / 10-bit / 12-bit A/D
converter resolution.
V S (t s ) = V AREF – Error ANx
Now it is possible to calculate the maximum value of the analog source resistance
RASRC. The formula for RASRC assumes that RAIN = 0 Ω.
ts
R ASRC = --------------------------------------------------------------------V∆
( C AIN + C EXT ) ⋅ ln ---------------------Error ANx
The formula is only valid for: V∆ / ErrorANx > 1
An assumed maximum ErrorANx = LSB / 2 leads to CEXT < (2r - 1) * CAIN
Depending on the A/D converter resolution the relations between CEXT and CAIN for the
calculation of RASRC are:
8-bit resolution:
10-bit resolution:
12-bit resolution:
Application Note
0 pF <ΙCEXT < 255 * CAIN
0 pF <ΙCEXT < 1023 * CAIN
0 pF <ΙCEXT < 4095 * CAIN
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VAIN
τ2
V0 = VAREF
τ3
ErrorANx
VS(t)
VS(tS)
Sampled
Voltage
V∆
V0 - V∆
τ1
τ2
t
tS
tCR
tC
tCYCLEn
tS
: Sample time
tC
: Conversion time
tCYCLEn : Cycle time of channel n
τ1,=τ2,=τ3 : Time constants
V0
: Voltage of the analog source
tCR
: Charge-redistribution time (conversion phase)
V∆============: Voltage jump at the start of the sample phase
ErrorANx : Voltage deviation between sampled voltage and
voltage of the analog source
Figure 13
Voltage Waveform at ANx
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5.4.1
Charge-Redistribution Time
During the charge-redistribution time, the Sample switch is open and the external
capacitance CEXT is charged via the resistor of the analog source RASRC.
RASRC
V0
CEXT
Figure 14
Electrical Model of the A/D Converter during τ3
The time constant during and after charge-redistribution time is τ3.
τ3
= R ASRC ⋅ C EXT
While the external capacitance CEXT is charged via RASRC, the A/D converter performs
the successive approximation (charge-redistribution). This is the transformation of the
analog voltage into a digital value. The reference for the transformation is the reference
voltage at pin VAREF referred to VAGND. It is very important for an exact conversion result
to hold the reference voltage and the reference ground on a constant level during the
charge-redistribution time. More details can be found in the chapter "Reference Voltage
VAREF and VAGND".
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5.4.2
Cycle Time
The cycle time tCYCLEn is the duration from the start of a conversion to the next
conversion start of the same analog channel. The figure below shows the relation
between the conversion time of an analog channel and the cycle time.
chx
chy
chz
chx
tCx
tCy
tCz
tCx
tCYCLEn
tCn
: Conversion time of analog channel n
tCYCLEn : Cycle time of analog channel n
chn
Figure 15
: analog channel n
Cycle Time
For continuous conversion mode of a channel, the conversion time tC can be equal to
the cycle time tCYCLEn. The cycle time of consecutive conversions is important for the
calculation of the voltage on CEXT at the start of next conversion. The voltage difference
between the analog source V0 and the analog input ANx at the start of a conversion
should be 0 V or negligible. The recommendation is:
t CYCLE ≥ 7.6 ⋅ τ 3 + t s
Note: After 7.6 * τ3 the remaining deviation from V0 is 0.049% of the assumed ErrorANx
for VS(tS).
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5.4.3
Calculation Example with (0 pF < CEXT < (2r -1) * CAIN)
The assumed values used in the example are:
CAIN
RAIN
CEXT
ErrorANx
= 33 pF,
tS = 1.28 µs,
= 250 Ω,
tC = 7.8 µs,
= 200 pF,
= 0.5 LSB10 = VAREF / 2048 = 2.44 mV
VAREF = V0 = 5 V,
r = 10 (10-bit resolution),
The calculation results in the values for RASRC and tCYCLEn.
5.4.3.1
Resistance of the Analog Source RASRC
First the voltage jump V∆ during the sample phase is calculated:
V∆ = (CAIN * (VAREF - VAREF/2)) / (CAIN + CEXT)
V∆ = (33 pF * (5 V - 2.5 V)) / (33 pF + 200 pF)
V∆ = 354 mV
The allowed maximum resistance of analog source RASRC is:
RASRC = tS / ((CAIN + CEXT) * ln(V∆ / ErrorANx))
RASRC = 1.28 µs/ ((33 pF + 200 pF) * ln(354 mV / 2.44 mV))
RASRC = 1103 Ω
The table below shows the different results of RASRC with the assumed values used in
the example.
Maximum Values for RASRC and different CEXT
Table 3
CEXT[pF]
RASRC [kΩ]
1
20
40
60
80
100
150 200 250 500 1000
5.4 3.7 2.9 2.3 2.0
1.7
1.3
1.1
0.9
0.6
0.35
10000
0.1
Note: The capacitive load at the analog inputs ANx should be as small as possible
because it reduces the allowed resistance of the analog source RASRC; See
Table 3. The only exception is the use of a very high external capacitance, which
supplies the A/D converter with the necessary charge during the sample phase.
5.4.3.2
Cycle Time tCYCLEn
The recommended minimum value of the cycle time is
tCYCLEn = 7.6 * RASRC * CEXT + tS
tCYCLEn = 7.6 * 1103 Ω * 200 pF + 1.28 µs
tCYCLEn = 2.95 µs
The calculated cycle time is smaller than the conversion time and, in that case,
continuous conversion of this analog channel is possible without inserting a waiting
period to charge the external capacitance CEXT.
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5.5
RASRC Calculation with (CEXT > (2r -1) * CAIN)
The selected external capacitance has to be high enough so the total charge, which is
necessary to load the internal C-net (CAIN) of the A/D converter, is supplied by the
external capacitor CEXT. The considerations below include the value of the external
capacitance CEXT with respect to the assumed maximal ErrorANx caused by the CEXT
and the necessary time tCYCLEn to reload the external capacitor.
5.5.1
External Capacitance CEXT
The calculation of the external capacitance CEXT is based on the assumption that
VAREF - V∆ is the sampled voltage and V∆= is the maximum allowed ErrorANx; See
Figure 16. After the charge balance (voltage jump, V∆= ) the voltage change at the
capacitors during the sample phase is extremely small because of the high time constant
τ3 of the external capacitance and the resistance of the analog source.
The example is calculated with the assumption of a maximum allowed error,
ErrorANx = LSBr / 2.
Error = LSBr / 2
Error = VAREF / (2r * 2)
Error > V∆ = (CAIN * (VAREF - VAREF/2)) / (CAIN + CEXT)
CEXT > (2r - 1) * CAIN
Depending on the A/D converter resolution the relations between CEXT and CAIN for the
calculation of RASRC are:
8-bit resolution:
10-bit resolution:
12-bit resolution:
CEXT > 255 * CAIN
CEXT > 1023 * CAIN
CEXT > 4095 * CAIN
The condition CEXT > (2r - 1) * CAIN allows a free choice of the sample time tS without
consideration of the resistance of the analog source RASRC but RASRC has a direct
influence on the cycle time tCYCLEn of the conversion.
5.5.2
Cycle Time tCYCLEn
The calculation of the cycle time takes into account that the external capacitor is not
totally charged to the voltage of the analog source V0 (worst case V0 = VAREF or
V0 = VAGND) but a small voltage rest VR is missing. See Figure 16.
With the condition CAIN << CEXT the formula for V∆=can be simplified:
V∆ = (CAIN * (VAREF - VAREF/2)) / (CAIN + CEXT)
V∆ ~ CAIN * VAREF / 2 * CEXT
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V∆ + VR ≤ ErrorANx
The condition
with
VR = VAREF - VC(tCYCLEn)
is based on Figure 16. The charge curve VC(t) of the capacitor CEXT via the resistance
of the analog source RASRC is:
V C (t) = V AREF – Error ANx ⋅ e
-t
------τ3
With an assumed maximum error of LSBr / 2 (ErrorANx = (VAREF / 2r) / 2) and with
τ3 = RASRC * CEXT the formulas result in the relation:
C EXT
t CYCLE ≥ R ASRC ⋅ C EXT ⋅ ln ----------------------------------------r
C EXT – 2 ⋅ C AIN
This formula is only valid for CEXT > 2r * CAIN
VAIN
tCYCLEn
V0 = VAREF
tCYCLEn
VR
ErrorANx
VC(tCYCLEn)
VC(t)
V∆
Sampled
Voltage
t
tCYCLEn : Cycle time of channel n
V0 : Voltage of the analog source
VC(t)=========: Charge curve for CEXT
VR : Voltage rest at the end of tCYCLEn
V∆============: Voltage jump at the start of the sample phase
ErrorANx : Voltage deviation between sampled voltage and
voltage of the analog source
Figure 16
Voltage at CEXT with High Capacitance for Periodical Conversions
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5.5.3
Cutoff Frequency fC
The resistance of the analog source and the external capacitance CEXT act as a lowpass filter with the cutoff frequency fC. A check is necessary whether the cutoff frequency
fits to the frequency of the analog source. If the relation between A/D converter cycle
frequency (fCYCLE = 1 / tCYCLEn) and the cutoff frequency is fCYCLE / fC = 0.1 then the
analog signal is damped with 5 o/oo (~1 LSB).
1
f C = ----------------------------------------------2 π ⋅ R ASRC ⋅ C EXT
Note: If the external circuit reaches the cutoff frequency then the voltage of the analog
source V0 is damped with the factor -3 dB (VAIN ~ 0.7 * V0 @ cutoff frequency fC).
5.5.4
Calculation Example with (CEXT > (2r - 1) * CAIN)
The assumed values used in the example are:
CAIN
RAIN
RASRC
ErrorANx
= 33 pF,
tS
= 1.28 µs,
= 250 Ω,
tC
= 7.8 µs,
= 20 kΩ,
CEXT = 100 nF
= 0.5 LSB10 = VAREF / 2048 = 2.44 mV,
VAREF = V0 = 5 V,
r = 10 (10-bit resolution),
(CEXT = 3030 * CAIN)
The calculation results in the value of cycle time tCYCLEn and cutoff frequency fC. The
values of the external capacitance CEXT and resistance of the analog source RASRC are
in a fixed relation with the cycle time tCYCLEn:
tCYCLEn ≥ RASRC * CEXT * ln(CEXT / (CEXT - 2r * CEXT))
tCYCLEn ≥=20 kΩ=* 100 nF * ln(100 nF / (100 nF - 210 * 100 nF))
tCYCLEn ≥=0.82 ms
The cutoff frequency is calculated via:
fC = 1 / (2 * π=* RASRC * CEXT)
fC = 1 / (2 * π=* 20 kΩ=* 100 nF)
fC = 80 Hz
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Table 4 includes calculation results of the cycle time in [ms] for different values of CEXT
and RASRC with the assumed values of the example (ErrorANx = 0.5 LSB10).
Table 4
Cycle Time tCYCLEn for Different Values of CEXT and RASRC
RASRC [kΩ]
tCYCLEn
[ms]
CEXT [nF]
34
40
50
75
100
500
1000
10000
1
0.17
0.07
0.06
0.04
0.04
0.03
0.03
0.03
5
0.87
0.37
0.28
0.22
0.21
0.17
0.17
0.17
10
1.73
0.75
0.56
0.45
0.41
0.35
0.34
0.34
15
2.60
1.12
0.84
0.67
0.62
0.52
0.52
0.52
20
3.47
1.49
1.13
0.90
0.82
0.70
0.69
0.68
35
4.33
1.86
1.41
1.12
1.03
0.87
0.86
0.85
30
5.20
2.24
1.69
1.35
1.24
1.05
1.03
1.02
40
6.93
2.98
2.25
1.80
1.65
1.40
1.38
1.35
50
8.66
3.73
2.82
2.25
2.06
1.75
1.72
1.69
100
17.33
7.45
5.63
4.49
4.12
3.50
3.44
3.38
Table 5 includes calculation results of the cutoff frequency in [Hz] for different values of
CEXT and RASRC with the assumed values of the example (ErrorANx = 0.5 LSB10).
Table 5
Cutoff Frequency fC for Different Values of CEXT and RASRC
RASRC [kΩ]
fC
[Hz]
CEXT [nF]
34
40
50
75
100
500
1000
10000
1
4681
3979
3183
2122
1592
318
159
16
5
936
796
637
424
318
64
32
3.2
10
468
398
318
212
159
32
16
1,6
15
312
265
212
141
106
21
11
1,1
20
234
199
159
106
80
16
8.0
0.8
35
187
159
127
85
64
13
6.4
0.6
30
156
133
106
71
53
11
5.3
0.5
40
117
99
80
53
40
8.0
4.0
0.4
50
94
80
64
42
32
6.4
3.2
0.3
100
47
40
32
21
16
3.2
1.6
0.2
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Analog Input AN0 ... ANy
5.6
RASRC Calculation with (CEXT = 0pF)
In this case, which is in real systems hard to realize, the external capacitance is
neglected. The electrical model is shown in Figure 17. It can be used for a rough
estimation of the external components if the value of CEXT is nearly zero pF. The internal
C-net capacitance of the A/D converter is directly charged via RASRC and RAIN.
RASRC
RAIN
CAIN
V0
Figure 17
5.6.1
Electrical Model of the A/D Converter during τ2 with CEXT = 0 pF
Resistance of the Analog Source RASRC
When the external capacitance is CEXT = 0 pF then time constant τ1 = 0 s and the
maximum voltage jump V∆=at the beginning of the sample time is approximately VAREF/2,
equal to the precharge value of the internal C-net.
V∆ = (CAIN * (VAREF - VAREF / 2)) / CAIN
V∆ = VAREF / 2
The resistance of the analog source RASRC, is calculated via the formula for systems
with a small external capacitance but without CEXT and with RAIN.
ts
R ASRC = -------------------------------------------- – R AIN
V∆
C AIN ⋅ ln ---------------------Error ANx
The calculation of the cycle time is not necessary because only during sample time, is
the internal C-net connected to the analog source. In the other phases of the cycle time,
the internal C-net is disconnected from the analog source. Therefore, no capacitance
has to be charged via RASRC until the start of the next sample time.
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Analog Input AN0 ... ANy
5.6.2
Calculation Example with (CEXT = 0pF)
The calculation example gives a rough estimation for the allowed maximum of RASRC if
CEXT is nearly zero pF. The assumed values used in the example are:
CAIN
RAIN
CEXT
ErrorANx
= 33 pF,
tS =1.28 µs,
= 250 Ω,
tC = 7.8 µs,
= 0 pF,
= 0.5 LSB10 = VAREF / 2048 = 2.44 mV,
VAREF = V0 = 5 V,
r = 10 (10-bit resolution),
The calculation results in the value for RASRC with V∆ = VAREF / 2.
RASRC = tS / (CAIN * ln(V∆ / ErrorANx)) - RAIN
RASRC = 1.28 µs / (33 pF * ln(2.5 V / 2.44 mV)) - 250 Ω
RASRC = 5345 Ω
The table below includes the maximum values for RASRC and different sample times with
the assumed values of the example:
Table 6
Maximum Values for RASRC and sample Times tS @ CEXT = 0 pF
tS [µs]
1
2
3
4
5
6
7
8
9
10
RASRC [kΩ]
4.1
8.5
12.9
17.2
21.6
26.0
30.4
34.7
39.1
43.5
Note: The leakage current specified in the Data Sheet can have an influence to the
accuracy of the analog input voltage, when the values of RASRC exceeds a certain
limit. This limit depends on the allowed inaccuracy referred to VAINx which is given
by the system demands. See chapter “Overload and Leakage Current”.
Application Note
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Analog Input AN0 ... ANy
5.6.3
Calculation Example with the Formula in the Data Sheet
The A/D converter Characteristics in the Data Sheet (example for C166 Family) include
the formula for the calculation of the maximum ’Internal resistance of analog source’.
With tS in ns and RASRC in kΩ the formula is:
RASRC ≤ tS / 450 - 0.25
This formula in the C166 Family Data Sheets is based on the assumption, that the analog
input ANx is only loaded with a small external parasitic capacitance: CEXT < 65 pF. For
systems with an external capacitance, which exceeds this value, the external
components have to be calculated as shown in the previous chapters.
The table below includes the maximum values for RASRC calculated with the formula in
the Data Sheets of the C166 Family.
Table 7
Maximum Values for RASRC and sample Times tS @ CEXT = 65 pF
tS [µs]
1
2
3
4
5
6
7
8
9
10
RASRC [kΩ]
2.0
4.2
6.4
8.6
10.9
13.1
15.3
17.5
19.8
22.0
Note: The leakage current specified in the Data Sheet can have an influence to the
accuracy, see note at Table 6.
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Reference Voltage VAREF and VAGND
6
Reference Voltage VAREF and VAGND
During the charge-redistribution phase, and also during the calibration phase, each
group of capacitors from the C-net is individually switched to either VAREF or VAGND.
Because of this switching and the according charge transfers in the C-net, the A/D
converter requires a dynamic current at pin VAREF.
Thus, the resistance of the voltage reference source has to be low enough to supply the
current for the charge-redistribution- and calibration phase. The external circuit at VAREF
has a direct influence to the required resistance of the voltage reference. If an external
capacitance CAREF, between VAREF and VAGND, is used then the voltage reference has
to supply a small continuous current to charge the external capacitor. The necessary
peak current during the charge-redistribution phase is supplied by the external
capacitance CEXT. The continuous current and the charge duration (tCYCLE) have to be
high enough to fill the external capacitance to a sufficient voltage level before the next
charge-redistribution phase starts.
If there is no external capacitance between VAREF and VAGND then the voltage reference
has to supply the peak current directly. The maximum allowed resistance RAREF
between the voltage reference VRF and VAREF using no external capacitance CAREF is
specified in the Data Sheets of the C500/C166 Family.
The specified value for RAREF in the Data Sheet is the worst case for the calculation of
the minimum sourcing peak current, which has to be supplied by the voltage reference.
V RF
I AREF ≥ ---------------R AREF
Application Note
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Reference Voltage VAREF and VAGND
6.1
Sources for the Voltage Reference
Depending on the system demands, several different kinds of voltage references can be
used in a system. The supply voltage of the microcontroller can be selected for the
reference voltage, but the accuracy is in percentage range. The accuracy of an external
high precision voltage reference is in the per mille range.
6.1.1
Supply Voltage of the Microcontroller
In most systems, the voltage reference used for the A/D converter is the supply voltage
VDD of the microcontroller. The typical accuracy of voltage regulators is 2 %; See power
semiconductor family TLE42xx from Infineon Technologies.
When using the digital supply voltage of the microcontroller, it is recommended to insert
a low pass filter between VDD and VAREF for the voltage reference; See figure below. The
low pass filter suppresses noise on pin VAREF to improve the accuracy of the A/D
converter results.
RAREF
VAREF
CAREF
Power
Supply
Tantalum
Ceramic
Central
Analog
Ground
GND
VAGND
Microcontroller
VDD
5V
VSS
Central Digital Ground
Figure 18
Supply Voltage used for Voltage Reference
The values of the capacitance CAREF and the resistor RAREF depend on the
characteristics of the system. Typical values are RAREF = 47 Ohm and CAREF = 100 nF
@ r = 10 and CAIN = 33 pF. The cutoff frequency of this low pass filter is fC = 34 kHz. If
there is noise on the system supply voltage with a very low frequency, then the cutoff
frequency can be reduced via an appropriate tantalum capacitance in parallel to CAREF,
which stabilizes the voltage reference.
Note: The impedance and the noise caused by the connection between Central Analog
Ground and Central Digital Ground should be as low as possible.
Application Note
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Reference Voltage VAREF and VAGND
6.1.2
External Voltage Reference
The source for an external voltage reference can be a standard supply voltage with
increased accuracy or with less noise. For systems where a high accuracy is demanded,
high precision voltage reference can be used with a typical accuracy in the range of
2.5 mV ... 20 mV.
VDD
RAREF
5.000 V
VAREF
CAREF
Tantalum
Ceramic
GND
VAGND
Central
Analog
Ground
Power
Supply
5V
VDD
GND
VSS
Microcontroller
Voltage
Reference
Central Digital Ground
Figure 19
External Voltage Reference
Note: If the supply voltage of the microcontroller and the voltage reference of the A/D
converter are switched on and off at different times, then it is very important that
the voltage reference is switched on or off only when the supply voltage of the
microcontroller is on otherwise the voltage reference supplies the system with
current via the ESD clamp diode. In that case, it is necessary to reduce the
overload current to the specified absolute maximum ratings; See chapter overload
and leakage current. The overload current can be reduced via a resistor or a
diode. If the additional external clamp resistor causes an unacceptable additional
error at VAREF then an external clamp diode should be used.
Application Note
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Reference Voltage VAREF and VAGND
6.2
RAREF Calculation Including an External Capacitance
The calculation is based on the assumption that there is an external capacitance CAREF
between VAREF and VAGND. The selected external capacitance has to be high enough
that the total charge, which is necessary to load the internal C-net (CAIN) for a total
conversion phase, is supplied by the external capacitor CAREF.
Voltage
Reference
IAREF
RAREF_INT
A/D Converter
VERROR
VAREF
RAREF
VRF
CAREF
RAIN
VAREF
tbit_conversion
CAIN
VAGND
Central Analog Ground
Figure 20
A/D Converter during Conversion Phase with CAREF
The following considerations include the value of the external capacitance CAREF with
respect to the assumed maximum voltage error at VAREF (ErrorAREF) caused by CAREF
and the necessary time tCYCLE to reload the external capacitor.
The relation between the external capacitance CAREF, the internal C-net CAIN and the
assumed maximum error caused by CAREF is:
C AREF ≥ 2
with:
r = 8: 8-bit resolution
r = 10: 10-bit resolution
r = 12: 12-bit resolution
Application Note
r+E
⋅ ( C AIN ) ⁄ 2
E = 0: ErrorAREF = 1 LSBr
E = 1: ErrorAREF = LSBr / 2
E = 2: ErrorAREF = LSBr / 4
38
ErrorAREF = 1 / 2E LSBr
LSBr
= VAREF / 2r
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Reference Voltage VAREF and VAGND
Note: The maximum voltage error (ErrorAREF) at VAREF caused by CAREF is referred to
the allowed maximum input voltage at ANx (VAINx = VAREF). For input voltages at
ANx smaller than VAREF the additional inaccuracy at VAINx is proportional less
than the value of ErrorAREF used in the example calculations. The real additional
inaccuracy at VAINx is:
ErrorAREF_real = (VAINx / VAREF) * ErrorAREF
with the condition VAGND ≤ VAINx ≤ VAREF
The condition (CAREF ≥ 2r+E CAIN / 2) allows a free choice of the A/D converter basic
clock tBC but the cycle time tCYCLE has a direct influence on the accuracy of the
conversion. The cycle time has to be long enough to recharge the external capacitance
CAREF before the next charge-redistribution phase is started.
The external capacitance CAREF has to be charged from the voltage reference. The
minimum current, which is drawn from the voltage reference, is based on the charge that
is necessary for a complete conversion. The charge Q for a complete chargeredistribution phase and a calibration phase is:
Q = C AIN ⋅ V AREF
The current for the voltage reference depends on the minimum cycle time for a total
conversion:
Q
I AREF = ----------------t CYCLE
The external resistance RAREF between the voltage reference and the input VAREF of the
A/D converter has an enormous influence on the accuracy. This resistor should be
chosen as small as possible! Because the continuous current IAREF causes a voltage
difference VERROR between the voltage reference VRF and the reference voltage input
VAREF of the A/D converter; See Figure 20.
V ERROR = R AREF ⋅ I AREF
Application Note
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Reference Voltage VAREF and VAGND
6.2.1
Calculation Example:
The assumed values used in the example are:
CAIN = 33 pF,
tBC = 160 ns,
RAIN = 250 Ω,
r
= 10, (10-bit resolution)
VRF = 5 V,
tCYCLE = 7.8 µs (C166 Family: minimum time @ fCPU = 20 MHz),
E = 2, ErrorAREF = 0.25 LSB, VERROR = VRF / 4096 = 1.22 mV
The value for the external capacitance between VAREF and VAGND is:
CAREF ≥ 2 r+E * CAIN / 2
CAREF ≥ 210+2 * 33pF / 2
CAREF ≥ 68 nF
Note: A typical recommendation for the value of the external capacitance is
CAREF = 100 nF
With the assumption VAREF = VRF, the minimum continuous current which has to be
supplied by the voltage reference is:
IAREF ≥=CAIN * VAREF / tCYCLE
IAREF ≥=33 pF * 5 V / 7.8 µs
IAREF ≥=21µA
The allowed maximum value for the resistor RAREF between voltage reference VRF and
input VAREF of the A/D converter is:
RAREF ≤=VERROR=/=IAREF
RAREF ≤ 1.22 mV / 21µA
RAREF ≤=58 Ω
Note: In case of an overload condition, it is possible that RAREF has to be increased, to
limit the overload current to the specified values. If that value of RAREF exceeds
the demanded error of the system, an external diode between VAREF and VDD can
reduce the overload current; See Figure 19.
Application Note
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Reference Voltage VAREF and VAGND
6.3
RAREF Calculation based on the Formula in the Data Sheet
The calculation of RAREF in the Data Sheets of the C500/C166 Family is based on the
assumption that there is no external capacitance between VAREF and VAGND. The
electrical model for the calculation is shown in the figure below.
Voltage
Reference
IAREF
A/D Converter
VERROR
Comparator
VAREF
RAREF_INT
RAREF
VRF
RAIN
VMSB
VAREF
CMSB
CLSB
CAIN
Conversion
Control
VAGND
Central Analog Ground
Figure 21
A/D Converter during Conversion Phase without CAREF
During charge-redistribution time (successive approximation), all capacitors of the A/D
converter are charged with VAREF/2 and compared with the sampled voltage from analog
input ANx. The successive approximation is started with the MSB and finished with the
LSB. The capacitor of the MSB needs most charge from the voltage reference due to the
binary weighting. The available time to charge the MSB to VAREF/2 and to compare the
MSB voltage with the sampled voltage is 4*tBC (tBC: Basic Clock frequency can be
controlled via register ADCON). Typically half the time can be used to charge MSB to
VAREF/2 (value depends on device type and on technology). The other half is necessary
for the comparison of the values by the comparator of the A/D converter.
The worst case for the maximum allowed resistance between voltage reference VRF and
input VAREF of the A/D converter is the conversion of the MSB. The capacitance CMSB
is charged with VAREF/2 and the voltage wave form at the comparator input is:
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Reference Voltage VAREF and VAGND
–t
---------------------------------------------------------------------
(R
+R
) ⋅ C MSB
V MSB (t) = ( V AREF ⁄ 2 ) ⋅ 1 – e AREF AIN
The maximum allowed value for RAREF with (VMSB(tBC) = VAREF/2 - ErrorMSB) is:
t BC ⋅ 2
– R AIN
R AREF ≤ -------------------------------------------------------V AREF
C MSB ⋅ ln ------------------------------Error MSB ⋅ 2
The figure below shows the comparator voltage VMSB(t) during the conversion of the
MSB. The conversion of the MSB lasts 4*tBC.
V
VAREF
ErrorMSB
2
VMSB(t)
VMSB(2*tBC)
t
tCHARGE
tCOMPARE
4 * tBC
tCHARGE : time to charge the MSB capacitance to VAREF/2 within 2*tBC
tCOMPARE : time to compare MSB voltage with sampled input voltage ANx within 2*tBC
Figure 22
Comparator Voltage during Conversion of MSB
The formula in the Data Sheet can be derived from the relation above. The typical value
CMSB of a 16-bit microcontroller used for the calculation is CMSB = 16.5 pF
(CMSB = CAIN / 2). The assumed maximum ErrorMSB caused by RAREF is
LSB/2 = VAREF/(2*210).
Application Note
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Reference Voltage VAREF and VAGND
t BC
- – R AIN
R AREF ≤ ---------------------12
57 ⋅ 10
This relation rounded with RAREF in kΩ and tBC in ns results in the Data Sheet formula:
RAREF ≤ΙtBC / 60 - 0.25
6.3.1
Calculation Example:
For a system using an fCPU = 25 MHz and a tBC = 160 ns the allowed maximum value
for RAREF is:
RAREF =Ι160 ns / 60 - 0.25
RAREF =Ι2.4 kΩ
with RAREF in kΩ and tBC in ns
The minimum current which has to be supplied by the voltage reference is:
IAREF ≥ VAREF / RAREF
IAREF ≥Ι5 V / 2400 Ω
with VAREF = 5 V
IAREF ≥Ι2.1 mA
The calculated current is not a continuous one. It is a peak current which flows only at
the beginning of MSB conversion and becomes smaller with each converted bit down to
the LSB.
Note: This value of RAREF assumes that no external capacitance between VAREF and
VAGND is used.
Application Note
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Reference Voltage VAREF and VAGND
6.4
Ratiometric Configuration
In a non-ratiometric configuration there is no relation between the voltage of the analog
source and the reference voltage at pin VAREF. Both, the accuracy of the reference
voltage and the accuracy of the analog source have an influence to the accuracy of the
total A/D conversion system, because any changes in the supply voltage of the analog
source results in a change at the analog input voltage ANx seen by the A/D converter.
Since the voltage reference is independent from the analog source excitation, the ADC
conversion result will reflect the changed excitation
Figure 23 shows the principle of a ratiometric configuration. The same voltage reference
source is used for the analog source excitation and the reference voltage input VAREF.
Therefore a given change in the analog source excitation causes the same change at
the reference voltage VAREF. The A/D converter conversion result is the ratio of the
analog input ANx, to the reference voltage VAREF. Since both, the analog input ANx and
the reference voltage VAREF are derived from the same voltage reference source,
changes do not cause measurement errors. Hence, the A/D converter conversion result
is independent to variations in the analog source excitation or variations in the reference
voltage input VAREF. Because of that a stable voltage reference is not necessary to
achieve an accurate measurement result.
Voltage
Reference
Analog
Source
VDD
RAREF
Ceramic
Tantalum
VAREF
CAREF
Central Analog Ground
ANx
Power
Supply
5V
VDD
GND
VSS
Microcontroller
VAGND
Central Digital Ground
Figure 23
Ratiometric Configuration
Application Note
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Overload and Leakage Current
7
Overload and Leakage Current
Both, overload and leakage currents are specified in the Data Sheet. Consideration of
overload and leakage currents can have an influence on the design of the external
components of the analog source. Figure 24 is a simplified electrical model with ESD
structure (clamp diodes) and leakage current of an analog input.
Analog
Source
IOZ1
VDD
Microcontroller
ANx
RASRC
IOV>0
MUX
IOV<0
IOZ1
VLEAK
VSS
V0
ESD Structure
Figure 24
VSS
Leakage Source
A/D Converter Input with ESD Structure and Leakage Source
Note: The ESD structure of the reference voltage VAREF and the reference ground
VAGND is the same as shown in the Figure 24.
7.1
Leakage Current
The maximum input leakage current of the A/D converter is specified in the Data Sheet
in section ’DC Characteristics’. The input leakage current is the sum of all currents which
can flow into or out of an input pin caused by parasitic effects of the input structure, see
Figure 24.
The symbols in the Data Sheets of the C500 and C166 Family used for the input leakage
current of the A/D converter are different. For the C166 Family it is IOZ1 and for the C500
Application Note
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Overload and Leakage Current
Family it is ILI. In this Application Note the symbol IOZ1 is used for the input leakage
current.
The specified value of the A/D converter input leakage current depends on the device
type. Please refer to the Data Sheet for the exact value.
The input leakage current has to be taken into account for the calculation of the
maximum allowed error of the A/D converter result referred to the analog source.
Because the resistance of the analog source RASRC and the input leakage current IOZ1
can cause an additional error via the external ’leakage voltage’ VLEAK.
VLEAK = IOZ1 * RASRC
The leakage voltage VLEAK can cause an additional unadjusted error AUELEAK.
AUELEAK = VLEAK / 1LSB
7.1.1
Calculation Example
Assumed system values:
AUELEAK = 0.25 LSB
Assumed maximum additional unadjusted error
caused by resistance of the analog source RASRC
VAREF
=5V
IOZ1
= |± 200 nA|
1 LSB = 4.9 mV (10-bit A/D converter)
Specified maximum input leakage current
What is the allowed maximum resistance of the analog source RASRC ?
RASRC
= VLEAK / IOZ1
RASRC
= AUELEAK * 1LSB / IOZ1
RASRC
= 0.25 LSB * 4.9 mV / 200 nA
RASRC
= 6125 Ω
Note: The specified maximum Input Leakage Current of |+/- 200 nA| can reduce the
conversion accuracy when the external resistance has a high value (>10 kOhm).
Application Note
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Overload and Leakage Current
7.2
Overload Current
An overload condition is not a normal operating condition. It occurs if the standard
operating conditions are exceeded, i.e. the voltage on an A/D converter input pin VAINx
exceeds the specified range (VAINx > VDD + 0.5 V or VAINx < VSS - 0.5 V). The supply
voltage must remain within the specified limits.
In case of an overload condition on an A/D converter input pin, one of the clamp diodes
becomes conductive. If VAINx > VDD + 0.5 V then the clamp diode connected to VDD
begins to conduct. If VAINx < VSS - 0.5 V then the clamp diode connected to VSS begins
to conduct; See Figure 24.
The overload current has to be taken into account for the calculation of external resistors
which protect the microcontroller inputs. These external resistors guarantee that, in case
of a system error, the specified maximum value of the overload current will not be
exceeded. The calculation also has to consider the specified absolute sum of input
overload currents on all port pins of the microcontroller and especially the specified
absolute sum of the A/D converter input.
7.2.1
Overload Current and Absolute Maximum Ratings
The parameters of the Absolute Maximum Ratings are stress ratings only and
functional operation of the microcontroller is not guaranteed at these or other conditions
above the ’operation conditions’. Stresses above the absolute maximum ratings may
cause permanent damage to the microcontroller. Exposing the microcontroller to
absolute maximum rating conditions for extended periods may affect device reliability.
When the system is switched off or in periods where it is not necessary to guarantee
correct operation, the absolute maximum ratings are the fundamental information for the
calculation of the input overload current, which may occur in case of a system error. In
those cases the specified maximum overload current is IOV = ±10 mA on any pin and the
absolute sum of input overload currents on all port pins is 100 mA. For the exact values,
please refer to the Data Sheet.
7.2.1.1
Calculation Example
Assumed system values:
=0V
VDD
VErr_max = 12 V
IOV_max = |±10 mA|
System supply voltage is off (worst case)
Maximum voltage of the analog signal
in case of a fatal system error
Specified absolute maximum rating of the
overload current
What is the minimum value for the external resistor RP to protect an
analog input pin for a short time overload condition?
Application Note
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Overload and Leakage Current
RP
= (VErr_max - VDD - 0.5 V) / IOV_max
RP
= (12 V - 0 V - 0.5 V) / 10 mA
RP
7.2.2
= 1150 Ω
Overload Current and Operating Conditions
The Operating Conditions must not be exceeded in order to ensure correct operation
of the microcontroller. The specified operating conditions allow a maximum overload
current of IOV = ±5 mA on any pin and the absolute sum over input overload currents on
all port pins is |50| mA. The specified TUE of the A/D converter is guaranteed only if the
absolute sum of input overload currents on all analog input pins does not exceed 10 mA.
For the exact values please refer to the Data Sheet.
7.2.2.1
Calculation Example
Assumed system values:
VDD
= 4.5 V
VErr_max = 12 V
IOV_max = |±5 mA|
Minimum system supply voltage during
operating conditions (worst case)
Maximum voltage of the analog signal
in case of a fatal system error
Specified maximum of the overload current
during operating conditions
What is the minimum value of the external resistor RP to protect an
analog input of the microcontroller and to ensure correct operation?
RP
= (VErr_max - VDD - 0.5 V) / IOV_max
RP
= (12 V - 4.5 V - 0.5 V) / 5 mA
RP
Application Note
= 1400 Ω
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PCB and Design Considerations
8
PCB and Design Considerations
This chapter is a brief introduction in mixed signal board design with a list of guidelines
for optimum printed circuit board layout for microcontrollers with on-chip A/D converter.
8.1
Component Placing
Partition the board with all analog components grounded together in one area and all
digital components in the other. Common power supply related components should be
centrally located.
Mixed signal components, including the microcontroller, should bridge the partitions
with only analog pins in the analog area, and only digital pins in the digital area.
Rotating the microcontroller can often make this task easier.
8.2
Power Supply
Place the analog power and voltage reference regulators over the analog plane. The
same holds for the digital power regulators.
Analog power traces should be over the analog ground plane. The same holds for the
digital power traces.
Decoupling capacitors should be close to the microcontroller pins, or positioned for the
shortest connection to pins with wide traces to reduce impedance.
If both large electrolytic and small ceramic capacitors are recommended, make the
small ceramic capacitor closest to the microcontroller pins.
8.3
Ground Planes
Have separate analog and digital ground planes on the same layer, separated by a
gap, with the digital components over the digital ground plane, and the analog
components over the analog ground plane.
Analog and digital ground planes should only be connected at one point (most cases).
The best place is below the microcontroller. Have vias available in the board to allow
alternative points.
The analog to digital ground plane connection should be near to the power supply, or
near to the power supply connections to the board, or near to the microcontroller.
For boards with more than 2 layers, do not overlap analog related and digital related
planes. Do not have a plane that crosses the gap between the analog ground plane
and the digital ground plane region.
Application Note
49
V 1.0, 2001-05
AP2428.01
C500 / C166 Microcontroller Families
PCB and Design Considerations
8.4
Signal Lines
Analog signal traces should be over the analog ground plane.
Digital power and digital signal traces should be over the digital ground plane.
Regions between analog signal traces should be filled with copper, which should be
electrically attached to the analog ground plane. Regions between digital signal traces
should be filled with copper, which should be electrically attached to the digital ground
plane. These regions should not be left floating, which only makes the interference
worse. Using ground plane fill has shown to reduce digital to analog coupling by up to
30 dB.
8.5
Clock Generation
Locate quartz crystal, ceramic resonator or external oscillator as close as possible to
the microcontroller.
Keep digital signal traces, especially the clock signal, as far away from analog input
and voltage reference pins as possible.
Avoid multiple oscillators or asynchronous clocks. Best results are obtained when all
circuits are synchronous to the A/D converter sampling clock.
Application Note
50
V 1.0, 2001-05
AP2428.01
C500 / C166 Microcontroller Families
Used Short Cuts
9
Used Short Cuts
ADC
ANx
AUELeak
: Analog Digital Converter
: Analog input X
: Additional unadjusted error caused by the leakage current
CAIN
CAIN_max
CAREF
CEXT
CHOLD
CLSB
CMSB
C-Net
C9 - C0
C7’ - C0’
chn
: A/D converter input capacitance (internal C-net)
: Maximum of the A/D converter input capacitance
: External capacitance connected to the reference voltage input VAREF
: External capacitance connected to the analog input
: Hold capacitance of the A/D converter
: LSB of the internal C-net
: MSB of the internal C-net
: Internal A/D converter capacitor network.
: C-net for conversion (10-bit resolution).
: C-net for calibration.
: Analog channel n
DNLE
: Differential nonlinearity error
E
ErrorAINx
: Variable for allowed Error to calculate CAREF
: Maximum deviation between the voltage on ANx and V0 when
the sample time is finished
ErrorAINx_real : Real deviation between the voltage on ANx and V0 referred to the
actual voltage at ANx
ErrorAREF
: Maximum voltage error at VAREF caused by CAREF
ErrorMSB
: Missing voltage to charge the MSB capacitance of the internal C-net to
VAREF/2 during charge-redistribution phase
ESD
: Electrostatic discharge
fCPU
fC
: CPU frequency
: Cutoff frequency
fCYCLE
: Cycle frequency (fCYCLE = 1 / tCYCLEn)
Application Note
51
V 1.0, 2001-05
AP2428.01
C500 / C166 Microcontroller Families
Used Short Cuts
INLE
IAREF
ILi
IOV
IOV_max
IOZ1
: Integral nonlinearity error
: Current of the voltage reference
: Input leakage current (C500 Family)
: Overload current
: Specified maximum rating of the overload current or
: Specified maximum of the overload current during operating conditions
: Input leakage current (C166 Family)
LSB
LSBr
: Least significant bit (general)
: Least significant bit referred to r-bit resolution (LSBr = VAREF / 2r)
MSB
: Most significant bit
Q
: Charge for a complete charge-redistribution- and a calibration phase
r
RAIN
RASRC
RAREF
RAREF_INT
RP
: Resolution of the A/D converter
: Internal series resistance of the A/D converter
: Internal resistance of the analog source
: Resistance between voltage reference and VAREF input
: Internal resistance of the voltage reference
: External resistor RP to protect an analog input in case of an
overload condition
tBC
tC
tCn
tCR
tCYCLE
tCYCLEn
tCHARGE
tCOMPARE
: A/D converter basic clock
: Conversion time
: Conversion time of analog channel n
: Charge redistribution time
: Cycle time
: Cycle time of analog channel n
: Time to charge the MSB capacitance to VAREF/2 within 2*tBC
: Time to compare MSB voltage with sampled input voltage ANx
within 2*tBC
: Sample time
: Internal clock, 2 * TCL = 1 / fcpu
: Time constants for the different phases of a conversion
: Total unadjusted error
tS
TCL
τ1,=τ2,=τ3
TUE
Application Note
52
V 1.0, 2001-05
AP2428.01
C500 / C166 Microcontroller Families
Used Short Cuts
VAREF
VAGND
VANx
VCAIN
VC(t)
VC(tCYCLE)
VDD
VERROR
VERR_max
VLeak
VMSB
VMSB(t)
VMSB(2tBC)
VR
VRF
VSS
VS(t)
VS(tS)
V0
V∆
: Reference voltage input for the A/D converter
: Reference ground for the A/D converter
: Voltage at the analog input ANx
: Voltage at the internal C-net
: Charge curve of CEXT for a total cycle
: Voltage of CEXT at the end of a total cycle
: Supply voltage
: Voltage at RAREF
: Maximum voltage of an analog signal in case of a fatal system error
: Leakage voltage at RASRC
: Voltage at the internal MSB of the C-net
: Comparator voltage during conversion of MSB
: Comparator voltage after 2*tBC
: Missing rest voltage at the end of a conversion cycle
: Voltage reference
: Digital GND
: Voltage during sample time
: Voltage at the end of sample time
: Voltage of the analog source
: Voltage jump at the beginning of the sample time
Application Note
53
V 1.0, 2001-05
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Published by Infineon Technologies AG
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