Application Note - Small Signal - Selection of the MOSFET for Faster Balancing of Li-Ion Batteries

Application Note AN 2013-02
V2.0 February 2013
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
IFAT PMM APS SE DS
Pradeep Kumar Tamma
Application Note AN 2013-02
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
V2.0 February 2013
Edition 2013-02-20
Published by
Infineon Technologies Austria AG
9500 Villach, Austria
© Infineon Technologies Austria AG 2013.
All Rights Reserved.
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Application Note AN 2013-02
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
V2.0 February 2013
Table of contents
1 Introduction .................................................................................................................................................. 4
2 Cell balancing .............................................................................................................................................. 4
3 Implementation of cell balancing ............................................................................................................... 5
4 Selection of the MOSFET ............................................................................................................................ 6
5 Summary & conclusion ............................................................................................................................... 7
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Application Note AN 2013-02
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
1
V2.0 February 2013
Introduction
In multi-cell battery packs, no two cells are identical. There is always a slight difference in the state of charge
(SOC), capacity, impedance and temperature characteristics even with cells from the same manufacturer.
These differences increase over the battery lifetime. By implementing cell balancing circuits these differences
can be reduced significantly. This application note focuses on the selection of the MOSFETs for the cell
balancing of Li-ion batteries.
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Cell balancing
Cell balancing is considered when multiple cells in a battery pack are connected in series. Cell balancing is
not needed in parallel connected Li-Ion cells since this configuration is self-balancing. In a battery pack, cells
are balanced when all the cells in the pack have the same voltage per cell whilst in a fully charged or
discharged state. If one or more of the cells in a pack are not matched then the battery pack is not balanced.
In an unbalanced stack, the usable capacity is significantly lower compared to the nominal capacity.
The impact of cell imbalance on run-time performance and battery life in applications using series connected
cells is certainly undesirable. The fundamental solution of cell balancing equalizes the voltage and SOC
among the cells.
Figure1: Simplified cell balancing set up
A simple implementation of cell balancing is using a MOSFET and a resistor placed in parallel with each cell
to discharge it or bypass a part of the charging current of the cells that are needed to be balanced. This
method is also called “resistor bleeding balancing”. These circuits are controlled by a comparator for simple
voltage based algorithms. Figure1 above illustrates a simplified cell balancing set up using bypass MOSFETs.
The main task here is to select a MOSFET. The MOSFET should have as small a footprint as possible so that
it occupies minimum space on the PCB. And it should have as low power dissipation as possible so that it
bypasses sufficient current to balance the cell in reasonable time without heating up.
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Application Note AN 2013-02
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
V2.0 February 2013
3 Implementation of cell balancing
Individual cell voltage must be monitored to allow cell balancing. When the cell-to-cell voltage variation is
greater than a specific value, the cell balancing circuitry is enabled that gradually matches the voltages of the
individual cells. As stated above, the MOSFET along with a series resistance bypasses a part of the current
around the cell.
During charging of the battery pack when the MOSFET is turned on, it bypasses the current around the cell.
This forces the cell to charge at a slower rate than the other cells in the pack. During discharge of the battery
pack when the MOSFET is turned on, it acts as an extra load to the cell which forces the cell to discharge
faster than the other cells in the pack. Figure2 illustrates an example of a cell balancing circuit for a single cell
in the battery pack.
Figure2: Example of cell balancing module
There are three considerations which determine the bypass current used to balance the cell: the amount of
cell imbalance, balance time and cell capacity. A reasonable amount of cell balancing is 10 % to 20% of
capacity and a minimum time available for cell balance is one charge/discharge period and can be extended
over multiple charge/discharge cycles.
For example, consider a cell of 2.3Ah capacity has an imbalance of 20% and has to be balanced in 1 hour
then the bypass current can be calculated by:
I bypass =
Im balance × Capacity 0.2 × 2.3 Ah
=
= 0.46 A
Balancingtime
1.0h
To bypass this current at a nominal cell voltage of 3.3V, the loss in bypass path is around 1.5W. Even if the
RDS(on) of the MOSFET (S1) is considered as negligible, the series resistance (R1) has to dissipate all of the
energy. Thus the size of the resistor will be very big. So there is a trade-off between balancing time and the
resistor size. Figure3 illustrates the relationship between R1, balancing time and bypass current of a 2.3Ah,
3.3V Li-Ion cell.
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Application Note AN 2013-02
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
V2.0 February 2013
Figure3: Series resistance vs. balancing time of a 2.3Ah, 3.3V Li-Ion cell
4 Selection of the MOSFET
The important factor that has to be considered in selecting a MOSFET for cell balancing is space occupied.
The MOSFET has to occupy minimum space on the board as most of the time the balancing circuit is
mounted on the battery pack itself.
In the above section, it is considered that the RDS(on) of the MOSFET is negligible. This is not the case in
practice; there will be a significant amount of on-resistance. Thus there will be losses in the MOSFET. Due to
this power dissipation in MOSFETs with small footprints, the chip temperature can increase to dangerous
levels. Thus the selected MOSFET for the circuit should have low on-resistance so that it has low power
dissipation which in turn has a low temperature rise at the junction. Therefore, a low ohmic part with a small
footprint is desirable.
™
Infineon’s new 60V, 60mΩ Small Signal OptiMOS 606 family is Best-in-class RDS(on) for the given footprint available in space saving TSOP-6, SOT-89 and SC59 packages. The low RDS(on) makes the OptiMOS™ 606
family suitable for cell balancing in Battery Energy Control Modules (BECM). Also the 4.5V Logic Level gate
enables it to be easily interfaced directly with MCUs/Digital circuits.
As all the products are qualified to AEC Q101, they are ideally suitable for automotive and high quality
demanding applications.
™
Table1 below illustrates the Small Signal OptiMOS 606 product portfolio.
Package
VDS
[V]
RDS(on) max
[mΩ]
(VGS=10V)
RDS(on) max
[mΩ]
(VGS=4.5V)
ID(max)
[A]
BSS606N
SOT-89
60
60
90
3.2
BSL606SN
TSOP-6
60
60
95
4.5
BSR606N
SC59
60
60
90
2.4
Table1: Small Signal OptiMOS™ 606 product portfolio
6
VGS(th) max
[V]
Qg(max)
[nC]
2.3
6.1
Application Note AN 2013-02
Selection of the MOSFET for
Faster Cell Balancing of Li-Ion Batteries
V2.0 February 2013
™
In order to understand the benefits of an OptiMOS
are calculated and shown below.
606 MOSFET in cell balancing the losses in the circuit
Consider a series resistance R1=3.3 Ω is used to balance a 2.3Ah cell with a nominal voltage of 3.3V. It is
also assumed that BSL606SN is used in the circuit and is driven by a 4.5V gate drive power supply. Thus the
bypass current I bypass in the balancing circuit is given by:
I bypass ≈
Vbatt ,nom
R1 + RDS ( on )
=
3.3V
≈ 1A
3.3Ω + 0.095Ω
Thus the losses in the MOSFET S1 are:
PLosses ,S 1 = I bypass ⋅ RDS ( on )
2
PLosses ,S 1 = 12 × 95 ×10 −3 ≈ 95mW
Assume, the ambient temperature is 85°C and the MOSFET is assembled on epoxy PCB FR4 with minimal
footprint. The temperature rise at the junction of the MOSFET S1 is:
∆T = ( PLosses ,S 1 ∗ RthJA )
∆T = 95 ×10 −3 W × 230 K / W ≈ 22 K
With this temperature rise, the junction temperature of the MOSFET at 85°C of ambient will be around 107°C.
5 Summary & conclusion
It is clear from the calculations above, that even with very fast cell balancing the temperature rise is still within
the limits thanks to the lower power dissipation of BSL606SN.
™
By using any of the OptiMOS 606 family for this application typically 20% of the board space can be saved in
comparison to existing solutions. This gives the flexibility to reduce the series resistance and in turn decrease
the balancing time within the existing board space.
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