Application Note AN-957 Measuring HEXFET MOSFET Characteristics Table of Contents Page 1. General Information........................................................................................ 1 2. BVDSS ................................................................................................................ 3 3. IDSS .................................................................................................................... 3 4. VGS(th) ................................................................................................................ 3 5. IGSS ................................................................................................................... 4 6. gfs .................................................................................................................... 4 7. RDS(on) .............................................................................................................. 5 8. VSD .................................................................................................................. 5 9. Composite Characteristics............................................................................. 6 10. Transfer Characteristics............................................................................... 6 11. Transfer Characteristics............................................................................... 7 12. A Fixture to Speed-Up Testing Time ......................................................... 10 This application note describes methods for measuring HEXFET Power MOSFET characteristics, both with a curve tracer and with special-purpose test circuits. AN-957 (v.Int) Measuring HEXFETCharacteristics (HEXFET is the trademark for International Rectifier Power MOSFETs) Topics covered: • • • • • • • • • • • • • • • • • • • Converting the nomenclature from bipolars to MOSFETs P-Channel HEXFET Power MOSFETs Initial settings Breakdown Drain leakage Gate threshold Gate leakage Transconductance On-resistance Diode drop Characteristics in synchronous rectification Transfer characteristics Measurements without a curve tracer Device capacitances Switching times Gate charge Reverse recovery A fixture to speed-up testing time Related topics 1. General Curve tracers have generally been designed for making measurements on bipolar transistors. While power MOSFETs can be tested satisfactorily on most curve tracers, the controls of these instruments are generally labeled with reference to bipolar transistors, and the procedure to follow in the case of MOSFETs is not immediately obvious. This application note describes methods for measuring HEXFET Power MOSFET characteristics, both with a curve tracer and with special-purpose test circuits. Testing HEXFET Power MOSFETs on a curve tracer is a simple matter, provided the broad correspondence between bipolar transistor and HEXFET Power MOSFET features are borne in mind. Table 1 matches some features of HEXFET Power MOSFETs with their bipolar counterparts. The HEXFET Power MOSFET used in all the examples is the IRF630. The control settings given in the examples are those suitable for the IRF630. The user must modify these values appropriately when testing a different device. The IRF630 was selected since it is a typical mid-range device with a voltage rating of 200 volts and a continuous current rating of 9 amps (with TC = 25°C). For measurements with currents above 20 amps, or for pulsed tests not controlled by the gate, the Tektronix 176 Pulsed High Current Fixture must be used instead of the standard test fixture. The IRF630 is an N-channel device. For a P-channel device, all the test procedures are the same except that the position of the Polarity Selector Switch must be reversed—that is, for P-channel devices, it must be in the PNP position. The curve tracer used as an example in this application note is a Tektronix 576, since this instrument is in widespread use. However, the principles involved apply equally well to other makes and models. Figure 1 shows the layout of the controls of the Tektronix 576 curve tracer, with major controls identified by the names used in this application note. Throughout this application note, when controls are referred to, the name of the control is printed in capitals. For all tests, when the power is on, the initial state of the curve tracer is assumed to be as follows: • LEFT/ RIGHT switch in “off” position • VARIABLE COLLECTOR SUPPLY at zero • DISPLAY not inverted • DISPLAY OFFSET set at zero • STEP/OFFSET POLARITY button OUT (not inverted) • VERT/HORIZ DISPLAY MAGNIFIER set at NORM (OFF) • The REP button of the STEP FAMILY selector should be IN • The AID button of the OFFSET selector should be IN AN-957 (v.Int) • The NORM button of the RATE SELECTOR should be IN Figure 1. Location of controls in a 576 curve tracer The accuracy of all tests is predicated on the correct use of the Kelvin connections, as indicated in the instructions for the curve tracer. This is particularly important for power semiconductors, as inductive and resistive drops across sockets and wiring are significant. Some tests require the use of high voltages. After the device is mounted in the test fixture as described for each test, the test fixture safety cover should be closed and the curve tracer manufacturer's safety warnings heeded. The exposed metal parts of many HEXFET Power MOSFETs (for example, the tab of TO-220 devices) are connected to the drain and are therefore at the potential of the collector supply. AN-957 (v.Int) As with any semiconductor device, some of the characteristics of HEXFET Power MOSFETs are temperature dependent. For tests in which there is significant heating of the HEXFET Power MOSFET, a low repetition rate should be used. For tests involving a slow transition through the linear region, a damping resistor of at least 10 ohms should be connected in series with the gate, close to the gate lead to prevent oscillations. If frequent testing of MOS-gated devices is expected, the use of a test fixture that plugs directly into the curve tracer would save a significant amount time. Such a fixture is descibed in Section 12. MOS-gated transistors are static sensitive. Wrist straps, grounding mats and other ESD precautions must be followed, as indicated in INT-955. 2. BVDSS This is the drain-source breakdown voltage (with VGS = 0). BVDSS should be greater than or equal to the rated voltage of the device, at the specified leakage current. 1. 2. 3. 4. 5. 6. 7. 8. 9. PER V E R T DIV 50 µA Connect the device as follows: drain to “C”, gate to “B”, source to 50 V “E”. Set the MAX PEAK VOLTS to 350V. Set the SERIES RESISTOR to limit the avalanche current to a safe value (i.e., tens of milliamps). A suitable value in this case would be 14 kOhms. Set the POLARITY switch to NPN. The MODE control should be set to NORM. HORIZONTAL VOLTS/DIV should be set at 50 volts/div on the Figure 2. Drain-source breakdown voltage "collector" range. VERTICAL CURRENT/DIV should be set at 50 microA/div. On the plug-in fixture, the CONNECTION SELECTOR should be set to “SHORT” in the “EMITTER GROUNDED” sector. This action grounds the gate and disables the step generator. Connect the device using the LEFT/RIGHT switch. Increase the collector supply voltage using the VARIABLE COLLECTOR SUPPLY control until the current (as indicated by the trace on the screen) reaches 250 microA. (See Figure 2.) Read BVDSS from the screen. 3. IDSS This is the drain current for a drain-source voltage of 100% of rated voltage, with VGS = 0. This measurement is made in the same manner as BVDSS, except that: 1. The MODE switch is set to “LEAKAGE”. 2. Connect the device using the LEFT/RIGHT switch and adjust the collector supply voltage to the rated voltage of the HEXFET Power MOSFET (200V for the IRF630). Read the value of IDSS from the display (see Figure 3). The vertical sensitivity may need altering to obtain an appropriately sized display. Often IDSS will be in the nanoamp range and the current observed will be capacitor currents due to minute variations in collector supply voltage. PER H O R Z DIV PER V E R T DIV 1 ηA PER H O R Z DIV 50 V Figure 3. Drain-source leakage current 4. VGS(th) This is the gate-source voltage which produces 250 microA of drain current (VDS = VGS). At this gate-source voltage the device enters the active region. In circuits where devices are connected in parallel, switching losses can be minimized by using devices with closely matched threshold voltages. This test requires the gate to be connected to the drain and conducted as follows: 1. Connect the device as follows: source to “E”, gate to “B”, drain to “C”. This connection arrangement may require the construction of a special test fixture. Bending of the device leads can cause mechanical stress which results in the failure of the device. AN-957 (v.Int) 2. Set the MAX PEAK VOLTS to 15V. 3. Set the SERIES RESISTOR to 0.3 ohms. 4. Set POLARITY to PNP. This causes the drain (collector) terminal to be negative with respect to the source (emitter) terminal. 5. Set the MODE CONTROL to NORM. 6. Set the VERTICAL CURRENT/DIV to 50 microA/div. 7. Set the HORIZONTAL VOLTS/DIV to 500 mV/div. 8. Set the CONNECTION SELECTOR to “SHORT” in the “EMITTER GROUNDED” sector. 9. DISPLAY should be inverted. 10. Connect the device using the LEFT/ RIGHT switch. Increase the VARIABLE COLLECTOR VOLTAGE until the drain current reaches 250 microA as indicated by the trace on the screen. Read the voltage on the horizontal center line (since this line corresponds to ID = 250 microA) (see Figure 4). PER V E R T DIV 50 µA PER H O R Z DIV 500 mV Figure 4. Gate-source threshold voltage 5. I GSS This is the gate-source leakage current with the drain connected to the source. An excessive amount of gate leakage current indicates gate oxide damage. PER V E R T DIV 1 ηA PER H O R Z DIV 5 PER V E R T DIV 1 ηA PER H O R Z DIV 5 V 1. The device is connected as follows: gate to “C”, drain to “B”, source V to “E”. This is not the usual connection sequence, and a special test fixture will be required if bending of the leads is to be avoided. 2. Set MAX PEAK VOLTS to 75V. 3. Set the SERIES RESISTOR to a low value (for example, 6.5 ohms). 4. Set POLARITY to NPN. 5. Set the MODE switch to LEAKAGE. 6. Set the CONNECTION SELECTOR to the “SHORT” position in the “EMITTER GROUNDED” sector. Figure 5. Gate-source leakage current at +20 V 7. HORIZONTAL VOLTS/DIV should be set at 5V/div. 8. VERTICAL CURRENT/DIV should be set to an appropriately low range. 9. Connect the device using the LEFT/RIGHT switch. Increase the collector supply voltage using the VARIABLE COLLECTOR SUPPLY control, but do not exceed 20V, the maximum allowable gate voltage. It may be necessary to adjust the vertical sensitivity. Read the leakage current from the display (see Figure 5). In many cases, the leakage current will be in the nanoamp range, in which case the trace will be dominated by currents which flow through the device capacitance as a result of minute fluctuations in the collector supply voltage. 10. The above procedure is for determining gate leakage current with a positive gate voltage. To make the same measurement using a negative voltage, reduce the VARIABLE COLLECTOR SUPPLY voltage to zero, change the POLARITY switch to the PNP position, and reapply the voltage (see Figure 6). The trace will take time to settle because of the gate-source capacitance. 6. gfs This is the forward transconductance of the device at a specified value of ID. gfs represents the signal gain (drain current divided by gate voltage) in the linear region. This parameter should be measured with a small ac superimposed on a gate bias and the curve tracer is not the appropriate tool for this measurement. Even with specific test equipment, as indicated in Section 11, the dc bias tends to overheat the MOSFET very rapidly and care should be exercised to insure that the pulse is suitably short. Figure 6. Gate-source leakage current at -20 V AN-957 (v.Int) 7. RDS(on) This is the drain-source resistance at 25°C with VGS = 10V. Since RDS(on) is temperature-dependent, it is important to minimize heating of the junction during the test. A pulse test is therefore used to measure this parameter. The test is set up in the following manner: 1. Connect the device as follows: gate to “B”, drain to “C”, source to “E”. 2. Set the MAX PEAK VOLTS to 15 V. 3. Set the SERIES RESISTOR to 0.3 Ohms. 4. The POLARITY switch should be set to NPN. 5. The MODE switch should be set to “NORM”. 6. Set the STEP AMPLITUDE to 1V. 7. Set NUMBER OF STEPS to 10. 8. Set OFFSET MULT to 0. 9. The CURRENT LIMIT should be set to 500 mA. 10. The STEP MULTIPLIER button should be OUT—that is, 0.1X not selected. 11. On the PULSED STEPS selector, the 80 microsec button should be IN (or the 300 microsec, if the 80 is not available). 12. On the RATE selector, the 0.5X button should be IN. 13. Set VERTICAL CURRENT/DIV at 1 amp/div (IRF630). This scale should be chosen according to the on-resistance of the device being tested 14. Set the CONNECTION SELECTOR to the “STEP GEN” position in the “EMITTER GROUNDED” sector. 15. Connect the device using the LEFT/RIGHT switch and raise the VARIABLE COLLECTOR SUPPLY voltage until the desired value of drain current is obtained. RDS(on) is obtained from the trace by reading the peak values of current and voltage (see Figures 7and 8). RDS(on) = VDS/ID. Logic level devices would have different settings for 6, 7 and 8 so that the on-resistance is measured at the specified gate voltage PER V E R T DIV 1 A PER H O R Z DIV 500 mV Figure 7. Drain-source resistance, pulsed mode PER V E R T DIV 1 A PER H O R Z DIV 500 mV Figure 8. Drain-source resistance 8. VSD This is the source-drain voltage at rated current with VGS = 0. It is the forward voltage drop of the body-drain diode when carrying rated current. If pulsed mode testing is required, use high current test fixture. 1. Connect the device as follows: gate to “B”, drain to “C”, source to “E”. 2. Set the MAX PEAK VOLTS to 15V. 3. Set the SERIES RESISTOR at 1.4 ohms or a value sufficiently low that rated current can be obtained. 4. Set POLARITY to PNP. 5. Set MODE to "NORM". 6. The 80 microsec button of the PULSED STEPS selector should be IN (or the 300 microsec, if the 80 is not available). 7. The CONNECTION SELECTOR should be set to the "SHORT" position in the “EMITTER GROUNDED” sector. 8. HORIZONTAL VOLTS/DIV should be on 200 mV/div. 9. VERTICAL CURRENT DIV should be on 1 amp/div. 10. The DISPLAY button should be set to invert. PER V E R T DIV 1 A PER H O R Z DIV 200 mV Figure 9. Source-drain voltage (diode) AN-957 (v.Int) 11. The device is connected using the LEFT/RIGHT switch. Increase the VARIABLE COLLECTOR SUPPLY voltage until rated current is reached (9A for the IRF630). Read VSD from the trace (see Figure 9). 9. Composite Characteristics The forward and reverse characteristics of the HEXFET Power MOSFET may be viewed at the same time. This display can be used to obtain an appreciation of the HEXFET Power MOSFET’s behavior in applications in which current flows in the channel in either direction. such as synchronous rectifiers and analog waveform switching. The procedure is the same as for on-resistance except that: 1. OFFSET is set to zero. 2. The POLARITY control is set at "AC". 3. The device is connected using the LEFT/RlGHTswitch. The VARIABLE COLLECTOR SUPPLY voltage is increased to obtain the required peak value of ID. Beware of device heating. Figure 10 shows the trace obtained with the IRF630. To obtain the reverse characteristics of the diode alone, invert the step polarity. The FET is inoperative, and the display will resemble that shown in Figure 11. The step polarity should also be inverted to obtain the composite characteristics of P-channel devices. PER V E R T DIV 2 A PER V E R T DIV 2 A PER H O R Z DIV 200 mV PER H O R Z DIV 200 mV Figure 10. Operation in first and third quadrant (synchronous rectification) Figure 11. Operation in first and third quadrant without gate drive 10. Transfer Characteristics The transfer characteristic curve of ID versus VGS may be displayed using the pulse mode. The test is set up in the same manner as the onresistance test, except for the following: 1. OFFSET MULTIPLY should be set at zero. 2. Set HORIZONTAL VOLTS/DIV on “STEP GEN”. 3. The 300 microsec button of the PULSED STEP SELECTOR should be IN. 4. Increase the VARIABLE COLLECTOR SUPPLY voltage to obtain the trace shown in Figure 12. The transfer characteristic is outlined by the displayed points. PER V E R T DIV 1 A PER H O R Z DIV Figure 12. Transfer characteristic (ID vs Vgs) AN-957 (v.Int) 250 µA 11. Measurement Of HEXFET Power Mosfet Characteristics Without A Curve Tracer D BVDSS HEXFET Power MOSFET parameters can be measured using standard laboratory equipment. Test circuits and procedures for doing this are described in the following sections, with the IRF630 used as an example. the test arrangement should be varied appropriately for other devices. DVM G S Figure 13. Test circuit for BVDSS BVDSS, Drain-Source Breakdown Voltage The test circuit is shown in Figure 13. The current source will typically consist of a power supply with an output voltage capability of about 3 time BVDSS in series with a current defining resistor of the appropriate value. When testing high voltage HEXFET Power MOSFETs it may not be practical or safe to use a supply of 3 times BVDSS. In such cases, another type of constant current source may be used. VGS(th), Threshold Voltage The test circuit is shown in Figure 14. The 1 kohm gate resistor is required to suppress potentially destructive oscillations at the gate. the current source may be derived from a voltage source equal to the gate voltage rating of the HEXFET Power MOSFET and a series resistor. VDS(on), On-Resistance 250 µA VGS(th) The test circuit is shown in Figure 15. The pulse width should be 300 microsec at a duty cycle of less than 2%. The value quoted is at a junction temperature of 25ºC. RDS(on) is calculated by dividing VDS(on) by ID. Connect the ground of the gate supply as close to the source lead as possible. D DVM 1KΩ Ω G S Figure 14. Test circuit for gate threshold voltage gfs, Transconductance Connect a 50V power supply between the device drain and source, as shown in Figure 16. Use a current probe to measure ID. A signal generator operating at low duty cycle to prevent heating of the device, is used to obtain 80 microsec pulses of the required voltage (VGS) to obtain the following currents: ID D BVDSS OSCILLOSCOPE or DVM PULSE COMMAND G + 10V S 0.015 x ID , 0.05 x ID , 0.15 x ID , 0.5 x ID , and 1.5 x ID where ID is the rated value at TC = 25ºC. Plot a graph of VGS versus ID. The transconductance is equal to the slope of the graph at the Figure appropriate value of drain 15. Test circuit for current. drain on-state voltage AN-957 (v.Int) Ciss, Coss, and Crss. Output, Input and Reverse Transfer Capacitances A 1 MHz capacitance bridge is used for all these tests.The capacitance to be measured is connected in series with a capacitance of known value to provide dc isolation. If Cu is the unknown capacitance, Ck is the known capacitance, and Cm is the measured capacitance, then Cu can be calculated as follows: Cu = CkCm Ck - Cm CP + 50V 100Ω Ω - OSCILLOSCOPE Figure 16. Test circuit for transconductance (1) Figures 17, 18 and 19 show the circuit connections for the three capacitances that characterize power MOSFETs. + 2000 pF 1.0 µF G - HIGH CK CB 10 MΩ Ω S LOW Figure 17. Test circuit for input capacitance D + 2000 pF 1.0 µF G - HIGH CK CB 10 MΩ Ω S LOW Figure 18. Test circuit for output capacitance AN-957 (v.Int) 2000 pF 10:1 LOW CB or DVM 25V Turn-on Delay Time, Rise Time, Turn-Off Delay Time, Fall Time HIGH RD 10M Data sheet value are for a resistive load, as shown in RG Figure 20, as well G Figure 19. Test circuit for transfer capacitance as individual data sheets. The gate pulses should be just long enough to achieve + complete turn-on, with a duty cycle of the 10V order of 0.1%. The series resistor is as specifyed in the data sheet. The definitions of rise, fall and delay times are given in Figure 21. D VDS 0.5 x RATED VDS TO THE OSCILLOSCOPE S VGS Figure 20. Test circuit for switching times Power MOSFETs can switch in nanoseconds. Unless the test circuit is laid-out with RF techniques, the measurements will be totally unreliable. Switching time measurements frequently amount to a characterization of the test circuit, rather than the device under test. Gate charge provides a better indication of the switching capability of power MOSFETs. Q g, Qgs, Qgd Total Gate Charge, Gate-Source Charge, Gate-Drain Charge The total gate charge has two components: the gate-source charge and the gate-drain charge (often called the Miller charge). INT-944 gives more details on this test. Figures 22 and 23 show the test circuit and waveforms. From the relationship Q = ∫i, the following results are obtained: VDS 90% 10% VGS td(on) ON DELAY TIME tr RISE TIME tdoff tf OFF DELAY TIME FALL TIME Figure 21. Switching time waveforms AN-957 (v.Int) Qg = (t3 - t0) ig, Qgd = (t2 - t1) ig, Qgs = Qg - Qgd D ID G VSD Body-Drain Diode Voltage Drop 1.5mA The current source may consist or a voltage source and a series resistor, as shown in Figure 24. VDS ≤ 0.8 x 200V S OSCILLOSCOPE The voltage should be applied in short pulses (less than 300 microsec) with a low duty cycle (less than 2%). Figure 22. Test circuit for gate charge trr, Qrr Body-Drain Diode Reverse Recovery Time and Reverse Recovery Charge Several test circuits are commonly used to charac-terize these parameters. Some have been qualified by JEDEC. The data sheet indicates the test method used for the specific device. VGS S 10V OSCILLOSCOPE or DVM V2 G IS V1 D t0 t1 t2 t t3 Figure 23. Gate charge waveforms Figure 24. Test circuit MOSFET diode drop 1 12. A fixture to speed-up testing time The most commonly tested parameters in a MOSgated transistor are gatesource leakage (IGSS), drain-source resistance (RDS(on)), (BVDSS), current (IDSS), voltage drain TO PVT 2 3 4 C 1 CSENSE B 2 330Ω Ω 3 DSENSE G 4 breakdown voltage drain TO CURVE TRACER ESENSE E 1 30V 2 source- 3 (VSD), 4 threshold (VGS(th)), and so on. These tests can be greatly simplifyed with the fixture shown in Figure25. 30V S Figure 25. Test fixture for HEXFET test SSENSE AN-957 (v.Int) POSITION MEASUREMENT COMMENT 1 IGSS C sense disconnected, Drain Source S/C connected, Collector Voltage applied to gate via 330Ω resistor. Note: Gate protected by back to back 30V zeners. 2 RDS(on) Collector Voltage applied to DrainBased Voltage applied to Gate via 330Ω resistor. 3 BVDSS / IDSS / VDS Collector Voltage applied to Drain, Gate Source S/C connected via 330Ω resistor. 4 VGS(th) Collector Voltage applied to Drain, Gate Drain S/C connected via 330Ω resistor. Related topics: Parameter definition in IGBTs Gate Charge Thermal characteristics ESD sensitivity ESD test methods