ICS9LPR501 Integrated Circuit Systems, Inc. 64-pin CK505 w/Fully Integrated Voltage Regulator PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 SRCC11/CR#_G Output Features: • 2 - CPU differential low power push-pull pairs • 10 - SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 5 - PCI, 33MHz • 1 - PCI_F, 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on CPU & SRC clocks Features/Benefits: • Does not require external pass transistor for voltage regulator • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Selectable between one SRC differential push-pull pair and two single-ended outputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 1 FS LB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 CPU MHz SRC MHz PCI MHz REF MHz USB MHz DOT MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 1118F—11/06/07 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H 64-pin TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Table 1: CPU Frequency Select Table FS LC B0b7 0 0 0 0 1 1 1 1 9LPR501 Pin Configuration Recommended Application: CK505 compliant clock with fully integrated voltage regulator ICS9LPR501 Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME 1 PCI0/CR#_A 2 VDDPCI 3 PCI1/CR#_B TYPE DESCRIPTION I/O 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair PWR I/O 4 PCI2/TME I/O 5 PCI3 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 9 GNDPCI VDD48 10 USB_48MHz/FSLA 11 12 GND48 VDD96_IO PWR PWR 13 DOTT_96/SRCT0 OUT 14 DOTC_96/SRCC0 OUT 15 16 GND VDD PWR PWR OUT PWR PWR I/O Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 37 and 38). The latched value controls the pin function on pins 37 and 38 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 outputs, VDD96_IO is 1.05 to 3.3V with +/-5% tolerance True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. 1118F—11/06/07 2 ICS9LPR501 Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME TYPE 17 SRCT1/SE1 OUT 18 SRCC1/SE2 OUT 19 20 21 22 23 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC PWR PWR OUT OUT PWR 24 SRCT3/CR#_C 25 SRCC3/CR#_D 26 27 28 29 30 31 VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 32 SRCC11/CR#_G DESCRIPTION True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. I/O True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair I/O Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair PWR I/O I/O PWR OUT OUT I/O Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 1118F—11/06/07 3 ICS9LPR501 Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME 33 SRCT11/CR#_H 34 35 36 SRCT10 SRCC10 VDDSRC_IO 37 CPU_STOP#/SRCC5 TYPE I/O OUT OUT PWR I/O 38 PCI_STOP#/SRCT5 I/O 39 40 41 42 VDDSRC SRCC6 SRCT6 GNDSRC 43 SRCC7/CR#_E I/O 44 SRCT7/CR#_F I/O 45 VDDSRC_IO PWR 46 CPUC2_ITP/SRCC8 OUT 47 CPUT2_ITP/SRCT8 OUT 48 NC N/A PWR OUT OUT PWR DESCRIPTION SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3 bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. True clock of differential SRC clock pair. Cpmplement clock of differential SRC clock pair. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. VDD pin for SRC internal circuits, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP No Connect 1118F—11/06/07 4 ICS9LPR501 Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME TYPE 49 VDDCPU_IO PWR 50 CPUC1_F OUT DESCRIPTION Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. 51 CPUT1_F OUT True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. 52 53 54 55 56 GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# PWR OUT OUT PWR IN 57 FSLB/TEST_MODE 58 59 60 61 GNDREF X2 X1 VDDREF 62 REF0/FSLC/TEST_SEL I/O 63 64 SDATA SCLK I/O IN Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. IN PWR OUT IN PWR Fully Integrated Regulator Connection for Desktop/Mobile Applications ICS9LPR501 VDDCPU_IO, Pin 49 1.05V to 3.3V (+/-5%) CPU_IO Decoupling Network 96_IO Decoupling Network NC PIN 48 PLL3_IO Decoupling Network SRC_IO Decoupling Network VDDSRC_IO Pin 45,36,26 VDDPLL3_IO, Pin 20 VDD96_IO, Pin 12 1118F—11/06/07 5 ICS9LPR501 Integrated Circuit Systems, Inc. General Description ICS9LPR501 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPR501 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram X1 REF R EF X2 OSC CPU(1:0) SRC8/ITP CPU CPU PLL1 SS SRC SRC(11-9,7:3) SR C _M A IN PCI33MHz SRC PLL3 SS PCI PCI33MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# SRC1/SE(2:1) CPU_STOP# Control Logic CR#_(A:H) SRC5_EN Differential Output ITP_EN SE Outputs 7 FSLC/TESTSEL FSLB/TESTMODE SRC0/DOT96 SATA PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD GND 49 52 55 52 26, 36, 45 23, 29, 42 39 23, 29, 42 20 19 16 19 12 11 9 11 61 58 2 8 Description CPUCLK Low power outputs Master Clock, Analog Low power outputs SRCCLK PLL 1 Low power outputs PLL3/SE PLL 3 DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK 1118F—11/06/07 6 ICS9LPR501 Integrated Circuit Systems, Inc. Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN MAX 4.6 V 1,7 0.99 3.8 V 1,7 4.6 V 1,7,8 V 1,7 Maximum Supply Voltage VDDxxx Supply Voltage Maximum Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply Maximum Input Voltage VIH 3.3V LVCMOS Inputs Minimum Input Voltage VIL Any Input GND - 0.5 Storage Temperature Ts - -65 Input ESD protection ESD prot Human Body Model 2000 150 UNITS Notes ° C 1,7 V 1,7 Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX Ambient Operating Temp Tambient - 0 70 °C 1 Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V 1 Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.99 3.465 V 1 Input High Voltage VIHSE Single-ended inputs 2 VDD + 0.3 V 1 Input Low Voltage VILSE Single-ended inputs VSS - 0.3 0.8 V 1 Input Leakage Current IIN -5 5 uA 1 Input Leakage Current IINRES VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND -200 200 uA 1 Output High Voltage VOHSE V 1 Single-ended outputs, IOH = -1mA Output Low Voltage VOLSE Single-ended outputs, IOL = 1 mA Output High Voltage VOHDIF Differential Outputs, IOH = TBD mA Output Low Voltage Low Threshold InputHigh Voltage (Test Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage VOLDIF Differential Outputs, IOL = TBD mA VIH_FS_TEST 3.3 V +/-5% VIH_FS VIL_FS Operating Supply Current iAMT Mode Current 0.4 V 1 0.9 V 1 0.4 V 1 2 VDD + 0.3 V 1 3.3 V +/-5% 0.7 1.5 V 1 3.3 V +/-5% VSS - 0.3 0.35 V 1 0.7 IDD_DEFAULT 3.3V supply, PLL3 off 200 mA 1 IDD_PLL3DIF 250 mA 1 250 mA 1 70 mA 1 IDD_PD3.3 3.3V supply, PLL3 Differential Out 3.3V supply, PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 1 mA 1 IDD_PDIO 0.8V IO supply, Power Down Mode 0.1 mA 1 IDD_iAMT3.3 3.3V supply, iAMT Mode 80 mA 1 IDD_PLL3SE IDD_IO Power Down Current 2.4 UNITS Notes IDD_iAMT0.8 0.8V IO supply, iAMTMode 10 mA 1 Input Frequency Fi VDD = 3.3 V 15 MHz 2 Pin Inductance Lpin 7 nH 1 CIN Logic Inputs 5 pF 1 Input Capacitance COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins TBD pF 1 fSSMOD Triangular Modulation 33 kHz 1 Spread Spectrum Modulation Frequency 1118F—11/06/07 7 1.5 30 ICS9LPR501 Integrated Circuit Systems, Inc. AC Electrical Characteristics - Input/Common Parameters PARAMETER SYMBOL Clk Stabilization TSTAB Tdrive_SRC T DRSRC Tdrive_PD# TDRPD Tdrive_CPU T DRSRC Tfall_PD# T FALL Trise_PD# T RISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion MIN Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MAX UNITS Notes 1.8 ms 1 15 ns 1 300 us 1 10 ns 1 5 ns 1 5 ns 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Rising Edge Slew Rate tSLR Differential Measurement 2.5 8 V/ns 1,2 Falling Edge Slew Rate tFLR Differential Measurement 2.5 8 V/ns 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1 Minimum Output Voltage VLOW Includes undershoot mV 1 Differential Voltage Swing VSWING Differential Measurement 300 Crossing Point Voltage VXABS Single-ended Measurement 300 Crossing Point Variation VXABSVAR Single-ended Measurement -300 mV 1 550 mV 1,3,4 140 mV 1,3,5 Duty Cycle DCYC Differential Measurement 55 % 1 CPU Jitter - Cycle to Cycle CPUJ C2C Differential Measurement 85 ps 1 SRC Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 125 ps 1 DOT Jitter - Cycle to Cycle DOTJ C2C Differential Measurement 250 ps 1 CPU[1:0] Skew CPUSKEW10 Differential Measurement 100 ps 1 CPU[2_ITP:0] Skew CPUSKEW20 Differential Measurement 150 ps 1 SRC[10:0] Skew SRCSKEW Differential Measurement TBD ps 1 1118F—11/06/07 8 45 ICS9LPR501 Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS MIN MAX Long Accuracy ppm see Tperiod min-max values -300 300 Clock period T period Absolute min/max period Tabs 33.33MHz output nominal/spread 29.49100 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL 33.33MHz output nominal 33.33MHz output spread V OH @MIN = 1.0 V 29.99100 VOL @ MIN = 1.95 V 30.00900 ns 6 30.15980 ns 6 30.65980 ns 6 V 1 0.4 V 1 mA 1 -33 mA 1 mA 1 38 mA 1 1 -33 VOH@MAX = 3.135 V 30 VOL @ MAX = 0.4 V UNITS NOTES 1,6 ppm Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 4 V/ns Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 4 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Skew tskew VT = 1.5 V Intentional PCI-PCI delay tdelay VT = 1.5 V Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 250 200 nominal 500 ps 1 ps 1,9 ps 1 Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz UNITS NOTES ppm 1,2 PARAMETER Long Accuracy SYMBOL ppm CONDITIONS see Tperiod min-max values MIN -100 MAX 100 Clock period Tperiod 48.00MHz output nominal 20.83125 20.83542 ns Absolute min/max period T abs 48.00MHz output nominal 20.48130 21.18540 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA V OH @MIN = 1.0 V Output High Current IOH Output Low Current IOL Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V Duty Cycle dt1 VT = 1.5 V Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 0.4 -29 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -23 29 VOL @ MAX = 0.4 V 1118F—11/06/07 9 2 V 1 mA 1 mA 1 mA 1 27 mA 1 2 V/ns 1 1 2 V/ns 1 45 55 % 1 350 ps 1 1 ICS9LPR501 Integrated Circuit Systems, Inc. Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX Long Accuracy ppm see Tperiod min-max values -300 300 UNITS Notes ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8203 69.8622 ns 2 Absolute min/max period Tabs 14.318MHz output nominal 69.8203 70.86224 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL 0.4 V 1 -33 -33 mA 1 30 38 mA 1 1 4 V/ns 1 IOL = 1 mA VOH @MIN = 1.0 V, Output High Current IOH Output Low Current IOL Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 4 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter tjcyc-cyc VT = 1.5 V 1000 ps 1 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Electrical Characteristics - SMBus Interface PARAMETER SYMBOL CONDITIONS SMBus Voltage VDD Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency VOLSMB @ IPULLUP IPULLUP SMB Data Pin T FI2C (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) F SMBUS Block Mode T RI2C MIN MAX 2.7 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 100 kHz 1 4 UNITS Notes Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 5 7 Operation under these conditions is neither implied, nor guaranteed. 8 Maximum input voltage is not to exceed maximum VDD 9 See PCI Clock-to-Clock Delay Figure 1118F—11/06/07 10 ICS9LPR501 Integrated Circuit Systems, Inc. Table 1: CPU Frequency Select Table 2 1 FSLB B0b6 0 0 1 1 0 0 1 1 FS LC B0b7 0 0 0 0 1 1 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 CPU MHz SRC MHz PCI MHz REF MHz USB MHz DOT MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Table 2: PLL3 Quick Configuration Pin 17 Pin 18 MHz MHz 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 27.000 N/A 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 27 SS N/A 1 N/A N/A B1b4 B1b3 B1b2 B1b1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 Spread % Comment PLL 3 disabled 0.5% Down Spread SRCCLK1 from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2.5% Down Spread Only SRCCLK1 from PLL3 N/A N/A None 24.576Mhz on SE1 and SE2 None 24.576Mhz on SE1, 98.304Mhz on SE2 None 98.304Mhz on SE1 and SE2 None 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 -0.5% Down on Pin 18 27Mhz on SE1 and SE2 N/A N/A N/A 1118F—11/06/07 11 N/A ICS9LPR501 Integrated Circuit Systems, Inc. Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1 Table 4: Device ID table B8b7 B8b6 B8b5 B8b4 Comment 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 56 pin TSSOP 64 pin TSSOP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1118F—11/06/07 12 ICS9LPR501 Integrated Circuit Systems, Inc. CPU Power Management Table PCI_STOP# CR# SMBus Register OE CPU1 CPU1# CPU(0,2) CPU(0,2)# 1 X 1 X X Enable Running Running Running Running X Enable Low/20K Low Low/20K Low 0 X X X Enable High Low High Low X X Disable Low/20K Low Low/20K Low Running Running Low/20K Low SRC/LCD SRC#/LCD# PD# CPU_STOP# 1 0 1 1 M1 SRC, LCD, DOT Power Management Table PD# CPU_STOP# PCI_STOP# CR# 1 X 0 X 1 X 0 1 X 1 X 0 X 1 X X X SMBus Register OE Free-Run Enable Running Running Enable Low/20K Low X Enable Running 1 X Enable Running Disable M1 SRC/LCD SRC#/LCD# PCI Stoppable/CR Selected Running Running 1 X 0 1 X X 1 X Running Running Low Low/20K Low Running High Low Running Running Running Low/20K Low Running Running Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low USB REF Running PCI_STOP# CR# SMBus Register OE PCIF/PCI PCIF/PCI Free-run Stoppable 1 X X Enable Running Running Running X Enable Low Low Low Low 0 X X Enable Running Low Running Running X Disable Low Low Low Low Low Low Low Low M1 DOT# Low/20K Singled-ended Power Management Table PD# CPU_STOP# DOT 1118F—11/06/07 13 ICS9LPR501 Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9LPR501 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 1118F—11/06/07 14 Not acknowledge stoP bit ICS9LPR501 Integrated Circuit Systems, Inc. Byte 0 FS Readback and PLL Selection Register Bit Pin Name Description Type 7 - FSLC CPU Freq. Sel. Bit (Most Significant) R 6 5 - FSLB FSLA R R 4 CPU Freq. Sel. Bit CPU Freq. Sel. Bit (Least Significant) Set via SMBus or dynamically by CK505 if detects dynamic M1 Reserved Select source for SRC Main Select source for SATA clock 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power-on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. - iAMT_EN 3 2 1 - Reserved SRC_Main_SEL SATA_SEL 0 - PD_Restore 0 See Table 1 : CPU Frequency Select Table 1 Default Latch Latch Latch RW Legacy Mode iAMT Enabled 0 RW RW RW SRC Main = PLL1 SATA = SRC_Main SRC Main = PLL3 SATA = PLL2 0 0 0 RW Configuration Not Saved Configuration Saved 1 Description Select SRC0 or DOT96 Select 0.5% down or center SSC Select 0.5% down or center SSC PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 PCI_SEL Type RW RW RW RW RW RW RW RW 0 SRC0 Down spread Down spread 1 DOT96 Center spread Center spread PCI from SRC_MAIN Default 0 0 0 0 0 0 1 1 Description Output enable for REF, if disabled output is tri-stated Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type 0 1 Default RW Output Disabled Output Enabled 1 RW RW RW RW RW RW RW Output Output Output Output Output Output Output Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Enabled Enabled Enabled Enabled Enabled Enabled Enabled 1 1 1 1 1 1 1 Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Output enable for SRC5 Output enable for SRC4 Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 5 4 3 2 1 0 Pin 13/14 - Name SRC0_SEL PLL1_SSC_SEL PLL3_SSC_SEL PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL See Table 2: PLL3 Quick Configuration Only applies if Byte 0, bit 2 = 0. PCI from PLL1 Byte 2 Output Enable Register Bit Pin Name 7 REF_OE 6 5 4 3 2 1 0 USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC11_OE SRC10_OE SRC9_OE SRC8/ITP_OE SRC7_OE SRC6_OE SRC5_OE SRC4_OE Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation 1118F—11/06/07 15 ICS9LPR501 Integrated Circuit Systems, Inc. Byte 5 Clock Request Enable/Configuration Register Bit Pin Name 7 CR#_A_EN 6 5 4 3 2 1 0 CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type 0 1 Default RW Disable CR#_A Enable CR#_A 0 RW RW RW RW RW RW RW CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 0 0 0 0 0 0 0 1 Enable CR#_E Enable CR#_F Enable CR#_G Enable CR#_H Default 0 0 0 0 0 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 Pin 1 0 Name CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP_CRTL (SRC1) SRC_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Enable CR#_G (clk req) -> SRC9 Enable CR#_H (clk req) -> SRC10 Reserved Reserved Type RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Disable CR#_G Disable CR#_H If set, SSCD (SRC1) stops with PCI_STOP# RW Free Running If set, SRCs (except SRC1) stop with PCI_STOP# RW Free Running Type R R R R R R R R 0 Vendor specific 1 Default X X X X 0 0 0 1 Type R R R R RW RW RW RW 0 See Device ID Table 1 Disabled Disabled Enabled Enabled Default 0 0 0 1 0 0 0 0 Type 0 Free running R RW RW normal operation 1X (2Loads) Outputs HI-Z 1 Stops with PCI_STOP# assertion no overclocking 2X (3 Loads) Outputs = REF/N Default RW RW Normal operation Test mode 0 See Table 3: V_IO Selection (Default is 0.8V) Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Vendor ID ICS is 0001, binary Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for SE1 Output enable for SE2 Byte 9 Output Control Register Bit Pin Name 7 PCIF5 STOP EN 6 5 4 TME_Readback REF Strength Test Mode Select 3 Test Mode Entry Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode 2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1 0 IO_VOUT1 IO_VOUT0 IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) RW RW 1118F—11/06/07 16 0 0 1 0 1 0 1 ICS9LPR501 Integrated Circuit Systems, Inc. Byte 10 CK505 Rev 0.85 Functions (ICS Rev H Silicon and Higher) Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled TBD TBD TBD TBD TBD Free Running Free Running 1 SRC5 Enabled TBD TBD TBD TBD TBD Stoppable Stoppable Default Latch 0 0 0 0 0 1 1 Type RW RW RW RW RW RW R RW 0 TBD TBD TBD TBD Off in iAMT Off in iAMT non-Gen2 Free Running 1 TBD TBD TBD TBD Free running in iAMT Free running in iAMT PCIe Gen2 compliant Stoppable Default 0 0 0 0 0 1 0 1 Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Type RW RW RW RW The decimal representation of M Div (5:0) is equal RW to reference divider value. Default at power up = RW latch-in or Byte 0 Rom table. RW RW 0 - 1 - Default X X X X X X X X 0 - 1 - Default X X X X X X X X 0 - 1 - Default X X X X X X X X Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved CPU2_iAMT_EN CPU1_iAMT_EN PCIe-Gen2 CPU2 Stop Enable Description Reserved Enables CPU2(ITP) output in iAMT state (M1) Enables CPU1 output in iAMT state (M1) PCIe-Gen2 status Enables control of CPU2(ITP) with CPU_STOP# Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Read Back byte count register Byte 13 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Description N Divider 8 N Divider 9 Byte 14 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Description Type RW RW RW The decimal representation of N Div (9:0) is equal RW to VCO divider value. Default at power up = latchRW in or Byte 0 Rom table. RW RW RW Byte 15 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. 1118F—11/06/07 17 Type RW RW RW RW RW RW RW RW ICS9LPR501 Integrated Circuit Systems, Inc. Byte 16 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 x X X X X X X Type RW RW RW RW The decimal representation of M Div (5:0) is equal RW to reference divider value. Default at power up = RW latch-in or Byte 0 Rom table. RW RW 0 - 1 - Default X X X X X X X X 0 - 1 - Default X X X X X X X X Type RW RW RW RW RW RW RW RW 0 - 1 - Default X X X X X X X X Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 Disable Disable Enable Enable Default 0 0 0 0 0 0 0 0 These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 17 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Description N Divider 8 N Divider 9 Byte 18 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Description Type RW RW RW The decimal representation of N Div (9:0) is equal RW to VCO divider value. Default at power up = latchRW in or Byte 0 Rom table. RW RW RW Byte 19 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 20 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 21 M/N Enables Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved M/N Enable CPU M/N Enable SRC/PCI Description 1118F—11/06/07 18 ICS9LPR501 Integrated Circuit Systems, Inc. Byte 22 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 8 N Div bit 9 M Div Bit 5 M Div Bit 4 M Div Bit 3 M Div Bit 2 M Div Bit 1 M Div Bit 0 Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Description Type 0 1 Default Byte 23 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 7 N Div bit 6 N Div bit 5 N Div bit 4 N Div bit 3 N Div bit 2 N Div bit 1 N Div Bit 0 Byte 24 CPU Divider Programming Bit Pin Name 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 CPUDiv3 2 CPUDiv2 1 CPUDiv1 0 CPUDiv0 Reserved CPU Divider Ratio Programming Bits RW 0 RW 0 RW 0 RW 0 RW 0000:/2 1000:/8 X RW 0001:/3 1001:/12 X RW 0010:/5 1010:/20 X RW 0011:/7 1011:/28 X Default Byte 25 SRC and PCI Divider Programming (CK505 PLL1) Bit Pin Name 7 PCIDiv3 6 PCIDiv2 5 PCIDiv1 4 PCIDiv0 3 SRCDiv3 2 SRCDiv2 1 SRCDiv1 0 SRCDiv0 Description PCI Divider Ratio Programming Bits for PLL1 SRC Divider Ratio Programming Bits Type 0 1 RW 0000:/2 1000:/8 X RW 0001:/3 1001:/12 X RW 0010:/5 1010:/20 X RW 0011:/9 1011:/36 X RW 0000:/2 1000:/8 X RW 0001:/3 1001:/12 X RW 0010:/5 1010:/20 X RW 0011:/9 1011:/36 X *Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions. 1118F—11/06/07 19 ICS9LPR501 Integrated Circuit Systems, Inc. Test Clarification Table Comments HW SW FSLB/ FSLC/ TEST_MOD TEST TEST_SEL E ENTRY BIT HW PIN HW PIN B9b3 Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control REF/N or HI-Z B9b4 <2.0V >2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N <2.0V X 1 0 HI-Z <2.0V X 1 1 REF/N B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z) 1118F—11/06/07 20 ICS9LPR501 Integrated Circuit Systems, Inc. c N SYMBOL L E1 INDEX AREA A A1 A2 b c D E E1 e L N α aaa E 1 2 a D 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° -0.10 -.004 A A2 VARIATIONS A1 N -Ce b SEATING PLANE aaa C 64 D mm. MIN 16.90 D (inch) MAX 17.10 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information ICS9LPR501yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS = Standard Device 1118F—11/06/07 21 MIN .665 MAX .673 ICS9LPR501 Integrated Circuit Systems, Inc. Revision History Rev. A B C D E F Issue Date Description 1. Updated Byte 11 10/27/06 2. Updated IDD to CK505 Rev 1.0 spec 1. Updated M/N programming bytes, removed the +2 and +8 02/09/07 2. Added Byte 63 bit 1 for SATA PLL on/off 04/03/07 Added Bytes 24-25. 04/17/07 Removed SSOP Ordering Information. 08/08/07 Release to Final. 11/06/07 Added Foot Note on SMBus. 1118F—11/06/07 22 Page # Various Various 20 22 19