A3987 DMOS Microstepping Driver with Translator Features and Benefits Description ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ The A3987 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full, half, quarter, and sixteenth step modes, with output drive capability of 50 V and 1.5 A. The A3987 includes a fixed off-time current regulator, which has the ability to operate in slow or mixed decay modes. Low RDS(on) outputs Short-to-ground protection Shorted load protection Automatic current decay mode detection/selection Mixed and slow current decay modes Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Package: 24 pin TSSOP with exposed thermal pad (suffix LP) Approximate scale The translator is the key to the easy implementation of the A3987. Simply inputting one pulse on the step input drives the motor to take one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3987 interface is an ideal fit for applications where a complex microprocessor is unavailable or over-burdened. The A3987 chopping control automatically selects the current decay mode (slow or mixed). When a STEP signal occurs, the translator determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to slow decay. If the change is to a lower current, then the decay mode is set to 30.1% fast decay. This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Continued on the next page… Typical Application Diagram 0.1 μF X7R 0.22 μF VREG CP1 VCP VDD 10 μF CP2 0.1 μF X7R 5 kΩ Microcontroller or Controller Logic ROSC VBB1 A3987 STEP DIR SLEEP/RESET VBB2 OUT1A OUT1B SENSE1 ENABLE MS1 MS2 REF OUT2A OUT2B SENSE2 3987DS, Rev. 7 100 μF A3987 DMOS Microstepping Driver with Translator Description (continued) Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover current protection. Special power-up sequencing is not required. The A3987 is supplied in a thin profile (1.2 mm maximum height) 24-lead TSSOP (suffix LP) with exposed thermal tab. The package is lead (Pb) free with 100% matte tin leadframe plating. Selection Guide Part Number A3987SLPTR-T Package Packing 24-pin TSSOP with exposed thermal pad 4000 pieces / reel Absolute Maximum Ratings Characteristic Symbol Rating Units 50 V ±1.5 A VDD 7.0 V VIN –0.3 to VDD + 0.3 V 50 V VSENSE 0.5 V VREF 0 to 4 V Load Supply Voltage VBB Output Current IOUT Logic Supply Voltage Logic Input Voltage Range Notes Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. VBBx to OUTx Sense Voltage Reference Voltage Nominal Operating Temperature TA –20 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Range S Thermal Characteristics* Characteristic Symbol Package Thermal Resistance Notes 4-layer PCB based on JEDEC standard RθJA 2-layer PCB with 3.8 in.2 2 oz. copper each side Rating Units 28 °C/W 32 °C/W *Additional thermal data available on the Allegro website. Maximum Power Dissipation, PD(max) 5.5 5.0 4.5 Power Dissipation, PD (W) 4.0 (R 3.5 θJ 3.0 A = (R θJ 2.5 A = 2.0 32 ºC 28 /W ºC /W ) ) 1.5 1.0 0.5 0.0 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3987 DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 µF 0.1 µF CP1 VREG Charge Pump Regulator VDD CP2 VCP 0.1 µF To VDD DAC VREG VCP DMOS Full Bridge 1 PWM Latch Blanking Mixed Decay OSC ROSC VBB1 OUT1A OUT1B To VDD STEP SENSE1 DIR Control Logic Translator SLEEP/RESET Gate Drive MS1 OCP DMOS Full Bridge 2 VBB2 MS2 OUT2A ENABLE PWM Latch Blanking Mixed Decay OUT2B SENSE2 DAC Buffer REF GND GND Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A3987 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 valid at TA = 25°C, VBB = 50 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ.2 Max. Units Output Drivers Load Supply Voltage Range VBB Logic Supply Voltage Range VDD Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current RDS(on) VF IBB IDD Operating 8 – 50 V During sleep mode 0 – 50 V 3.0 – 5.5 V Operating Source driver, IOUT = –1.5 A – 0.54 0.6 Ω Sink driver, IOUT = 1.5 A – 0.54 0.6 Ω Source diode, IF = –1.5 A – – 1.2 V Sink diode, IF = 1.5 A – – 1.2 V fPWM < 50 kHz – – 4 mA Operating, outputs disabled – – 2 mA Sleep (idle) mode – – 20 μA fPWM < 50 kHz – – 12 mA Outputs off – – 10 mA Sleep mode – – 100 μA VDD × 0.7 – – V Control Logic Logic Input Voltage Logic Input Current VIN(1) VIN(0) – – VDD × 0.3 V IIN(1) VIN = VDD × 0.7 –20 <1.0 20 μA IIN(0) VIN = VDD × 0.3 –20 <1.0 20 μA Input Hysteresis Blank Time Fixed Off-Time tBLANK tOFF 150 – 600 mV fosc = 4 MHz 0.7 1 1.3 μs ROSC tied to ground 15 25 35 μs ROSC = 59 KΩ Reference Input Voltage Range Reference Input Current IREF GM Error3 Err 23 30 37 μs 0.8 – 4 V –3 0 3 μA VREF = 4 V, DAC = 37.5% – – ±15 % VREF = 4 V, DAC = 70.31% – – ±10 % VREF = 4 V, DAC = 100% – – ±5 % Crossover Dead Time tDT 300 650 900 ns Reset Pulse Width tRP 0.2 – 1 μs Sleep Pulse Width tS >2.5 – – μs 2.35 2.7 3 V 0.05 0.10 – V UVLO Enable Threshold VUVLO UVLO Hysteresis VUVHYS VDD rising Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A3987 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 (continued) valid at TA = 25°C, VBB = 50 V, unless noted otherwise Characteristics Min. Typ.2 Max. Units Iocpst 2 – – A Symbol Test Conditions Protection Circuitry Overcurrent Protection Threshold4 Overcurrent Blanking Thermal Shutdown Temperature Thermal Shutdown Hysteresis tocp 1 3 μs TTSD – 165 – °C TTSDhys – 15 – °C 1Negative current is defined as coming out of (sourcing) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF / 8) – VSENSE ] / (VREF / 8). 4OCP is tested at T = 25°C in a restricted range and guaranteed by characterization. A tA tB STEP tC tD MS1, MS2, RESET/SLEEP, or DIR Time Duration STEP minimum, HIGH pulse width Symbol Typ. Unit tA 1 μs STEP minimum, LOW pulse width tB 1 μs Setup time, input change to STEP tC 200 ns Hold time, input change to STEP tD 200 ns Figure 1. Logic Interface Timing Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A3987 DMOS Microstepping Driver with Translator Table 1. Microstep Resolution Truth Table MS1 MS2 Microstep Resolution Excitation Mode L L Full step 2 phase H L Half step 1-2 phase L H Quarter step W1-2 phase H H Sixteenth step 4W1-2 phase Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step (#) Half Step (#) 1/4 Step (#) 1/16 Step (#) Phase 1 Current (% of ITRIP(max)) 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 0.00 9.38 18.75 29.69 37.50 46.88 56.25 64.06 70.31 76.56 82.81 87.50 92.19 95.31 98.44 100.00 100.00 100.00 98.44 95.31 92.19 87.50 82.81 76.56 70.31 64.06 56.25 46.88 37.50 29.69 18.75 9.38 0.00 2 1 2 3 4 3 5 6 2 4 7 8 5 9 Phase 2 Current (% of ITRIP(max)) 100.00 100.00 98.44 95.31 92.19 87.50 82.81 76.56 70.31 64.06 56.25 46.88 37.50 29.69 18.75 9.38 0.00 –9.38 –18.75 –29.69 –37.50 –46.88 –56.25 –64.06 –70.31 –76.56 –82.81 –87.50 –92.19 –95.31 –98.44 –100.00 –100.00 Step Angle (°) 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4 180.0 Full Step (#) Half Step (#) 1/4 Step (#) 1/16 Step (#) 5 9 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 10 3 6 11 12 7 13 14 4 8 15 16 1 1 Phase 1 Current (% of ITRIP(max)) 0.00 –9.38 –18.75 –29.69 –37.50 –46.88 –56.25 –64.06 –70.31 –76.56 –82.81 –87.50 –92.19 –95.31 –98.44 –100.00 –100.00 –100.00 –98.44 –95.31 –92.19 –87.50 –82.81 –76.56 –70.31 –64.06 –56.25 –46.88 –37.50 –29.69 –18.75 –9.38 0.00 Phase 2 Current (% of ITRIP(max)) Step Angle (°) –100.00 –100.00 –98.44 –95.31 –92.19 –87.50 –82.81 –76.56 –70.31 –64.06 –56.25 –46.88 –37.50 –29.69 –18.75 –9.38 0.00 9.38 18.75 29.69 37.50 46.88 56.25 64.06 70.31 76.56 82.81 87.50 92.19 95.31 98.44 100.00 100.00 180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4 360.0 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3987 DMOS Microstepping Driver with Translator STEP STEP 100 100 70 70 Slow Phase 1 IOUT1A DIR = H (%) 100 Mixed –70 –100 100 70 Phase 2 IOUT2B DIR = H (%) 0 Slow Slow Slow Mixed Mixed Mixed Slow Slow Mixed 0 –70 –70 –100 –100 Figure 2. Decay Mode for Full-Step Increments Mixed 0 70 Phase 2 IOUT2A DIR = H (%) Slow Home Microstep Position –100 Slow Home Microstep Position –70 Home Microstep Position 0 Home Microstep Position Phase 1 IOUT1A DIR = H (%) Slow Figure 3. Decay Modes for Half-Step Increments STEP 100 94 70 38 Slow Mixed Slow Mixed Slow 0 Home Microstep Position Phase 1 IOUT1A DIR = H (%) –38 –70 –93 –100 100 93 70 Phase 2 IOUT2B DIR = H (%) 38 Slow Mixed Slow Mixed Slow Mixed 0 –38 –70 –93 –100 Figure 4. Decay Modes for Quarter-Step Increments Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3987 DMOS Microstepping Driver with Translator STEP 98100 95 92 88 83 77 70 64 56 47 38 29 19 Phase 1 IOUT1A DIR = H (%) 9 Slow 0 Mixed Slow Mixed –9 –19 –29 Home Microstep Position –38 –47 –56 –64 –70 –77 –83 –88 –92 –95 –98 –100 98100 95 92 88 83 77 70 64 56 47 38 29 19 Phase 2 IOUT2B DIR = H (%) 9 0 Slow Mixed Slow Mixed Slow –9 –19 –29 –38 –47 –56 –64 –70 –77 –83 –88 –92 –95 –98 –100 Figure 5. Decay Modes for Sixteenth-Step Increments Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A3987 DMOS Microstepping Driver with Translator Functional Description Device Operation The A3987 is a complete microstepping Microstep Select (MS1 and MS2) Inputs MS1 and MS2 motor driver with built-in translator for easy operation with a minimum of control lines. The A3987 is designed to operate bipolar stepper motors in full, half, quarter, and sixteenth step modes. The full bridges on the dual outputs are composed entirely of N-channel DMOS FETS, and the full bridge currents are regulated by fixed off-time, pulse width modulated (PWM) control circuitry. For each full bridge, the individual step currents are set by the combination of: a common external reference voltage, VREF ; an external current sense resistor, RSENSEx ; and the output voltage of an internal DAC that is controlled by the output of the translator. select the microstepping format (see table 1 for state settings). Changes to these inputs do not take effect until the next STEP command. It is good practice to use a pull-up resistor to VDD in order to limit input current should an external overvoltage occur. A minimum of 5 kΩ is recommended. At power-up or reset, the translator sets the DACs and phase current polarity to the initial home state (see figures 2 through 5 for home state conditions), and also sets the current regulator for both output phases to mixed decay mode. When a command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence) and current polarity. The microstep resolution is set by inputs MS1 and MS2 (see in table 1 for state settings). If logic inputs are pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs should an overvoltage event occur. If the new DAC output level is lower than the previous level, then the decay mode for that full bridge will be set to mixed decay. If the new DAC level is higher or equal to the previous level, then the decay mode for that full bridge will be slow decay. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Low-Power Mode Select (SLEEP/RESET) An activelow control input used to minimize power consumption when the A3987 is not in use. This disables much of the internal circuitry including the output FETs and internal regulator. A logic high allows normal device operation and power-up in the home state. When coming out of sleep mode, a 1 ms delay is required before issuing a STEP command, to allow the internal regulator to stabilize. The outputs can also be reset to the home state without entering sleep mode. To do so, pulse this input low for a duration between tRP(min) and tRP(max). Step Input (STEP) A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2. Direction Input (DIR) The state of the DIR input determines the direction of rotation of the motor. A logic change on the DIR pin will not take effect until the next STEP command is issued. Internal PWM Current Control Each full bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink FETs are enabled and current flows through the motor winding and the corresponding current sense resistor, RSENSEx. When the voltage across RSENSE equals the DAC output voltage, the current sense comparator resets the PWM latch, which turns off the source drivers (in slow decay mode) or the sink and source drivers (in fast or mixed decay modes). The maximum value of current limiting is set by the selection of RSENSE and the voltage at the REF input, with a transconductance function approximated by: ITRIP(max) = VREF / (8 × RSENSE ) . The DAC output reduces the VREF output to the current sense comparator in precise steps: ITRIP = (% ITRIP(max) / 100) × ITRIP(max) , (see table 2 for % ITRIP(max) at each step). Note: It is critical that the absolute maximum voltage rating (0.5 V) on the SENSE pins is not exceeded. Fixed Off-Time The internal PWM current control circuitry uses a 4 MHz master oscillator to control the duration of time that the drivers remain off. The fixed off-time, tOFF , is determined by the selection of an external resistor connected from the ROSC timing terminal to VDD. If the ROSC terminal is tied directly to GND, tOFF defaults to 25 μs. The off-time is approximated by: tOFF ≈ ROSC / (1.981 × 109) Blanking This function blanks the output of the current sense comparator when the outputs are switched by the internal current control circuitry. The comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A3987 DMOS Microstepping Driver with Translator the internal body diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK , is internally set to approximately 1 μs. decay portion, tFD , the device switches to slow decay mode for the remainder of the fixed off-time period. Charge Pump (CP1 and CP2) The charge pump is used to triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3987 synchronous rectification feature turns on the appropriate FETs during current decay, effectively shorting out the body diodes in the low RDS(on) driver. This lowers power dissipation significantly, and can eliminate the need for external Schottky diodes for many applications. To prevent reversal of load current, synchronous rectification is turned off when a zero current level is detected. generate a gate supply greater than VBBx to drive the source FET gates. A 0.1 μF ceramic capacitor is required between CP1 and CP2 for pumping purposes. A 0.1μF ceramic capacitor is required between VCP and the VBB terminals to act as a reservoir to operate the high-side FETs. Internal Regulator (VREG) The VREG terminal should be decoupled with a 0.22 μF capacitor to ground. This internally generated voltage is used to operate the sink FET outputs. VREG is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE) This input activates all of the FET outputs. When logic high, the outputs are disabled, and when logic low, the outputs are enabled. Inputs to the translator (STEP, DIR, MS1, and MS2) are always active, except in Sleep mode, regardless of the ENABLE input state. Shutdown In the event of a fault (either excessive junction temperature, or low voltage on VCP), the outputs of the device are disabled until the fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the home state. Mixed Decay Operation The full bridges can operate in mixed decay mode when set by the step sequence (see figures 3 through 5). As the trip point is reached, the device goes into fast decay mode for 30.1% of the fixed off-time, tOFF. After this fast Fault latched 2 A / div. 500 ns / div. Figure 6. Short-to-ground event Synchronous Rectification When a PWM off-cycle is Short-to-Ground Should a motor winding short to ground, the current through the short will rise until the overcurrent threshold, ICOPST , a minimum of 2 A, is exceeded. The driver turns off after a short propagation delay and latches the fault. The device will remain disabled until the SLEEP/RESET input goes high or VDD power is removed. As shown in figure 6, a short-to-ground produces a single overcurrent event. Shorted Load During a shorted load event, the current path is through the sense resistor. During this fault condition the device will be protected, however, the fault will not be latched. When the full bridge turns on, the current will rise and exceed the overcurrent threshold. After the blank time,tBLANK , of approximatly 1 μs, the driver will look at the voltage on the SENSEx pin. The voltage on the SENSEx pin will be larger than the voltage set by the REF pin, and the full bridge will turn off for the time set by the ROSC pin. Figure 7 shows a shorted load condition with an off-time of 30 μs. toff = 30 μs 2 A / div. 5 μs / div. Figure 7. Short-to-load event 10 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3987 DMOS Microstepping Driver with Translator Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3987 must be soldered directly onto the board. On the underside of the A3987 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A3987, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout, shown in figure 8, illustrates how to create a star ground under the device, to serve both as a low impedance ground point and thermal path. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. OUT1A The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in figure 8, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) PCB Thermal (2 oz.) Thermal Vias OUT1A OUT1B GND VIN RS1 1 OUT1B SENSE1 MS2 NC U1 MS1 CCP DIR CVCP STEP CREF CREF ROSC RS2 A3987 PAD CP2 CP1 VCP GND REF ROSC VDD CIN2 OUT1B GND ENABLE OUT2A SENSE2 VIN VBB1 OUT1A RS1 CVDD Solder A3987 SLEEP/RESET VREG CCP CVCP ROSC CIN2 CREG OUT2B VBB2 CIN1 RS2 CREG CIN1 VREF VREF OUT2A OUT2A CVDD OUT2B OUT2B Figure 8. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A3987 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground. 11 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3987 DMOS Microstepping Driver with Translator Device Pin-out Diagrams 24 VBB1 SENSE1 1 23 MS2 OUT1A 2 22 OUT1B NC 3 21 CP2 MS1 4 20 CP1 DIR 5 STEP 6 PAD 19 VCP GND 7 18 GND REF 8 17 ROSC ENABLE 9 VDD 10 OUT2A 11 SENSE2 12 16 SLEEP/RESET 15 VREG 14 OUT2B 13 VBB2 Terminal List Table Number Name Pin Description 1 SENSE1 2 OUT1A 3 NC 4 MS1 Logic input 5 DIR Logic input 6 STEP Logic input 7, 18 GND Ground terminals 8 REF Gm reference input 9 ENABLE 10 VDD 11 OUT2A 12 SENSE2 Sense resistor terminal for Full Bridge 1 DMOS Full Bridge 1, output A No connection Logic input Logic supply DMOS Full Bridge 2, output A Sense resistor terminal for Full Bridge 2 13 VBB2 14 OUT2B Load supply DMOS Full Bridge 2, output B 15 VREG Internal regulator 16 SLEEP/RESET 17 ROSC 19 VCP Reservoir capacitor terminal 20 CP1 Charge pump capacitor terminal 21 CP2 Charge pump capacitor terminal 22 OUT1B Logic input Oscillator input DMOS Full Bridge 1, output B 23 MS2 Logic input 24 VBB1 Load supply – PAD Exposed thermal pad for enhanced thermal dissipation. 12 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3987 DMOS Microstepping Driver with Translator Package LP, 24 Pin TSSOP with Exposed Thermal Pad 7.80 ±0.10 24 0.65 0.45 4° ±4 +0.05 0.15 –0.06 B 3.00 4.40 ±0.10 6.40 ±0.20 A 1 6.10 (1.00) 2 4.32 0.25 24X SEATING PLANE 0.10 C +0.05 0.25 –0.06 3.00 0.60 ±0.15 0.65 1.20 MAX 0.15 MAX C 1.65 SEATING PLANE GAUGE PLANE 4.32 C PCB Layout Reference View For reference only (reference JEDEC MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Copyright ©2006-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 13 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com