A3992 Datasheet

A3992
DMOS Dual Full-Bridge Microstepping PWM Motor Driver
Features and Benefits
Description
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Designed for pulse width modulated (PWM) current control of
bipolar microstepped stepper motors, the A3992 is capable of
continuous output currents to ±1.5 A and operating voltages to
50 V. Internal fixed off-time PWM current control timing circuitry
can be programmed via the serial interface to operate in slow, fast,
or mixed decay modes.
±1.5 A, 50 V continuous output rating
Low RDS(on) DMOS output drivers
Short-to-ground protection
Shorted load protection
Optimized microstepping via six bit linear DACs
Programmable mixed, fast, and slow current decay modes
4 MHz internal oscillator for digital timing
Serial interface controls chip functions
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Inputs compatible with 5 or 3.3 V control signals
Sleep and Idle modes
The desired load current level is set via the serial port with two
six bit linear DACs in conjunction with a reference voltage. The
six bits of control allow maximum flexibility in torque control for
a variety of step methods, from microstepping to full step drive.
Load current is set in 1.56% increments of the maximum value.
Synchronous rectification circuitry allows the load current to flow
through the low RDS(on) of the DMOS output driver during current
decay. This feature eliminates the need for external clamp diodes
in most applications, saving cost and external component count,
while minimizing power dissipation.
Packages
24 pin batwing DIP (suffix B) and 24 pin TSSOP with
exposed thermal pad (suffix LP)
Internal circuit protection includes short-to-ground, shorted load,
thermal shutdown with hysteresis, and crossover current protection.
Special power up sequencing is not required.
The A3992 is supplied in a thin profile (1.2 mm maximum height)
24 pin TSSOP (suffix LP) with exposed thermal pad and a 24 pin
plastic DIP with dual copper batwing tabs (suffix B). The exposed
thermal pad on the LP is at ground potential and needs no electrical
isolation. Both packages are lead (Pb) free with 100% matte tin
leadframe plating.
LP package approximate scale
Typical Application
0.22 μF
VREG
0.22 μF
CP1
0.22 μF
VCP
VDD
10 μF
CP2
5 kΩ
Microcontroller or
Controller Logic
ROSC
CLOCK
DATA
VBB1
A3992
VBB2
100 μF
OUT1A
OUT1B
SENSE1
0.1 μF
STROBE
REF
SLEEP
OUT2A
OUT2B
SENSE2
0.1 μF
3992DS, Rev. 2
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Selection Guide
Part Number
A3992SB-T
15 pieces/tube
Packing
Package
A3992SLPTR-T
Tape, 4000 pieces/reel
24 pin batwing DIP
24 pin TSSOP with
exposed thermal pad
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Symbol
Notes
Rating
Units
50
V
±1.5
A
V
VBB
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions, do
not exceed the specified current rating or a junction temperature of 150°C.
Output Current
IOUT
Logic Supply Voltage
VDD
7.0
Logic Input Voltage Range
VIN
–0.3 to 7
V
50
V
50
V
3
V
500
mV
–20 to 85
ºC
VBBx to OUTx Voltage
OUTx to SENSEx Voltage
REF Reference Voltage
SENSE Voltage (DC)
VREF
VSENSE
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range S
Thermal Characteristics*
Characteristic
Package Thermal Resistance
Symbol
RθJA
Notes
Rating
Units
B package on 4-layer PCB
26
°C/W
B package on 2-layer PCB with 3.15 in.2
2 oz. copper each side
36
°C/W
LP package on 4-layer PCB
28
°C/W
LP package on 2-layer PCB with 3.8 in.2
2 oz. copper each side
32
°C/W
*Additional thermal data available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Functional Block Diagram
0.22 µF
0.22 µF
CP1
CP2
VREG
2V
VDD
UVLO and
Fault
Detect
Charge
Pump
Regulator
Bandgap
VCP
MUX
0.22 µF
To VDD
VCP
6 Bit
Linear DAC
DMOS Full Bridge 1
VBB1
>47 µF
Internal
Oscillator
OSC
OUT1A
Programmable
PWM Timer
OSC Select/
Divider
OUT1B
Fixed-Off
Blank
Mixed Decay
SENSE1
Gate
Drive
CLOCK
To VDD
OCP
Control
Logic
DATA
Serial Port
STROBE
Phase 1,2
Sync Rect Mode
Sync Rect Disable
Mode 1, 2
DMOS Full Bridge 2
VBB2
OUT2A
SLEEP
OUT2B
Programmable
PWM Timer
To 2V
VREF
REF
Fixed-Off
Blank
Mixed Decay
Buffer
SENSE2
0.1 µF
6 Bit
Linear DAC
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3992
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
ELECTRICAL CHARACTERISTICS1 valid at TA= 25°C, VBB = 50 V, fPWM < 50 kHz, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.2
Max.
Units
Output Drivers
Operating, IOUT = ±1.5 A
15
–
50
V
Load Supply Voltage Range
VBB
During Sleep mode
0
–
50
V
VOUT = VBB
–
<1.0
50
μA
Output Leakage Current
IDSS
–
<–1.0
–50
μA
VOUT = 0 V
Source driver, IOUT = -1.5 A
–
0.54
0.6
Ω
Output On Resistance
RDS(on)
Sink driver, IOUT = 1.5 A
–
0.54
0.6
Ω
Source diode, IF = -1.5 A
–
–
1.2
V
Body Diode Forward Voltage
VF
Sink diode, IF = 1.5 A
–
–
1.2
V
fPWM < 50 kHz
–
–
8
mA
Motor Supply Current
IBB
Operating, outputs disabled
–
–
6
mA
Sleep or Idle mode
–
–
20
μA
fPWM < 50 kHz
–
–
12
mA
Outputs off
–
–
10
mA
Logic Supply Current
IDD
Idle mode (Word 1, D18 = 0)
–
–
1.5
mA
Sleep mode
–
–
100
μA
Control Logic
Logic Supply Voltage Range
VDD
Operating
4.5
5
5.5
V
VIN(1)
2.0
–
–
V
Logic Input Voltage
VIN(0)
–
–
0.8
V
IIN(1)
VIN = 2.0 V
–
<1.0
20
μA
Logic Input Current
IIN(0)
VIN = 0.8 V
–
<–2.0
–20
μA
Input Hysteresis
0.20
–
0.40
V
>2
–
–
μs
Minimum sleep pulse width
tS
OSC input frequency
fOSC(in)
Divide by 1 (Word 2, D13=0, D14=1)
2.5
–
6
MHz
OSC input duty cycle
40
–
60
%
OSC shorted to GND
3
4
5
MHz
Internal Oscillator
fOSC
ROSC= 51 kΩ
3.4
4
4.6
MHz
DAC Accuracy
VDAC
Measured relative to REF buffer output
–
±0.5
–
LSB
Reference Input Voltage Range
.5
–
2.6
V
Reference Buffer Offset
VOS
–
±10
–
mV
Word 0, D18 = 0, D17 = 1, VREF = 0.5 to 2.6 V
7.4
8
8.8
–
Reference Divider Ratio
VREF/VSENSE
3.6
4
4.4
–
Word 0, D18 = 1, D17 = 1, VREF =0.5 to 2.6 V
Reference Input Current
IREF
VREF = 2.0 V
–0.5
–
0.5
μA
1.940
2.0
2.060
V
Internal Reference Voltage
VREFINT
Comparator Input Offset Volt.
VIO
VREF = 0 V
–5
0
5
mV
Internal VREF, Range = 8, DAC = 63
–6
0
6
%
Internal VREF, Range = 8, DAC = 31
–9
0
9
%
3
GM Error
VERR
–6
0
6
%
Internal VREF, Range = 4, DAC = 63
Internal VREF, Range = 4, DAC = 15
–10
0
10
%
50% to 90%; PWM change to source on
500
800
1000
ns
50% to 90%; PWM change to source off
35
–
250
ns
Propagation Delay Times
tpd
50% to 90%; PWM change to sink on
500
800
1000
ns
50% to 90%; PWM change to sink off
35
–
250
ns
Crossover Dead Time
tDT
300
650
900
ns
UVLO Enable Threshold
VUVLO
VDD rising
3.9
4.2
4.45
V
UVLO Hysteresis
VUVLOHYS
0.05
0.10
–
V
Protection Circuitry
Overcurrent Protection Threshold4
IOCPST
2
–
–
A
Overcurrent Blanking
tOCP
1
–
3
μs
Thermal Shutdown Temperature
TJ
–
165
–
°C
Thermal Shutdown Hysteresis
TJHYS
–
15
–
°C
1Negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3V
ERR = [(VREF / Range) – VSENSE ] / (VREF / Range).
4OCP is tested at T = 25°C in a restricted range and guaranteed by characterization.
A
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Serial Interface Description
The A3992 is controlled via a 3 wire serial port. The
programmable functions allow maximum flexibility in
configuring the PWM to the motor drive requirements.
The serial data is written as two 19 bit words, 1 bit
to select which word (referred to here as Word 0 and
Word 1) and 18 bits of data. The serial port is defined
in the following tables and text descriptions.
D7 – 12 Bridge 2 Linear DAC. 6 bit word to set the
desired current level for bridge 2. Setting all bits to
zero disables Full Bridge 2, all drivers off. (See Current Regulation in the Functional Description section.)
D13 Bridge 1 Phase. This bit controls the direction
of current for motor phase 1 as defined below:
D13
Word 0 Bit Assignments
Word 0 is selected by setting D0 = 0. Assignments are
summarized in the following table, and described in
detail in the remainder of this section.
OUT1A
OUT1B
0
L
H
1
H
L
D14 Bridge 2 Phase. This bit controls the direction
of current for motor phase 2 as defined below:
Word 0 Bit Assignments
Bit
Function
D14
OUT2A
OUT2B
0
L
H
1
H
L
D0
Word Select = 0
D1
Bridge 1, DAC, LSB
D2
Bridge 1, DAC, Bit2
D3
Bridge 1, DAC, Bit3
D4
Bridge 1, DAC, Bit4
D15
Mode
D5
Bridge 1, DAC, Bit 5
0
Mixed Decay
D6
Bridge 1, DAC, MSB
1
Slow Decay
D7
Bridge 2, DAC, LSB
D8
Bridge 2, DAC, Bit2
D9
Bridge 2, DAC, Bit3
D10
Bridge 2, DAC, Bit4
D11
Bridge 2, DAC, Bit 5
D12
Bridge 2, DAC, MSB
D13
Bridge 1 Phase
D14
Bridge 2 Phase
D15
Bridge 1 Mode
D16
Bridge 2 Mode
D17
Reference Select
D18
Range Select
D1 – D6 Bridge 1, Linear DAC. 6 bit word to set de-
sired current level for bridge 1. Setting all bits to zero
disables Full Bridge 1, all drivers off. (See Current
Regulation in the Functional Description section.)
D15 Bridge 1 Mode. This bit determines the decay
for Full Bridge 1 as defined below:
D16 Bridge 2 Mode. This bit determines the decay
for Full Bridge 2 as defined below:
D16
Mode
0
Mixed Decay
1
Slow Decay
D17 Ref Select. This bit determines the reference
input for the two 6 bit linear DACs. Logic low selects
internal 2 V reference voltage, logic high selects external reference input on the REF pin.
D18 Gm Range Select. D18 determines if the scaling
factor used is 4 or 8:
D18
Divider
Load Current
0
÷8
ITRIP = VDAC/(RSENSE × 8)
1
÷4
ITRIP = VDAC/(RSENSE × 4)
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Word 1 Bit Assignments
Word 1 is selected by setting D0 = 1. Assignments are
summarized in the following table, and described in
detail in the remainder of this section.
Word 1 Bit Assignments
from erroneously resetting the source enable latch,
the sense comparator is blanked. The blank timer runs
after the off time counter to provide the programmable
blanking function. The blank timer is reset when
PHASE is changed.
Bit
Function
D0
Word Select = 1
D1
Blank Time LSB
D2
Blank Time MSB
D3
Off Time LSB
D4
Off Time Bit1
D5
Off Time Bit2
D6
Off Time Bit3
D7
Off Time MSB
D8
Fast Decay Time LSB
D8 – D11 Fast Decay Time. 4 bits to set the fast
D9
Fast Decay Time Bit1
D10
Fast Decay Time Bit2
D11
Fast Decay Time MSB
D12
C0 Oscillator Control
D13
C1 Oscillator Control
D14
SR Control Bit 1
D15
SR Control Bit 2
D16
Reserved for testing
D17
Reserved for testing
decay portion of fixed off-time for the internal PWM
control circuitry. The fast decay portion is defined by:
tfd = (1 + n) × POSC × 8 – POSC ,
where n = 0 to 15.
For example, with a master oscillator frequency of
4 MHz ( POSC = 250 ns), the fixed off-time is adjustable from 1.75 to 31.75 μs, in increments of 2 μs. For
tfd > toff , the device will effectively operate in fast
decay mode.
D18
Idle Mode
D3 – D7 Fixed Off Time. 5 bits to set the fixed
off-time for the internal PWM control circuitry. Fixed
off-time is defined by:
tOFF = (1 + n) × POSC × 8 – POSC ,
where n = 0 to 31.
For example, with a master oscillator frequency of
4 MHz ( POSC = 250 ns), the fixed off-time is adjustable from 1.75 to 63.75 μs, in increments of 2 μs.
D12 – D13 Oscillator Control. 2 bits to set timing
D1 – D2 Blank Time. 2 bits to set the blank time scal-
ing factor for the current sense comparator:
options:
D13
D12
Source and Rate
0
0
Internal clock 4 MHz
D2
D1
Time
0
1
External clock f ÷ 1
0
0
4 × POSC
1
0
External clock f ÷ 2
0
1
6 × POSC
1
1
External clock f ÷ 4
1
0
8 × POSC
1
1
12 × POSC
When a source driver turns on, a current spike occurs
due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike
A 4 MHz internal oscillator can be used for the timing functions. If more precise control is required, an
external oscillator can be input to OSC pin. To accommodate a wider range of system clocks, an internal
divider is provided to generate the desired MO frequency.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
D14 – D15 Synchronous Rectification. 2 bits set the
D16, D17 (Reserved). 2 bits reserved for testing.
different modes of operation (see Synchronous Rectification in the Functional Description section):
They should be programmed to 0 during normal operation.
D18 Idle Mode. The device can be put into the lowpower Idle mode by writing a 0 to D18. The outputs
are disabled, the charge pump turned off, and the device consumes a lower supply current. The undervoltage monitor circuit remains active.
D15
D14
Synchronous Rectifier
0
0
Active
0
1
Disabled
1
0
Passive
1
1
Allegro defined use
Functional Description
VREG. The VREG pin should be decoupled with a
0.22 F capacitor to ground. This internally generated supply voltage is used to run the sink side DMOS
outputs. VREG is internally monitored and in the
case of a fault condition, the outputs of the device are
disabled.
Current Regulation. The reference voltage can be set
by analog input to the REF terminal, or via the internal
2 V precision reference. The choice of reference voltage and selection of sense resistor set maximum trip
current, as follows:
ITRIPMAX = VREF / (Range × RSENSE) .
Microstepping current levels are set according to the
following equations:
ITRIP = VDAC / (Range × RSENSE) , and
VDAC = ((1+DAC) × VREF) / 64 ,
where DAC is the input code, 1 to 63 (Word 0, D1 to
D12), and Range is 4 or 8, as selected by Word 0, D18.
Programming a DAC input code to 0 disables the corresponding bridge, and results in minimum load current.
PWM Timer Function. The PWM timer is program-
mable via the serial port to provide fixed off-time
PWM signals to the control block. In mixed decay
mode, the first portion of the off-time operates in fast
decay, until the fast decay time count is reached, followed by slow decay for the remainder of the fixed
off-time. If the fast decay time is set longer than the offtime, the device effectively operates in fast decay mode.
Oscillator. The PWM timer is based on an oscillator
input, typically 4 MHz. The A3992 can be configured
to select either the 4 MHz internal oscillator or, if
more precise accuracy is required, an external clock
can be connected to the OSC terminal. If an external
clock is used, 3 internal divider choices are selectable
via the serial port to allow flexibility in choosing fOSC
based on available system clocks. If the internal oscillator option is used, the absolute accuracy is dependent
on process variation of resistance and capacitance.
A precision resistor can be connected from the OSC
terminal to VDD to further improve the tolerance. The
frequency is calculated as:
fOSC = 204 × 109 / ROSC
.
If the internal oscillator is used without the external resistor the OSC terminal should be connected to GND.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than VBBx to
drive the source FET gates. A 0.22 μF ceramic capacitor is required between CP1 and CP2 for pumping
purposes. A 0.22 μF ceramic capacitor is required
between VCP and the VBB terminals to act as a reservoir to operate the high-side FETs.
Sleep Mode. Control input on the SLEEP pin is used
to minimize power consumption when not the device
is not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge
pump. Logic low puts the device into Sleep mode,
logic high allows normal operation and startup of the
device into the home position. When asserted low,
the serial port is reset. All bits are reset to 0s, with the
exception of D7, the fixed off-time MSB, which is set
to 1. This prevents the off-time from being too short,
which could result in a loss of current control. When
coming out of Sleep mode, allow 1 ms before issuing
a step command, to allow the charge pump to stabilize.
Shutdown. In the event of a fault due to excessive
junction temperature, or to low voltage on VCP or
VREG, the outputs of the device are disabled until the
fault condition is removed. At power up, and in the
event of low VDD, the UVLO circuit disables the drivers and resets the data in the serial port.
Fault latched
2 A / div.
500 ns / div.
(A) Short-to-ground event
Short to Ground. Should a motor winding short to
ground, the current through the short will rise until the
overcurrent (OCP) threshold is exceeded, a minimum
of 2 A. The driver will turn off after a short propagation delay and latch the device. The device will remain
latched until the SLEEP input goes high or VDD
power is removed. As shown in panel A of the figure
below, a short to ground will produce a single overcurrent event.
Shorted Load. During a shorted load event, the cur-
rent path is through the sense resistor. The device will
be protected, however, the device does not see this as a
fault because the current path is not interrupted, so this
condition will not latch the part.
When a bridge turns on, the current will rise and exceed the overcurrent threshold. After a blank time of
approximately 1μs, the driver will look at the voltage
on the SENSE pin. The voltage on the SENSE pin will
be larger than the voltage set by the VREF pin, and
the bridge will turn off for the time set by the OSC
pin. Panel B of the figure below shows a shorted load
condition with an off-time of 30 μs.
MUX. The MUX pin is reserved for Allegro internal
use and has no function to the end user. In the application, this pin can be tied to ground or left floating.
toff = 30 μs
2 A / div.
5 μs / div.
(B) Short-to-load event
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Synchronous Rectification. When a PWM off-cycle
with the two serial port control bits:
1. Active mode. Prevents reversal of load current.
is triggered, by a bridge disable command or internal
Turns off synchronous rectification when a 0 current
fixed off-time cycle, load current recirculates accordlevel is detected.
ing to the decay mode selected by control logic. The
2. Passive mode. Allows reversal of current, but will
A3992 synchronous rectification feature turns on the
turn off the synchronous rectifier circuit if the load
appropriate MOSFETs during current decay, and effeccurrent inversion ramps up to the current limit.
tively shorts out the body diodes with the low RDS(on)
3. Disabled. Prevents MOSFET switching during load
driver. This lowers power dissipation significantly, and
recirculation in fast decay portion of the off-time. Durcan eliminate the need for external Schottky diodes for
ing the slow decay portion of the off-time, the low-side
most applications.
switch turns on, which recirculates current through the
low-side MOSFET and low-side body diode.
Three distinct modes of operation can be configured
Applications Notes
Current Sensing. To minimize inaccuracies in sens-
Thermal Protection. Circuitry turns off all drivers
ing the IPEAK current level caused by ground trace IR
drops, the sense resistor should have an independent
ground return to the GND terminal of the device. For
low value sense resistors, the IR drops in the PCB
sense resistor traces can be significant and should
be taken into account. The use of sockets should
be avoided because they can introduce variation in
RSENSE due to their contact resistance.
when the junction temperature reaches 165°C typical.
It is intended only to protect the device from failures
due to excessive junction temperatures, and should not
imply that output short circuits are permitted. Thermal
shutdown has a hysteresis of approximately 15°C.
Allegro MicroSystems recommends a value of RSENSE
given by:
RSENSE = 0.5 / ITRIP MAX .
D
STROBE
Serial Port Write Timing Operation. Data is clocked
into a shift register on the rising edge of a CLOCK
signal. Normally, STROBE is held high, and is only
brought low to initiate a write cycle. The data is written MSB first. Refer to the diagram below for timing
requirements.
E
F
C
CLOCK
G
DATA
MSB
A
LSB - D0
B
SLEEP
H
Serial Port Timing Diagram
A. Minimum Data Setup Time
B. Minimum Data Hold Time
C. Minimum Setup Strobe to Clock rising edge
D. Minimum Clock High Pulse Width
E. Minimum Clock Low Pulse Width
15 ns
10 ns
120 ns
40 ns
40 ns
F. Minimum Setup Clock rising edge to Strobe
G. Minimum Strobe Pulse Width
H. Minimum Sleep to Clock Setup Time
I. Setup “Idle” Release to Output Enable
50 ns
120 ns
50 μs
1 ms
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Layout. The printed circuit board should use a heavy
groundplane. For optimum electrical and thermal
performance, the A3992 must be soldered directly
onto the board. On the underside of the A3992 package is an exposed pad, which provides a path for
enhanced thermal dissipation. The thermal pad should
be soldered directly to an exposed surface on the PCB.
Thermal vias are used to transfer heat to other layers
of the PCB.
In order to minimize the effects of ground bounce and
offset issues, it is important to have a low impedance
single-point ground, known as a star ground, located
very close to the device. By making the connection between the pad and the ground plane directly under the
A3992, that area becomes an ideal location for a star
ground point. A low impedance ground will prevent
ground bounce during high current operation and ensure that the supply voltage remains stable at the input
terminal. The recommended PCB layout, shown in the
diagram below, illustrates how to create a star ground
under the device, to serve both as a low impedance
ground point and thermal path.
The two input capacitors should be placed in parallel,
and as close to the device supply pins as possible. The
ceramic capacitor (CVBB1) should be closer to the
pins than the bulk capacitor (CVBB2). This is necessary because the ceramic capacitor will be responsible
for delivering the high frequency current components.
The sense resistors, RSx , should have a very low
impedance path to ground, because they must carry
a large current while supporting very accurate voltage measurements by the current sense comparators.
Long ground traces will cause additional voltage
drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins
have very short traces to the RSx resistors and very
thick, low impedance traces directly to the star ground
underneath the device.
OUT1A
OUT1A
OUT1B
VBB
OUT1B
GND
CS1
1
VBB
CS1
RS1
RS1
SENSE1
NC
NC
U1
STROBE
CCP
CLOCK
CVCP
DATA
CREF
CREF
CREG
PAD
CP2
CP1
VCP
GND
OSC
MUX
SLEEP
SENSE2
CS2
RS2
A3992
REF
OUT2A
CVBB2
OUT1B
GND
VDD
ROSC
CVDD
VBB1
OUT1A
VREG
CCP
CVCP
ROSC
CVBB2
CREG
OUT2B
VBB2
CVBB1
RS2
CVBB1
CS2
VREF
OUT2A
OUT2B
VREF
OUT2A
CVDD
OUT2B
LP package layout shown
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Device Pin-out Diagrams
B Package
LP Package
VCP 1
24 OSC
CP1 2
23 SLEEP
CP2 3
22 VREG
23 NC
OUT1A 2
22 OUT1B
NC 3
21 OUT2B
OUT1B 4
24 VBB1
SENSE1 1
21 CP2
STROBE 4
VBB1 5
20 VBB2
GND 6
19 GND
DATA 6
GND 7
18 GND
GND 7
18 GND
17 SENSE2
REF 8
17 OSC
16 OUT2A
MUX 9
16 SLEEP
STROBE 10
15 VDD
VDD 10
15 VREG
CLOCK 11
14 MUX
OUT2A 11
DATA 12
13 REF
SENSE2 12
SENSE1 8
OUT1A 9
20 CP1
CLOCK 5
PAD
19 VCP
14 OUT2B
13 VBB2
Terminal List Table
Number
B
LP
Package Package
Name
Pin Description
1
19
VCP
Reservoir capacitor terminal
2
20
CP1
Charge pump capacitor terminal
3
21
CP2
Charge pump capacitor terminal
4
22
OUT1B
5
24
VBB1
Load supply
6, 7, 18, 19
7, 18
GND
Ground. On B package, internally fused to the die pad
for enhanced thermal dissipation.
8
1
SENSE1
9
2
OUT1A
10
4
STROBE
Logic input
11
5
CLOCK
Logic input
12
6
DATA
Logic input
13
8
REF
Gm reference input
14
9
MUX
Not used
15
10
VDD
Logic supply
DMOS Full Bridge 1, output B
Sense resistor terminal for Full Bridge 1
DMOS Full Bridge 1, output A
16
11
OUT2A
17
12
SENSE2
DMOS Full Bridge 2, output A
20
13
VBB2
21
14
OUT2B
22
15
VREG
Internal regulator
23
16
SLEEP
Logic input
24
17
OSC
Oscillator input
–
3, 23
NC
No connection
–
–
PAD
Exposed thermal pad for enhanced thermal dissipation.
Sense resistor terminal for Full Bridge 2
Load supply
DMOS Full Bridge 2, output B
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Package B, 24 Pin DIP with Fused Pins
+0.25
30.10 –0.64
24
+0.10
0.38 –0.05
+0.76
6.35 –0.25
+0.38
10.92 –0.25
5.33 MAX
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
7.62
A
1
2
+0.51
3.30 –0.38
1.27 MIN
+0.25
1.52 –0.38
2.54
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
0.018
0.46 ±0.12
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Package LP, 24 Pin TSSOP with Exposed Thermal Pad
7.80 ±0.10
4° ±4
24
0.65
0.45
+0.05
0.15 –0.06
B
3.00
4.40 ±0.10
6.40 ±0.20
A
1
6.10
(1.00)
2
4.32
0.25
24X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.60 ±0.15
0.65
1.20 MAX
0.15 MAX
C
1.65
SEATING PLANE
GAUGE PLANE
4.32
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ©2006-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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