A3995 Datasheet

A3995
DMOS Dual Full Bridge PWM Motor Driver
Not for New Design
The A3995SEVTR-T is in production but has been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications. The
device should not be purchased for new design applications because
obsolescence in the near future is probable. Samples are no longer
available.
Date of status change: June 27, 2016
Recommended Substitutions:
Recommended Substitutions:
A5995GEVSR-T
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3995
DMOS Dual Full Bridge PWM Motor Driver
Features and Benefits
Description
▪
▪
▪
▪
▪
▪
▪
The A3995 is designed to drive two DC motors at currents up to
2.4 A. Capable of drive voltages up to 36 V, the A3995 includes
two independent fixed off-time PWM current regulators that
operate in either fast or slow decay mode, as determined by
the MODE input. Internal synchronous rectification control
circuitry is provided to improve power dissipation during
PWM operation.
36 V output rating
2.4 A, DC motor driver
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Very thin profile QFN package
Protection features include: thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power-up sequencing is not required.
The A3995 is supplied in a 36 pin QFN package (suffix EV)
with exposed power tab for enhanced thermal performance. It
has a 6 mm × 6 mm footprint, with a nominal overall package
height of 0.90 mm, and is lead (Pb) free, with 100% matte tin
leadframe plating.
Package: 36 pin QFN
0.90 mm nominal height (suffix EV)
Approximate scale 1:1
Typical Application Diagram
CP1
CP2
VCP
VDD
VBB
OUT1A
OUT1A
MODE1
A3995
PHASE1
Microcontroller or
Controller Logic
VBB
OUT1B
OUT1B
SENSE1
SENSE1
ENABLE1
VREF1
MODE2
PHASE2
OUT2A
OUT2A
ENABLE2
A3995DS Rev. 2
GND
GND
OUT2B
OUT2B
GND
GND
VREF2
SENSE2
SENSE2
A3995
DMOS Dual Full Bridge PWM Motor Driver
Selection Guide
Part Number
A3995SEVTR-T
Packing
1500 pieces per reel
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Supply Voltage
VDD
Output Current*
IOUT
Logic Input Voltage Range
VIN
SENSEx Pin Voltage
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
VSENSEx
Notes
Pulsed tw < 1 μs
Rating
Units
-0.5 to 36
V
38
V
–0.4 to 7
V
Continuous
2.4
A
Pulsed tw < 1μs
3.5
A
Pulsed tw < 1μs
VREFx
–0.3 to 7
V
0.5
V
2.5
V
2.5
V
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
TA
Range S
* May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a
Junction Temperature of 150°C.
Thermal Characteristics (may require derating at maximum conditions)
Symbol
RθJA
Test Conditions
EV package, 4 layer PCB based on JEDEC standard
Min. Units
27
ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
Power Dissipation, PD (mW)
Characteristic
Package Thermal Resistance
3500
3000
2500
2000
EV Package
4-layer PCB
(RQJA = 27 ºC/W)
1500
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3995
DMOS Dual Full Bridge PWM Motor Driver
VDD
CHARGE
PUMP
OSC
VBB
VBB
VCP
CP1
CP1
Functional Block Diagram
DMOS Full Bridge 1
VCP
MODE1
OUT1A
CONTROL
LOGIC
PHASE1
OUT1A
OUT1B
GATE
DRIVE
Sense1
VREF1
PWM Latch
BLANKING
SENSE1
+
3
OUT1B
-
ENABLE1
SENSE1
RS1
DMOS Full Bridge 2
VCP
MODE2
OUT2A
CONTROL
LOGIC
PHASE2
OUT2A
GATE
DRIVE
ENABLE2
VREF2
3
+
Sense2
OUT2B
OUT2B
PWM Latch
BLANKING
-
Sense2
SENSE2
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
SENSE2
RS2
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3995
DMOS Dual Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1, valid at TA = 25 °C, VBB = 36 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.2
Max.
Units
Load Supply Voltage Range
VBB
Operating
8.0
–
36
V
Logic Supply Voltage Range
VDD
Operating
3.0
–
5.5
V
VDD Supply Current
IDD
–
7
10
mA
Output On Resistance
RDS(on)
Vf , Outputs
Source driver, IOUT = –1.2 A, TJ = 25°C
Sink driver, IOUT = 1.2 A, TJ = 25°C
IOUT = 1.2 A
Output Leakage
IDSS
Outputs, VOUT = 0 to VBB
VBB Supply Current
IBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
–
350
450
mΩ
–
350
450
mΩ
–
–
1.3
V
–20
–
20
μA
–
–
8
mA
V
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
Propagation Delay Times
Crossover Delay
VIN(1)
0.7×VDD
–
–
VIN(0)
–
–
0.3×VDD
V
VIN = 0 to 5 V
–20
<1.0
20
μA
150
300
500
mV
PWM change to source on
350
550
1000
ns
PWM change to source off
35
–
300
ns
PWM change to sink on
350
550
1000
ns
PWM change to sink off
35
–
250
ns
IIN
Vhys
tpd
tCOD
300
425
1000
ns
Blank Time
tBLANK
2.5
3.2
4
μs
VREFx Pin Input Voltage Range
VREFx
Operating
0.0
–
1.5
V
IREF
VREF = 1.5
–
–
±1
μA
VUV(VBB)
VBB rising
VREFx Pin Reference Input Current
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VUV(VBB)hys
VUV(VDD)
VDD rising
7.3
7.6
7.9
V
400
500
600
mV
2.65
2.8
2.95
V
VUV(VDD)hys
75
105
125
mV
TJTSD
155
165
175
°C
TJTSDhys
–
15
–
°C
1For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits.
3V
ERR = [(VREF/3) – VSENSE] / (VREF/3).
2Typical
DC Control Logic
PHASE
ENABLE
MODE
OUTA
OUTB
Function
1
1
1
H
L
Forward (slow decay SR)
1
1
0
H
L
Forward (fast decay SR)
0
1
1
L
H
Reverse (slow decay SR)
0
1
0
L
H
Reverse (fast decay SR)
X
0
1
L
L
Brake (slow decay SR)
1
0
0
L
H
Fast decay SR*
0
0
0
H
L
Fast decay SR*
* To prevent reversal of current during fast decay SR – the outputs will go to the high impedance state as the current gets near zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A3995
DMOS Dual Full Bridge PWM Motor Driver
Logic Timing Diagram, DC Driver
ENB
PH
MODE
VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
1
2
3
4
5
6
7
VBB
8
9
VBB
1 5
6
OutA
OutB
3
2 4
7
OutA
OutB
8
9
A
Charge Pump and VREG Power-up Delay (z200 μs)
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A3995
DMOS Dual Full Bridge PWM Motor Driver
Functional Description
Device Operation The A3995 is designed to operate two
DC motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse width
modulated (PWM) control circuitry. The peak current to each full
bridge is set by the value of an external current sense resistor,
RSx , and a reference voltage, VREFx .
If the logic inputs are pulled up to VDD, it is good practice to use
a high value pullup resistor in order to limit current to the logic
inputs should an overvoltage event occur. Logic inputs include:
PHASEx, ENABLEx, and MODE.
Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP . Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and RSx. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
RS and the voltage at the VREF input with a transconductance
function approximated by:
ITripMax = VREF / (3×RS)
Note: It is critical to ensure that the maximum rating of 500 mV
on each SENSEx pin is not exceeded.
Control Logic Dc motor commutation is accomplished by
applying a PWM signal together with the PHASE or ENABLE
inputs. Fast or slow current decay during the off-time is selected
via the MODE pin. Synchronous Rectification is always active
regardless of the state of the MODE pin.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the VBB in order to drive the
source-side DMOS gates. A 0.1 F ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1 F
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
Shutdown In the event of a fault (excessive junction temperature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Synchronous Rectification When a PWM-off cycle is
triggered by an internal fixed off-time cycle, load current will
recirculate. The A3995 synchronous rectification feature will
turn on the appropriate MOSFETs during the current decay. This
effectively shorts the body diode with the low RDS(on) driver. This
significantly lowers power dissipation. When a zero current level
is detected, synchronous rectification is turned off to prevent
reversal of the load current.
MODE Control input MODE is used to toggle between fast
uses a one shot circuit to control the time the drivers remain off.
The one shot off-time, toff , is internally set to 30 μs.
decay mode and slow decay mode. A logic high puts the device
in slow decay mode. Synchronous rectification is always enabled
when ENABLE is low.
Blanking This function blanks the output of the current sense
Braking The Braking function is implemented by driving the
Fixed Off-Time The internal PWM current control circuitry
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related
to the capacitance of the load. The driver blank time, tBLANK , is
approximately 3 s.
Phase Input (PHASEx) The state of the PHASEx input
determines the direction of rotation of the motor.
device in slow decay mode via the MODE pin and applying an
ENABLE chop command. Because it is possible to drive current
in both directions through the DMOS switches, this configuration effectively shorts the motor-generated BEMF as long as the
ENABLE chop mode is asserted. The maximum current can be
approximated by VBEMF/RL. Care should be taken to ensure that
the maximum ratings of the device are not exceeded in worst case
braking situations: high speed and high inertia loads.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A3995
DMOS Dual Full Bridge PWM Motor Driver
Motor Configurations For applications that require either a
stepper/DC motor driver or dual stepper motor driver, Allegro offers
the A3989 and A3988. These devices are offered in the same QFN
package as the A3995. The A3988 is capable of driving 2 bipolar
stepper motors at output currents up to 1.2 A. The stepper control
logic is industry standard parallel communication. Please refer to
the Allegro website for further information and datasheets about
those devices.
Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A3995 must be soldered directly onto the board. On the underside of the A3995 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A3995, that area
becomes an ideal location for a star ground point.
A low impedance ground will prevent ground bounce during
high current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below, illustrates how to create a star ground
under the device, to serve both as low impedance ground point
and thermal path.
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high frequency current components.
Sense Pins The sense resistors, RSx, should have a very
low impedance path to ground, because they must carry a large
current while supporting very accurate voltage measurements
by the current sense comparators. Long ground traces will cause
additional voltage drops, adversely affecting the ability of the
comparators to accurately measure the current in the windings.
As shown in the layout below, the SENSEx pins have very short
traces to the RSx resistors and very thick, low impedance traces
directly to the star ground underneath the device. If possible,
there should be no other components on the sense circuits.
Note: When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
VBB
VBB
CVCP
CVCP
CIN3
CCP
RS1
NC
GND
CP1
MODE1
RS2
VBB
PHASE1
GND
OUT2A
NC
OUT1A
VREF2
SENSE2
NC
OUT2B
SENSE1
VDD
OUT2A
OUT2B
OUT1B
NC
OUT1A
PAD
OUT1B
PHASE2
CIN2
SENSE2
VBB
CIN1
CIN1
OUT2A
A3995
SENSE1
OUT2B
VCP
MODE2
VREF1
OUT1B
NC
OUT1A
U1
CIN2
NC
GND
1
CP2
RS2
GND
CIN3
GND
ENABLE1
CCP
RS1
ENABLE2
GND
CVDD1
CVDD1
GND
VDD
CVDD2
CVDD2
EV package layout shown.
Figure 5. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the
A3995 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical
vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A3995
DMOS Dual Full Bridge PWM Motor Driver
19 NC
20 OUT2A
21 SENSE2
22 OUT2B
23 VBB
24 OUT2B
25 SENSE2
26 OUT2A
27 MODE2
Pin-out Diagram
MODE1 28
18
GND
NC 29
17
PHASE1
16
GND
15
NC
CP1 32
14
VREF2
CP2 33
13
VREF1
GND 34
12
NC
ENABLE1 35
11
VDD
ENABLE2 36
10
PHASE2
GND 30
PAD
1
2
3
4
5
6
7
8
9
NC
OUT1A
SENSE1
OUT1B
VBB
OUT1B
SENSE1
OUT1A
NC
VCP 31
Terminal List Table
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
–
Name
NC
OUT1A
SENSE1
OUT1B
VBB
OUT1B
SENSE1
OUT1A
NC
PHASE2
VDD
NC
VREF1
VREF2
NC
GND
PHASE1
GND
NC
OUT2A
SENSE2
OUT2B
VBB
OUT2B
SENSE2
OUT2A
MODE2
MODE1
NC
GND
VCP
CP1
CP2
GND
ENABLE1
ENABLE2
PAD
Description
No Connect
DMOS Full Bridge 1 Output A
Sense Resistor Terminal for Bridge 1
DMOS Full Bridge 1 Output B
Load Supply Voltage
DMOS Full Bridge 1 Output B
Sense Resistor Terminal for Bridge 1
DMOS Full Bridge 1 Output A
No Connect
Control Input
Logic Supply Voltage
No Connect
Analog Input
Analog Input
No Connect
Ground
Control Input
Ground
No Connect
DMOS Full Bridge 2 Output A
Sense Resistor Terminal for Bridge 2
DMOS Full Bridge 2 Output B
Load Supply Voltage
DMOS Full Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full Bridge 2 Output A
Control Input
Control Input
No Connect
Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Ground
Control Input
Control Input
Exposed pad for enhanced thermal performance. Should
be soldered to the PCB
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A3995
DMOS Dual Full Bridge PWM Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
1.15
6.00 ±0.15
0.30
0.50
36
36
1
2
1
2
A
6.00 ±0.15
D 37X
SEATING
PLANE
0.08 C
4.15
C
5.80
4.15
5.80
0.90 ±0.10
+0.05
0.25 –0.07
0.50
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VJJD-3, except pin count)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.55 ±0.20
B
A Terminal #1 mark area
4.15
2
1
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can
improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
36
4.15
Copyright ©2006-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
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