2EDN Gate Driver IC Replacement Guide

Ei ceDR I V ER™
Dual channel 5 A, high-speed, low-side gate driver with high negative input voltage capability and
advanced reverse current robustness
Repl a cem e nt guid e
2EDN752x / 2EDN852x
Tobias Gerber
Application Note
About this document
Scope and purpose
This replacement guide is a step-by-step introduction on how to use the industry pin-out compatible
2EDN752x / 2EDN852x low-side gate drivers as a replacement for other dual LS Drivers on the market.
Intended audience
This document is intended for experienced hardware engineers who already have a basic knowledge of gate
drivers.
Table of contents
1
Introduction ............................................................................................................... 2
2
Description 2EDN752x / 2EDN852x ................................................................................ 3
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.3
3.3.1
3.3.2
Replacement step-by-step ........................................................................................... 4
First step: Preparation ........................................................................................................................ 4
Supply voltage............................................................................................................................... 4
Inputs ............................................................................................................................................. 4
Output ........................................................................................................................................... 5
Footprint........................................................................................................................................ 6
Second step: Device selection ............................................................................................................ 6
Cross reference table .................................................................................................................... 6
Third step: Power-up........................................................................................................................... 6
Before power-up ........................................................................................................................... 6
After power-up .............................................................................................................................. 7
4
Summary ................................................................................................................... 8
1
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Introduction
1
Introduction
Initial criteria for the designer to consider when selecting a suitable gate driver IC technology will include
current capabilities, switching speeds, form factor, level of integration (e.g. how many driver channels are
available and what safety features are built in), and how well the process and package technologies are
matched to the efficiency and thermal performance requirements of the target application. When
exchanging components in such a design, the solution must exactly match these criteria to the original
design.
This low-side gate driver provides two independent, non-isolated, low-side gate drivers, each offering a 5 A
peak source or sink current. Both channels operate with typical rise and fall times of just 5 ns. Despite the
high current, the output stage still offers a very low on resistance, meaning that there is very low power
dissipation in the driver even if a very small (or no) external gate resistor is used.
These extended parameters make it possible to replace a wide range of drivers.
Application Note
2
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Description 2EDN752x / 2EDN852x
2
Description 2EDN752x / 2EDN852x
The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level
MOSFETs and supports OptiMOS™ , CoolMOS™ , Standard Level MOSFETs, Superjunction MOSFETs, as well
as IGBTs and GaN Power devices.
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to
+20 V. The robustness of the -10 V input pin protects the driver against latch-up or electrical overstress that
can be induced by parasitic ground inductances. This greatly enhances system stability.
The 4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under
abnormal conditions. Under such circumstances, this UVLO mechanism provides crucial independence if
other supervisor circuitries detect abnormal conditions.
Each of the two outputs is able to sink and source 5 A currents utilizing a true rail-to-rail stage. This ensures
very low on resistance of 0.7 Ω up to the positive rail and 0.55 Ω down to the negative rail. Very tight channel
to channel delay matching, typ. 1 ns, permits parallel use of two channels, leading to a source and sink
capability of 10 A. An industry leading reverse current robustness eliminates the need for Schottky diodes at
the outputs and reduces the component count and cost.
From Controller
The pinout of the 2EDN family is compatible with the industry standard footprint. Two different control
input options, non-inverted and inverted, offer high flexibility. Three package variants, DSO 8-pin, TSSOP 8pin, WSON 8-pin, allow optimization of PCB board space usage and thermal characteristics.
VDD
2EDN752x /
2EDN852x
1 ENA
ENB 88
2 INA
OUTA 7
33 GND
VDD 6
44 INB
Load1
Load2
M1
Rg1
Rg2
M2
OUTB 55
CVDD
Figure 1
Typical application
Application Note
3
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Replacement step-by-step
3
Replacement step-by-step
3.1
First step: Preparation
Before replacing a device, we recommend to measure and check key parameters in the initial design. In
some cases an adjustment after replacement is necessary.
3.1.1
Supply voltage
The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current
capability of 2EDN752x / 2EDN852x when driving very large MOSFETs.
The minimum operating supply voltage is set by the undervoltage lockout function to a typical default value
of 4.2 V or 8V. This lockout function protects power MOSFETs from running into linear mode with
subsequent high power dissipation.
The 2EDN752x / 2EDN852x have a strong output stage. We recommend a capacitor of > 22 nF close to pin 3
(GND) and pin 6 (VDD).
Please measure power supply parameters at pin 3 (GND) to pin 6 (VDD) as described in table 1.
Table 1
Supply voltage parameter
Parameter
Symbol
Note
Positive supply voltage
VVDD
4.5 V to 20 V; min defined by UVLO
VDD quiescent current
IVDDqu1 / IVDDqu2
VDD current max
IVDD max
Power supply has to support more than 0.7 mA under
quiescent conditions (no switching).
Current consumption at VDD pin 6 with max switching
frequency and max voltage VVDD
3.1.2
Inputs
The 2EDN752x / 2EDN852x are available in 2 different configurations with respect to the logic configuration
of the 4 input pins (input plus enable).
The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins
left open. The standard PWM inputs are internally pulled down to a logic low voltage. This prevents a switchon event during power up and a non-driven input condition. The version with the inverted PWM input has an
internal pull up resistor to prevent unwanted switch-on.
All inputs are compatible with LVTTL levels and provide a hysteresis of 1 V (typ.). This hysteresis is
independent of the supply voltage.
All input pins have an extended negative voltage range. This prevents cross current over single wires during
GND shifts between signal source (controller) and driver input.
Application Note
4
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Replacement step-by-step
Please measure pin 1 (ENA), pin 2 (INA), pin 4 (INB) and pin 8 (ENB) to pin 3 (GND) as described in table 2.
Table 2
Input parameters
Parameter
Symbol
Note
Input/Enable low level
VINL , VENL
Input/Enable high level
VINH , VENH
Input/Enable rise/fall time
TINRISE, TINFALL
Max voltage level, inclusive noise floor, should
have a space to input voltage threshold for
transition high-low.
Recommended safety margin to (0.8V) > 200mV
Min voltage level, inclusive noise floor, should
have space to input voltage threshold for transition
low-high.
Recommended safety margin to (2.3V) > 200mV
If channels A and B run in parallel mode, the
rise/fall time has to be faster than 100 ns (10%90%) to avoid cross current on output stages
3.1.3
Output
The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a 5 A
(typ.) sourcing and sinking current. This output stage has shoot through protection and current limiting
behavior. The output impedance is very low with a typical value below 0.7 Ω for the sourcing p-channel MOS
and 0.5 Ω for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for
achieving true rail-to-rail behavior and avoiding a source follower’s voltage drop.
Gate Drive Outputs are held active low in the case of floating inputs on ENx, INx or during startup or power
down once UVLO is not exceeded. Under all conditions the startup, UVLO or shutdown, outputs are held in
defined states.
From Controller
Often for replacements, the original device could have a different output stage topology internally. This
includes different internal impedance, slew rates and timing behavior. It is a good idea to measure the
MOSFET gate voltage reaction (B) according to the input signal (A) as described below (see figure 2).
Adjusting resistor Rg can bring the signal as close as possible to the original time and slope.
A
VDD
2EDN752x /
2EDN852x
1 ENA
ENB 88
2 INA
OUTA 7
33 GND
VDD 66
44 INB
Load1
Load2
M1
Rg1
Rg2
OUTB 55
M2
B
CVDD
Figure 2
Transfer signal measurement
Application Note
5
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Replacement step-by-step
3.1.4
Footprint
Some original devices have no enable input signals. In this case, pins 1 and 8 need careful observation as
described in table 1..
Table 3
Footprint enable pins
Status
Behavior
Note
Pads for pin 1 and 8 are not
connected to any network
Floating
Pads for pin 1 and 8 are
connected to VDD
Pads for pin 1 and 8 are
connected to GND
Static voltage on Vdd
No action needed.
New device has an internal pull-up
resistor (400 k) to enable driver.
No action needed.
New device is enabled.
Pads or PCB need rework. Without
modification, the driver will not enable
the output
Static GND potential
3.2
Second step: Device selection
3.2.1
Cross reference table
Infineon offers a cross-reference table on the Infineon homepage to help with the first selection.
To use the list, first search for the gate driver currently being used. If the current device is not on the list,
then please look for a device which has a parameter set as close as possible to the device being used.
Choose the linked Infineon EiceDRIVER ™ from the list.
The cross-reference list is a good starting position with the important parameters, but the datasheet is the
final reference for any decision. Once an initial selection is made, please carefully compare the original
driver datasheet with the new device datasheet.

It is recommended to check the package drawings between original device and new device.

Compare your findings and parametric data from earlier testing with the new device datasheet. Power
supply, inputs, outputs, timings and footprint have to be within limits.

If these parameters are checked, you are ready to move ahead with the right Infineon EiceDRIVER ™.
3.3
Third step: Power-up
3.3.1
Before power-up
After carefully reworking and adding a new EiceDRIVER ™, please check the parts around the driver as
detailed in table 4.
Table 4
Blocking Capacitor and gate resistor
Part
Note
Blocking capacitor between pins 3 and 6
Gate resistor Rg on each channel
Please use a ceramic capacitor > 22 nF
If precise MOSFET timing is necessary, please
adjust the gate resistor according the new driver
output impedance.
Application Note
6
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Replacement step-by-step
3.3.2
After power-up
Even after the basic checks are complete the application can have feedback from (or interaction with) other
components. We recommend controlling all components based upon parametric limits and temperature.
If needed, it is possible to adjust Rg to get the same slew rate on the power MOSFET. This may be needed to
fulfill the EMI requirements.
Application Note
7
Revision 1.0, 2015-11-02
Replacement guide
2EDN752x / 2EDN852x
Summary
4
Summary
After the changes are completed, the application will normally have a better performance due to the lower
losses resulting from faster MOSFET switching and lower output stage impedance.
Finally, it should be noted that as well as the gate driver ICs themselves, Infineon is also providing
comprehensive development and prototyping support in the form of application-specific evaluation boards
and reference designs. Built around the 2EDNx52x drivers and the new CoolMOS™ C7 600 V MOSFETs, these
evaluation and development tools include a 130 kHz 800 W CCM PFC board, a 3.5 kW PFC design, and a
halfbridge 600 W LLC board with a 12 V, 50 A output.
[1] References https://www.infineon.com/2EDN
Revision History
Major changes since the last revision
Page or Reference
--
Application Note
Description of change
First release
8
Revision 1.0, 2015-11-02
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBLADE™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, iWafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™,
PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM
Limited, UK. ANSI™ of American National Standards Institute. AUTOSAR™ of AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CATiq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of
Microsoft Corporation. HYPERTERMINAL™ of Hilgraeve Incorporated. MCS™ of Intel Corp. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim
Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA.
muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ of Openwave Systems Inc. RED HAT™ of Red Hat, Inc. RFMD™ of RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun
Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design
Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2014-07-17
www.infineon.com
Edition 2015-10-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG.
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Document reference
AN_2015010_PL52_001
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