Design of Secondary-Side Rectification using IR1168 Dual SmartRectifier Control IC

Application Note AN-1139
Design of Secondary-Side Rectification using
IR1168 Dual SmartRectifier™ Control IC
By Adnaan Lokhandwala
Table of Contents
Introduction & Device Overview
LLC Resonant Half Bridge Converter Operation
Dual SmartRectifierTM Operation in Resonant Converters
Typical System Schematics and Passive Components Nomenclature
Detailed Design Procedure & Example
Layout Guidelines
Appendix
Symbol list
References
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Introduction and Device Overview
IR1168 is a smart secondary-side driver IC designed to drive the two N-Channel
power MOSFETs used as synchronous rectifiers in isolated DC-DC resonant
converters. The IC can control one or more paralleled MOSFETs to emulate the
behavior of Schottky diode rectifiers. Ruggedness and noise immunity are
accomplished using an advanced blanking scheme and double-pulse
suppression which allow reliable operation in both fixed and variable frequency
modes. The drain to source voltage of the MOSFET is sensed differentially to
determine the level of the current and the device is turned on and off in close
proximity of the zero current transition. The pinout for this 8 pin device is shown
below.
Figure 1: IR1168 Dual SmartRectifier™ control IC pin assignment
The SmartRectifier™ Control Technique is based on sensing the voltage across
the MOSFET and comparing it with two negative thresholds to determine the turn
on and off transition for the device. A higher negative threshold, VTH2, detects
current through the body diode and hence, controls the turn on transition for the
power device. Similarly, a second negative threshold, VTH1, determines the level
of the current at which the device turns off as shown below.
VGate
VDS
VTH2
VTH1
VTH3
Figure 2: IR1168 Dual SmartRectifier™ control IC differential voltage sensing thresholds
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When the power device is turned on, the instantaneous sensed voltage reduces
to RDSon ⋅ I D and depending on the level of the device current, could fall below the
turn off threshold and cause false device turn off. Additionally, the device turn on
is also associated with some parasitic ringing between the transformer leakage
inductance and device output capacitance. Hence, additional control logic has
been incorporated to prevent false turn off and gate chattering when the device
current transitions between its body diode and channel.
LLC Half-Bridge Converter Operation
The increasing popularity of the LLC resonant converter in its half-bridge
implementation is due to its high efficiency, low EMI emissions and its ability to
achieve high power density. This topology is also the most attractive topology for
front-end DC bus conversion. It utilizes the magnetizing inductance of the
transformer to construct a complex resonant tank with buck boost transfer
characteristics in the soft-switching region. The typical power stage schematic for
this topology with synchronous output rectification (low-side configuration) is
shown below.
Vin
M1
1
Lr
SR1
2
Ls1
Lm
M2
Cout
LOAD
Ls2
Cr
Rtn
SR2
Figure 3: Typical schematic of a DC-DC half-bridge resonant converter with synchronous output
rectification
Devices M1 and M2 operate at 50% duty cycle and the output voltage is
regulated by varying the switching frequency of the converter. The converter has
two resonant frequencies – a lower resonant frequency (given by Lm, Lr, Cr and
the load) and a fixed higher series resonant frequency fr1 (given by LR and CR
only). The two bridge devices can be soft-switched for the entire load range by
operating the converter either above or below fr1. This topology behaves very
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similarly to a series resonant converter when it operates in the region above fr1.
The typical AC transfer characteristics 1 for a LLC tank resonant converter are
shown in Figure 4.
1A
2A
3A
4A
5A
6A
5.0
ZVS REGION
2.5
SEL>>
0
ZCS REGION
fr1
M(V(Vout)/V(Vin))
180d
100d
0d
-90d
1.0KHz
3.0KHz
P(V(Vout)/V(Vin))
10KHz
30KHz
100KHz
300KHz
1.0MHz
Frequency
Figure 4: Typical frequency response of a LLC resonant converter
The characteristics of a LLC resonant converter can be divided into three regions
according to 3 different modes of operation. The converter should be prevented
from entering the ZCS region of operation. In the region above fr1, the converter
operates very similar to a series resonant converter. In this operating region, Lm
never resonates with resonant capacitor Cr; it is clamped by output voltage and
acts as the load of the series resonant tank.
In the ZVS range below fr1, the LLC resonant converter operation is more
complex and can be divided into two time intervals. In the first time interval, Lr
resonates with Cr and Lm is clamped by output voltage. When the current in the
resonant inductor Lr resonates back to same level as the magnetizing current, Lr
and Cr stop resonating. Lm now participates in the resonant operation and the
second time interval begins. During this time interval, the resonant components
change to Cr and Lm in series with Lr.
1
For this AC analysis, only the fundamental component of the square-wave voltage input to the
resonant network contributes to the power transfer to output. The transformer, rectifier and filter
are replaced by an equivalent AC resistance, Rac.
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Dual SmartRectifierTM Operation in Resonant Converters
The IR1168 Dual SmartRectifier™ IC can emulate the operation of the two
secondary rectifiers by properly driving the Synchronous Rectifier (SR)
MOSFETs. The rectifier currents in the two secondary legs are sensed using the
power MOSFET RDSon as a shunt resistance and the GATE pins of the MOSFET
are driven depending on the level of the sensed voltage with respect to the 3
thresholds shown earlier in Figure 2.
The core of this device are the two high-voltage (200V), high speed comparators
which differentially sense the drain to source voltage of the MOSFET, in order to
determine the polarity and level of the device currents. Dedicated internal logic
then manages to turn the power device on and off in close proximity of the zero
current transition. This ensures accurate performance without the need of PLL or
external timing sources. Additionally, internal blanking logic is used to prevent
spurious gate transitions and guarantee operation in fixed and variable frequency
operation modes. Typical waveforms are shown in Figure 5 below.
Figure 5: Typical operating waveforms showing MOT and tBLANK functions
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¾ Turn On Phase
When the conduction phase of the SR FET is initiated, current will start flowing
through its body diode, generating a negative VDS voltage across it. The body
diode has generally a much higher voltage drop than the one caused by the
MOSFET on resistance and therefore will trigger the turn-on threshold VTH2. At
that point, the IR1168 will drive the gate of MOSFET ON which will in turn cause
the conduction voltage VDS to drop down. This drop is usually accompanied by
some amount of ringing, that can trigger the input comparator to turn off; hence,
a fixed Minimum On Time (MOT) blanking period is used that will maintain the
power MOSFET on for a minimum amount of time. The MOT also limits the
minimum conduction time of the SR MOSFET and hence in this case, the
maximum switching frequency of the converter.
¾ Turn Off Phase
Once the SR MOSFET has been turned on, it will remain on until the rectifier
current will decay to the level where VDS will cross the turn-off threshold VTH1.
Once the threshold is crossed and the GATE is turned off, the current will once
again flow through the body diode causing the VDS voltage to jump negative.
Depending on the amount of residual current, VDS may again trigger the turn on
threshold; hence, to prevent false turn-on, VTH2 is blanked for an internally set
blank time after VTH1 has triggered as shown in Figure 5. As soon as VDS crosses
the positive threshold VTH3, this blanking time is terminated and the IC is ready
for next conduction cycle. The turn off speed is more critical in this transition to
avoid cross conduction on the primary side and reduce switching losses.
Please note that both MOT and the Blanking time logic are allowed only once per
switching cycle; it is necessary that VDS reaches VTH3 for them to be enabled
again (therefore ready for the next switching cycle).
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Typical System Schematics and Passive Components Nomenclature
The passive components needed for IR1168 operations are:
• Cdc: supply decoupling capacitor
Components not necessary but recommended are:
• RCC: series resistor on supply capacitor
• Rg1, 2: synchronous MOSFET gate resistors
The supply voltage for the IC can be drawn directly from the converter’s output
when it falls within the recommended range for the IC. In all other cases, it is
recommended to provide a dedicated supply through either:
• Auxiliary transformer winding
• Transformer main winding tap
Typical system implementations for IR1168 are shown below –
SR1
Rcc
Cdc
Rg1
1
2
3
4
GATE1
GATE2
VCC
GND
VS1
VS2
VD1
VD2
8
7
6
5
Rg2
+
-
IR1168S
OUTPUT
SR2
Figure 6: IC Supply derived directly from the converter output voltage
SR1
Cdc
Rg1
1
2
3
Rcc
4
GATE1
GATE2
VCC
GND
VS1
VS2
VD1
VD2
8
7
6
5
Rg2
+
-
IR1168S
OUTPUT
SR2
Figure 7: IC supply derived from an auxiliary winding on the power transformer
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Detailed Design Procedure
Fundamental values to be captured on the system if not known by design are
1. Minimum ( f SWmin ) and maximum ( f SWmax ) switching frequency
2. Secondary minimum conduction time, also called Minimum On Time
(MOT) in SmartRectifier™ terminology.
3. The maximum temperature of the environment in which the IR1168 IC will
operate, TICamb (this is normally the maximum PCB temperature)
4. The available supply voltage Vsupply . It can be the converter output voltage
or a dedicated supply (auxiliary winding).
The following design procedure assumes that the synchronous MOSFET has
been already identified as well as the above mentioned systems parameters. The
basic idea behind this is the need to ideally approximate a rectifier behavior,
having the voltage sense as a sole input to the controller.
a. IC current consumption calculation
First, from the selected synchronous MOSFET, the total gate charge Qg and gate
to drain charge Qgd data have to be identified, together with the corresponding
gate voltage Vgs. Because of the IR1168 mode of operations, the secondary
device current initially flows through the SR body diode; therefore, the turn on
gate characteristic doesn’t include the Miller charge of the MOSFET. Figure 8
below shows how the regular gate characteristics (black) change when the
switch is turned on at zero or slightly negative drain to source voltage (red).
Figure 8: MOSFET gate characteristic when driven by SmartRectifier™ control
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It is evident much less charge is required and the behavior can satisfactorily be
modeled as a capacitor:
Csync =
Qg − Qgd
Vgs
If more parts are paralleled, the above capacitance must be multiplied with the
number of devices. The maximum IC required current can then be calculated
using the following equation:
I CC = I QCC + 2 × f SWmax CsyncVghigh + 1.18 ⋅10−8 f SWmax
where Vg high is the IR1168 gate driver output voltage and fSWmax is the converter
maximum switching frequency as previously identified. The second term is
entirely due to the two synchronous MOSFET gate drive while the third term
accounts for the IC internal logic consumption in regular operations (the factor
1.18 ⋅10 −8 accounts for the frequency dependent current requirements for the
internal logic). Notice this term is independent of the supply voltage of the IC.
b. Supply series resistor and gate resistor design, and thermal verification
IR1168 based synchronous rectification has the prerogative to turn the switch on
and off at VDS levels close to zero. Hence, the gate resistor does not have an
impact on the transitions and can be designed on a different basis.
In order for the gate loop to be optimized, oscillations have to be avoided in
regular operations. Assuming the total gate trace loop inductance (Lg) is known,
(a first order estimation can be 1nH/mm of physical trace length), the minimum
recommended gate resistor will be
Rg loop > 2
Lg
Ciss
Where Ciss is the switch input capacitance (from MOSFET datasheet). It is
evident how a good layout practice can dramatically reduce this requirement.
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Now, let’s consider the well known series RC network transient; the energy
dissipated by the resistor is exactly equal to the energy stored in the capacitor.
The IR1168 internal gate driver is of course always in series with the external
gate resistor, which means they will linearly share the power dissipation.
First, let’s calculate the energy stored in the gate capacitance of one of the two
synchronous MOSFETs:
1
Eg1 = Csync1Vg2high
2
The total power dissipated by the driver buffer AND the total gate resistance (for
both gate drivers) will therefore be
Pdr = Pdr1 + Pdr 2 = 2 f SW max Eg1 + 2 f SW max Eg 2
The driver buffer and the gate resistance will linearly share this power dissipation
as described in the following relationship:
⎛
Rg1
Rg1
+
PR g 1 = ⎜
⎜R +R
Rg1 + RSink
Source
⎝ g1
Rearranging this last relationship
PR g 1
Pdr1
⎞ Pdr1
⎟⋅
⎟ 2
⎠
Rg1
Rg1
1⎛
= ⎜
+
2 ⎜⎝ Rg1 + RSource Rg1 + RSink
⎞
⎟
⎟
⎠
Solving this equation with respect to Rg1, 2 (which includes the external gate
resistor and the MOSFET internal gate resistance), it is possible to determine the
percentage of the total driving power dissipated into the gate resistor as a
function of its value. Notice on IR1168 datasheet, pull up ( rup ) and pull down
( rdown ) resistances are defined. Also, for the above calculations, we
use RSink = rdown and RSource = 1.1rup in order to account for some extra energy
dissipated for voltage clamping.
The final step is the thermal verification for the chosen value. Using the
maximum junction to ambient thermal resistance, the maximum temperature
(where ambient refers to the environment in which the IC will work, i.e. box, PCB
etc.) and the IC maximum junction temperature, it is now possible to calculate the
maximum allowable IC power dissipation.
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PICmax =
TJ max − TIC _ amb
RϑJA
where, RθJA=128ºC/W (from IR1168 datasheet).
Because PRg1, 2 is known and supply current has already been calculated, this will
imply to limit the maximum VCC supply voltage for the IC (therefore the maximum
input power for IR1168)
PIC + PR g 1 + PR g 2
VCC max = max
I CC
The following charts show the maximum allowable VCC vs. maximum switching
frequency for different load capacitances (assuming Tjmax=125°C and
TIC_amb=55°C and 1Ω MOSFET internal gate resistor).
20
Maximum allowable V CC voltage [V]
19
18
17
16
15
14
Csync = 1nF
Csync = 2nF
13
Csync =5nF
Csync = 8nF
12
Csync = 10nF
11
50
100
150
200
250
300
350
400
450
500
Maximum synchronous HexFET switching frequency [kHz]
Figure 9: Max VCC supply voltage vs. switching frequency with Rg1, 2=3Ω
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20
19
Maximum allowable VCC voltage [V]
18
17
16
15
14
Csync = 1nF
Csync = 2nF
13
Csync =5nF
Csync = 8nF
Csync = 10nF
12
11
50
100
150
200
250
300
350
400
450
500
Maximum synchronous HexFET switching frequency [kHz]
Figure 10: Max VCC supply voltage vs. switching frequency with Rg1, 2=4Ω
From the two above charts, it is clear how the supply voltage and gate resistor
play a major role in the design trade off. In most commercial systems, the
minimum gate resistor value for loop damping will satisfy the thermal
requirements. If not, the procedure has to be iterated taking the following steps
Step 1: decrease the VCC to the lowest possible value through a series resistor 2 :
V
−V
RCC = supply CC
I CC
If this allows VCC to comply the thermal limit, then the gate resistor value can be
kept as designed.
2
It is worth mentioning the additional benefit of adding some series resistance to supply, which
provides an enhanced filtering effect with the local decoupling capacitor. For systems powered
from the output (no dedicated power through windings, etc.) this can result in smoother
operations.
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Step 2: Increase the gate resistor value. This can be of some effect if a small
resistor value has been selected.
c. Decoupling capacitor
Several techniques are possible for decoupling capacitor sizing, depending on
the converter topology and/or special requirements. The two most common
cases relevant here are IR1168 powered directly from either the output or from a
dedicated winding.
In the first case, in order to reduce the voltage ripple and possible noise, a good
design practice is to use a series resistor on the supply (if not already used for
thermal management reasons) and size the capacitor in order to obtain a low
pass filter with a pole frequency a couple of octaves below the minimum
operating switching frequency (this is not the stand-by operating frequency of the
converter)
2
Cdc _ min =
π ⋅ f SWmin ⋅ RCC
In case of operations through an auxiliary winding or winding tap, the decoupling
capacitor should be sized in order to allow one switching period operation even in
the absence of the main supply, with an acceptable voltage ripple ΔVCC
Cdc _ min =
I CC
f SWmin ⋅ ΔVCC
Design example
System data:
• f SWmax = 250kHz
•
f SWmin = 50kHz
•
TICamb = 70º C
•
Converter output voltage = 19V
Synchronous MOSFET: IRF7855PbF (60V/9.4mΩ max)
• Qg = 26nC @ Vgs = 10V
•
Qgd = 9.6nC @ Vgs = 10V
•
Ciss = 1.56nF
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a. IC current consumption calculation
C sync =
Qg − Qgd
= 1.6nF
Vgs
I CC = I QCC + 2 × f SWmax CsyncVghigh + 1.18 ⋅10−8 f SWmax = 13.7 mA
d. Supply series resistor and gate resistor design, and thermal verification
Assuming the total gate loop trace length is 15mm (0.6inch); Lg ≈ 15nH
Rgloop > 2
Lg
Ciss
= 3.97Ω
From IR1168 datasheet, driver pull down resistance rdown = 1.2Ω
Assume MOSFET internal gate resistance is 1Ω.
Hence, R g > 1.77Ω
Select Rg1, 2 = 1.8Ω
Let’s now verify the system thermally:
Pdr1 = 2 f SW max E g = 46.9mW
Therefore
⎛
Rg 1
Rg 1
+
PRg 1 = ⎜
⎜R +R
Rg1 + RSink
Source
⎝ g1
⎞ Pdr1
⎟⋅
= 19.9mW
⎟ 2
⎠
Assuming an IC maximum junction temperature of 100ºC,
PICmax =
TJ max − TIC _ amb
RϑJA
= 234mW
The maximum VCC voltage can now be calculated as -
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VCCmax =
PICmax + PRg
I CC
= 20V
The available supply voltage is below this value and hence, the IC supply can be
directly generated from the converter output (series resistor recommended).
RCC = 50Ω
This resistor will dissipate a maximum of 9.4mW at f SWmax .
b. Decoupling capacitor
Since this system can be directly powered from the converter output, the filtering
criterion is the preferred one for sizing the decoupling capacitor. Therefore,
Cdc _ min =
2
π ⋅ f SW ⋅ RCC
= 255nF
min
Select standard value Cdc = 270nF
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Layout guidelines and examples
¾ IC placement
Due to the nature of the control, based on fast and accurate voltage sensing, it is
highly recommended to layout the circuit in order to keep the IR1168 as close as
possible to the two SR MOSFETs.
¾ IC Decoupling Capacitor
The key element to proper bypassing for the IC is the physical location of the
bypass capacitor and its connections to the power terminals of the control IC. In
order for the capacitor to provide adequate filtering, it must be located as close
as physically possible to the VCC and GND pins and connected through the
shortest available path.
¾ Differential Sensing for VD/VS
IR1168 offers differential voltage sensing for both the synchronous MOSFETs. It
is recommended to minimize the trace lengths and to keep them separated from
the power ground as much as possible. For sensing optimization related to
MOSFET package inductance, please refer to the appendix.
When a sensing resistor is used for current feedback in the rectifier power loop, it
is highly recommended not to include it in the driving and sensing loops as
shown in Figure 11 (this will cause some noise on the VCC but will be filtered by
the decoupling capacitor and RCC series resistor).
SR1
Rcc
Cdc
Rg1
1
2
3
4
GATE1
GATE2
VCC
GND
VS1
VS2
VD1
VD2
8
7
6
Rg2
5
+
-
IR1168S
OUTPUT
SR2
Rsense
Figure 11: Output current sense resistor placement (if present)
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¾ Gate Drive Loop
Minimizing the length of the gate drive loop will reduce the requirements for loop
damping and would enhance system robustness. Once the layout is finalized, a
“rule of thumb” estimation consists in measuring the physical loop trace length in
assuming each millimeter (1mm = 39.37mils) accounts for 1nH. Other methods
include measurement (low frequency RCL meters or current slope for a given
voltage pulse) or FEM simulations.
¾ Layout examples
to supply
Figure 12: Single layer board, SO8 MOSFETs and surface-mount gate resistors
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Figure 13: Single layer board, DFET MOSFETs and surface-mount gate resistors
Figure 14: Single layer board, TO220 MOSFETs and through-hole gate resistors
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Appendix
Symbols list
VTH1: IR1168 turn-off threshold
VTH2: IR1168 turn-on threshold
VTH3: IR1168 periodic logic (reset) threshold
RAC: Equivalent AC resistance for resonant tank AC analysis
RDSon: synchronous rectifier MOSFET channel ON resistance
ID: synchronous rectifier MOSFET drain current
VDS: synchronous rectifier MOSFET drain to source voltage
MOT: IR1168 minimum ON time parameter
tblank: IR1168 turn off blanking time
Cdc: IR1168 decoupling capacitor on Vcc
Rg1, 2: SR MOSFET gate drive loop resistance external to IR1168 IC
RCC: supply voltage series resistor value (Vsupply to VCC)
fSWmax: converter maximum operating switching frequency
fSWmin: converter minimum operating switching frequency
Qg: SR MOSFET total gate charge
Qgd: SR MOSFET gate to drain (Miller) charge
Vgs: SR MOSFET gate to source voltage
Vghigh: IR1168 gate drive output voltage
IQCC: IR1168 quiescent current
Lg: total gate loop parasitic inductance
Ciss: SR MOSFET input capacitance
Eg1, 2: Energy stored in the gate capacitance of each SR MOSFET
Pdr1, 2: Total power dissipated by the gate drive function for each SR MOSFET
RSource: gate driver source resistance
RSink: gate driver sink resistance
PRg1, 2: Power dissipated in each gate resistor
PICmax: IR1168 IC maximum power dissipation
TIC_amb: IC environment temperature (most cases is PCB temperature where IC is
soldered)
RθJA: IR1168 IC junction to ambient thermal resistance
VCC: Supply voltage on IR1168 Vcc pin
ICC: IR1168 IC supply current
Vsupply: System available supply voltage for SR function
Cdc_min: minimum calculated decoupling capacitance
ΔVCC: supply peak to peak ripple voltage on IR1168 VCC pin
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References
[1] IR1168 SmartRectifier™ control IC datasheet, International Rectifier, March
2008.
[2] “Design of Secondary Side Rectification using IR1167 SmartRectifier™
Control IC” International Rectifier Application Note AN1087, 2006.
[3] Adnaan Lokhandwala, Maurizio Salato & Marco Soldano “Dual
SmartRectifierTM – DirectFET Chipset Solution Overcomes Package Induced
Sensing Limitations Allowing High Performance Synchronous Output
Rectification in LCD TV Power Supplies”, Proceedings of PCIM China 2007.
[4] Adnaan Lokhandwala, Maurizio Salato & Marco Soldano “SmartRectifierTM
control simplifies output synchronous rectification in DC-DC series resonant
converters”, Proceedings of PCIM Europe 2006.
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