Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

Application Note AN-1123
Bootstrap Network Analysis: Focusing on the
Integrated Bootstrap Functionality
By Andrea Merello
Table of Contents
Page
1.
Introduction ...............................................................................2
2
Theoretical considerations about the bootstrap topology .....3
2.1
Bootstrap resistor contribution ..............................................4
2.2
Bootstrap capacitor contribution.............................................4
3
Sizing the bootstrap circuit using the integrated bootFET ...9
4
Test bench measurements with no load current ...................12
5
Considering the bootstrap circuit for varying loads .............16
6
Limitations of the integrated bootstrap ..................................19
7
Conclusions ..............................................................................20
The intent of this document is to develop the bootstrap sizing theory and practice, while
focusing in particular on topologies where the gate driver IC features integrated
bootstrap functionality.
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1
1. Introduction
One of the most widely used methods to supply power to the high-side drive circuitry of a
gate driver IC is the bootstrap power supply. The bootstrap power supply consists of a
bootstrap diode and a bootstrap capacitor; this circuit is illustrated in Figure 1.
bootstrap
diode
bootstrap
resistor
DC+
R
VCC
boot
VF
VB
VBS
bootstrap
capacitor
V GE
I
V
LOAD
VS
CC
V CEon
V FP
VSS
DC-
Figure 1: bootstrap power supply
This method has the advantage of being both simple and low-cost. However, the
requirement to refresh the charge on the bootstrap capacitor may result in limitations on
the power converter’s duty-cycle and the power switch’s on-time. Proper capacitor and
bootstrap resistance selection can drastically reduce these limitations.
The maximum voltage that the bootstrap capacitor (VBS) can reach is dependent on the
elements of the bootstrap circuit shown in Fig. 1. The voltage drop across RBOOT, VF of
the bootstrap diode, the drop across the low-side switch (VCEON or VFP, depending on the
direction of current flow through the switch), and if present, the drop across a shunt
resistor (not shown in Fig. 1) placed between the low-side switch’s emitter and the DCrail, all need to be considered.
The intent of this document is to develop the bootstrap sizing theory and practice, while
focusing in particular on topologies where the gate driver IC features the integrated the
bootstrap “diode”1.
1
The integrated bootstrap “diode” is described in this document in a simplified way by means of a resistor and an ideal
switch in series. It may also be referenced as “bootstrap FET” as reflecting the real physical implementation in the silicon
design.
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2
2. Theoretical considerations about the bootstrap topology
Some preliminary considerations need to be understood before examining the details of
sizing the bootstrap circuit that is used in the half-bridge topology. The following
simplified schematic can aid to develop this understanding (see Figure 2).
This representation of the bootstrap circuit (as shown in Fig. 2) eases the computation of
the VBS behavior as a function of the S1 switch state, or, as a function of its duty cycle
(D= duty cycle= TON/T≡1-D*)2, gate charge, leakage currents, and bootstrap resistor and
capacitor.
Figure 2: Simplified bootstrap schematic
VBSMAX, in general, represents the supply voltage (VCC in Figure 1) plus or minus the
bootstrap circuit’s static drops.
It is important to understand that in the discussion that follows, the duty cycle of switch
S1 is assumed to have reached steady state and will remain constant. This implies that
the formulas reflect results that are valid considering the duty cycle is constant in time.
Later, some important considerations will then be derived while dealing with the “AC”
response of the system (i.e., as duty cycle varies in time).
“Static” equations: VBS behavior in one PWM cycle:
The voltage (VBS) that develops across the bootstrap capacitor (CBOOT) is, in general,
characterized by two contributions (according to Fig. 2). The first is represented by the
voltage drop caused across the bootstrap resistor during the period in which the ideal
switch (S1) is on (TON). The second is a superimposed ripple, characteristic of the
switching nature of the system; the magnitude of the AC ripple is primarily determined
by the sizing of the bootstrap capacitor and can be calculated when S1 is off (TOFF). For
the remainder of this discussion, VBSMAX is defined as the maximum obtainable value for
VBS; this is represented by the VBSMAX generator in Figure 2.
2
TON is the on time of the switch, which represents the time while the gating signal of the low-side IGBT is active.
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2.1 Bootstrap resistor contribution
The total charge that has to be supplied to the circuit by the supply (VBSMAX) during the
switching period (TS) is shown in Eq.1.
*
*
QTOT = QG + I leak ⋅ TS
(EQ.1)
The variable QG is defined as the total amount of charge needed by the gate of the power
device and the gate driver level shifter, and ILEAK takes into account the DC current that
has to be supplied to the gate driver high side circuitry.
Considering that S1 is driven by a PWM waveform, and that charge is provided through
the bootstrap resistor only during the TON time, then the average current flowing through
the bootstrap resistor is as calculated in Eq.2.
*
I=
*
QG + I leak ⋅ TS QG ⋅ f + I leak
=
Ton
D
(f =
(Eq. 2)
T
1
; D = ON )
TS
TS
The average voltage drop across RBOOT is then defined by the Eq. 3.
*
VRboot
Q ⋅ f + I leak
= G
⋅ Rboot
D
(Eq. 3)
2.2 Bootstrap capacitor contribution
The total charge supplied by the bootstrap capacitor to the high-side circuitry can be
calculated by Eq. 4.
*
*
QTOT = QG + I leak ⋅ Toff = QG + I leak ⋅ (1 − D) ⋅ TS
(Eq. 4)
The ripple amplitude for VBS can be determined by considering Eq. 5.
∆VBS =
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QTOT
Cboot
AN-1123
(Eq. 5)
4
The shape of VBS as a function of time is represented in Figure 3, where the various
contributions have been distinguished. The calculation for Vdrop (as shown in Fig. 3)
given by Eq. 6.
Vdrop = VRboot + ∆VBS / 2 3
(Eq. 6)
The above mentioned formula is valid only when the duty cycle is low enough such that
VRboot becomes greater than ∆VBS/2. This happens approximately when the recharge time
is enough to fully charge the bootstrap capacitor (for this calculation, we will assume the
capacitor is fully charged after a ∆t of 4 time constants). Equation 7 shows the duty
cycle’s boundary condition.
D<
4 ⋅ Rboot ⋅ Cboot
TS
. (Eq. 7)
Figure 3: VBS waveform
4 ⋅ Rboot ⋅ Cboot
, Eq. 6 is no longer valid and Vdrop becomes equal to ∆VBS
TS
as shown in Fig. 4.
Whenever D >>
Vdrop = ∆VBS
(Eq. 8)
An important consideration that must be made is that while the VBS ripple depends only
on the bootstrap capacitor, the average voltage drop (Vdrop) from the maximum reachable
VBS (VBSMAX) depends only on the bootstrap resistor.
3
Vdrop represents the drop of VBS from the maximum value that it can reach (VBSMAX)
considering all the elements of the bootstrap circuit, that are not mentioned in this
simplified description. These elements will be described further ahead.
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QG
Vdrop
VBSmax
VB
Ileak*T
VS
Figure 4: Vdrop for
D >>
4 ⋅ Rboot ⋅ Cboot
TS
It should be noted that even with a reasonably large bootstrap capacitor (to make ∆VBS
negligible) VRboot drop may be large. This contribution to the VBS drop fixes a limit to the
minimum acceptable duty cycle for a given bootstrap resistor. Equation 9 shows DMIN
while neglecting the ∆VBS contribution and that Vdrop is the maximum acceptable drop
from the supply.
*
Q ⋅ f + I leak
D MIN = G
⋅ Rboot
Vdrop
(Eq. 9)
Example:
QG* = 40 nC, f = 20 kHz, Ileak = 200 µA, Rboot = 220 Ω, Vdro p= 2 V (VBS = VCC - Vdrop = 13
V) . The minimum acceptable duty cycle will be 11%.
A simulation has been performed using the following parameters and the results are
shown in Figs. 5 and 6. For this simulation, Rboot = 220 Ω, QG = 40 nC, Ileak = 200 µA, f
= 1/TS = 20 kHz, the DMIN duty cycles are either D=10% or D=30%, and Cboot = 47 nF or
1µF (pre-charged to VBSmax = 15 V).
Below is an example of the calculation for the case where Cboot equals 47 nF and the duty
cycle is 10%.
4 ⋅ Rboot ⋅ C boot 4 ⋅ 220 Ω ⋅ 1 µF
D = 10% <<
=
= 82.7%
TS
50 µs
then
Vdrop = VRboot + ∆VBS / 2
The expected VRboot for the worst case (D=10%) is:
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40 nC ⋅ 20 kHz + 200 µA
⋅ 220 Ω = 2.2 V
10%
V Rboot =
The expected ripple (Cboot = 47 nF) is:
∆VBS =
40 nC + 200 µA ⋅ (1 − 10%) ⋅ 50 µs
= 1V
47 nF
Vdrop = VRboot + ∆VBS / 2 = 2.7 V ⇒ VBS = 12.3 V
Dynamic response:
The simulations plotted in Figure 5 and 6 are shown with Cboot equal to 47 nF or 1 µF and
the duty cycle equal to 10% or 30%. The green and yellow curves represent VBS with a
47 nF bootstrap capacitor. The purple and red curves represent VBS with a 1 µF bootstrap
capacitor.
Figure 6 shows the effect of the different bootstrap capacitors, which affects only the VBS
ripple (the average value is, in fact, kept constant).
Figure 5 shows the step response of the system starting with the bootstrap capacitor fully
charged to 15 V (D=100%). In particular this picture shows that the average VBS has a
behavior that is similar to a single pole system with a time constant that is calculated in
Eq. 10.
τ=
Rboot ⋅ Cboot
D
(Eq. 10)
This relationship between the duty cycle and the step response of the system allows us to
understand that for lower duty cycles, the time constant (τ) becomes larger (and thus the
response is slower) and that for higher duty cycles, the response is faster.
This behavior works as an adaptive filter for changes in the duty cycle. This can be seen
in a further simulation (see Fig. 7) in which a sinusoidal wave (40 Hz fundamental plus
the 3rd harmonic) modulated duty cycle is fed to the circuit (TS= 50 µs, electrical
frequency = fe).
In Figure 5 the parameters are Rboot = 220 Ω, Cboot = 1 µF and D = 10%.
τ=
220 ⋅ 1 µF
1
= 2.2 ms → fτ =
= 72 Hz
0.1
2πτ
The combination of Rboot = 220 Ω, Cboot = 1 µF and D = 10% is also shown.
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τ=
200 ⋅ 1 µF
1
= 733 µs → fτ =
= 217 Hz
0.3
2πτ
Figure 5: Bootstrap circuit parametric simulation: S1 duty cycle and bootstrap capacitor
1V
Figure 6: Ripple behavior for different Cboot
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15 V
14 V
13 V
12 V
rd
4
Figure 7: 40 Hz Sine plus 3 harmonic modulation of S1 duty cycle
*
*
As a drawback, QTOT = QG + I leak ⋅ Toff = QG + I leak ⋅ (1 − D) ⋅ TS increases for low duty
cycles. In this case, a larger bootstrap capacitor will do the job of keeping the ripple
under control and increasing the average time constant.
The dynamic response of the system is of particular interest. Fig. 8 shows the expected
(calculated) VBS for different electrical frequencies. The duty cycle is represented as a
function (sine + 3rd harmonic) of an angle (which is equal to 2πfe, where fe is the
electrical frequency of the rotor) which swings from 0° to 360°.
In the same plot, VBS voltages that are obtained with different fe are shown. An
additional note to mention regarding this figure is that the yellow curve, VBS (DC),
represents the curve obtained when using the static equations mentioned previously (Eqs.
3, 5, 6, & 8). The cyan curve is obtained with fe = 40 Hz as in the simulation of Fig. 7.
3. Sizing the bootstrap circuit using the integrated bootFET
As shown in Figure 1 the bootstrap circuit includes some components that must be taken
into account when sizing the bootstrap resistor and capacitor. In the case of using a gate
driver with integrated bootstrap functionality (e.g., those with an integrated bootstrap
FET), the external bootstrap diode is not used (for most applications) and the voltage
drop across the bootstrap FET replaces the VF typically considered during circuit
4
Same data as per previous pages: Rboot = 220 Ω, QG = 40 nC, Ileak = 200 µA, f=1/TS = 20
kHz
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analysis. The other elements that must be considered include power switch (e.g., IGBT),
the free wheeling diode in parallel with the switch, and any shunt resistors used on the
DC- rail or in series with the low-side switch and the DC- rail.
VBS vs. dutycycle at different rotor electrical
frequencies
1
15
0.9
14.5
0.8
VBS
0.6
0.5
13.5
VBS (DC)
0.4
VBS (fe=40Hz)
13
12.5
VBS (fe=100Hz)
0.3
VBS (fe=150Hz)
0.2
Duty cycle
0.1
12
0
100
LO duty cycle
0.7
14
200
300
0
400
angle
Figure 8: Expected VBS drop at different rotor electrical frequencies
Following the nomenclature used in the above paragraphs, VBSmax (see Figure 2 and 5) can
be computed as follows:
VBS max = VCC − VCE
(Eq. 11: bootstrap FET)
or
VBS max = VCC − VF − VCE
(Eq. 12: bootstrap diode)
Where Vcc is the low-side supply, VF is the forward drop of the bootstrap diode, VCE can
be either the voltage drop on the IGBT (when current is flowing into the power device) or
the forward biased voltage drop of the freewheeling diode (in this case, it is a negative
contribution which increases VBSMAX). In the worst case sizing, VCE is represented by the
VCEon of the low-side IGBT.
The following design example will consider a system as shown in Figure 9, where the
bootstrap FET is represented by an ideal switch and a resistor.
The first step in sizing the bootstrap circuit is to determine the minimum voltage drop
(Vdrop) when the high-side IGBT is on. Considering that a minimum gate voltage must be
provided to the IGBT’s gate (VGEmin), Vdrop is the maximum possible voltage drop of the
VBS supply, and is defined by the following formula:
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Vdrop ≤ VCC − VGE min − VCEon
(Eq. 13)
Figure 9: Bootstrap FET represented by ideal switch and Rboot
It should be noted that gate drivers from International Rectifier are equipped with under
voltage lock-out (UVLO) protection on the high-side gate drive where the VBS voltage is
monitored to ensure a minimum threshold; should the VBS decrease below this threshold,
the UVLO protection would engage and disable the gate driver IC. Therefore, the
minimum VGE should be greater than the high-side supply undervoltage negative going
threshold (VBSUV-).
VGE min > VBSUV −
The following factors that contribute to the discharge of the bootstrap capacitors voltage
(VBS) during the time that the low-side switch is off must also be considered.
− IGBT required gate charge during turn-on (QG);
− IGBT gate-source leakage current (ILK_GE);
− Floating section quiescent current (IQBS);
− Floating section leakage current (ILK)
− Bootstrap diode reverse bias leakage (ILK_DIODE)
− Charge required by the internal level shifters (QLS);
− Bootstrap capacitor leakage current (ILK_CAP);
− High-side maximum on time ((1-DMIN)*TS where DMIN is the minimum duty cycle).
ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other
types of capacitors are used. It is strongly recommend to use at least one low ESR
ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient
solution).
The total amount of charge that is removed from the bootstrap capacitor during the time
that the high-side device is referred to as QTOT (see Eq. 4) and can be calculated by Eq.
14.
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QTOT = QG + Q LS + ( I LK _ GE + I QBS + I LK + I LK _ CAP ) ⋅ (1 − DMIN ) ⋅ TS
*
= QG + I leak ⋅ (1 − DMIN ) ⋅ TS
The bootstrap capacitor can be chosen by using Cboot >
DMIN >
(Eq. 14)
QTOT
and verifying that:
Vdrop
4 ⋅ Rboot ⋅ Cboot
TS
so that Vdrop = ∆VBS (see Figure 4).
Let’s suppose the above equation is not verifiable, Vdrop may be calculated by
Vdrop = VRboot + ∆VBS / 2 . Using the formula mentioned in Eq. 3 and the known value of
Vdrop, VBS can be determined by VBS min = VCC − VCEon − Vdrop while remembering the VGEmin
requirement.
4. Test bench measurements with no load current
To provide a better example of the integrated bootstrap circuitry’s behavior/performance,
a comparison of some lab examples are included. There are three comparisons shown
and include:
ƒ 10 Ω bootstrap resistor and external bootstrap diode circuit
ƒ Integrated bootstrap circuitry
ƒ Parallel of integrated bootstrap circuitry and external bootstrap components
Test conditions:
ƒ PWM=20 kHz
ƒ Cboot=1 µF
ƒ Fundamental=25 Hz
ƒ Minimum pulse = 560 ns (modulation index=97.7%)
ƒ No load current
ƒ Gate driver IC: IR2136 (external bootstrap topology) or IRS2136D (integrated
bootstrap)
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Phase voltage
LO duty cycle
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
Figure 10: 10 Ω + diode external bootstrap circuit (560 ns min pulse)
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
Figure 11: Integrated bootstrap circuitry (560 ns min pulse)
It is interesting to note (see Fig. 11) the integrated bootstrap network provides a filtering
effect at the 25 Hz fundamental frequency. In the same picture VBS can be seen to reach
nearly 15 V without losing the forward drop of the bootstrap diode.
In this second example, the minimum pulse is increased to 5 µs and the modulation index
decreased to 80%.
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VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
Figure 12: Integrated bootstrap circuitry in parallel with external bootstrap components (560 ns
min pulse)
Test conditions:
ƒ PWM=20 kHz
ƒ Cboot=1 µF
ƒ Fundamental=25 Hz
ƒ Minimum pulse = 5 µs (modulation index=80%)
ƒ No load current
ƒ Gate driver IC: IR2136 (external bootstrap topology) or IRS2136D (integrated
bootstrap)
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
Figure 13: 10 Ω resistor + diode external bootstrap circuit (5 µs min pulse)
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VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
Figure 14: Integrated bootstrap circuitry (5 µs min pulse)
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
Figure 15: Integrated bootstrap circuitry in parallel with external Bootstrap components
(5 µs min pulse)
With a low modulation index, the integrated bootstrap circuitry provides results as good
as those obtained with the external bootstrap circuit at 25 °C.
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5. Considering the bootstrap circuit for varying loads
In the examples shown above, the tests do not consider the effect of the current delivered
(positive or negative) to the load. The effect of the load current influences the value of
VBSMAX. A description of this effect follows.
There are three different situations that can occur. The first is the case where ILOAD is
less than zero.
‚ ILOAD < 0; the load current flows into the low-side IGBT and generates a given
VCEon
VBSMAX = VCC (−VF ) − VCEon
(Eq. 15)
In this case, we find the lowest value for VBSMAX. This represents the worst case for the
sizing of the bootstrap capacitor. The low-side IGBT’s VCEON pulls up the VS node and
reduces the available voltage for charging the bootstrap supply. In the case of a circuit
that uses a shunt resistor in series with the IGBT, its voltage drop may influence the
result as well.
If we consider a small phase shift between the phase current and the phase voltage (a
phenomenon that happens when the phase duty cycle is high and the bootstrap capacitor
has more time to charge), depending on the magnitude of VCEON, the induced voltage
drop may be reduced.
In the second case, the load current is zero and the voltage drop across the switch can
be neglected. This situation was discussed above in this document and happens during
current zero crossings.
‚
ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected
V BSMAX = VCC (−V F )
(Eq. 16)
In the third case, the load current is positive and the voltage drop across the switch is due
to the drop that results from the freewheeling diode.
‚
ILOAD > 0; the load current flows through the freewheeling diode
VBSMAX = VCC (−VF ) + VFP
(Eq. 17)
In this case we have the highest value for VBSMAX. ILOAD flows into the free-wheeling
diode, the voltage drop of which increases the available voltage for charging VBS. The
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same consideration can be made for ILOAD < 0, but in this case the phenomenon happens
when the duty cycle is at a minimum (which helps by increasing VBSMAX).
Figure 16 shows the result of a simulation where the load current is phase shifted with the
applied voltage. The plots show the duty cycle (green), simulated VBS voltage (blue = 200
Ω bootstrap resistor, Cyan = 10 Ω bootstrap resistor + diode, Orange = maximum
achievable VBS) and the load current (red) positive entering the phase.
a
b
c
d
Figure 16: Simulation of VBS with variable duty cycle and load current phase
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The parameters for the simulation include:
IQBS = 150 µA;
ILK = 50 µA;
QLS = 1.2 nC;
QG = 40 nC;
TS = 50 µs (f=20 kHz);
VF=1 V;
Rboot =220Ω;
VCC = 15 V;
VCEon = 3 V;
VGEmin = 10 V; and
DMIN=10% (minimum duty cycle of the PWM carrier).
The schematic of the simulation is a modification of the circuit shown in Figure 2, to
allow us to consider the effects of VCEON and VFP (that have been idealized as having a
sinusoidal shape).
Now we’ll examine a series of test measurements that help us understand the VBS
behavior as a function of both modulation and current phase lag with voltage. The test
conditions are shown below (slightly different from previous test conditions).
ƒ PWM=20 kHz
ƒ Cboot=1 µF
ƒ Fundamental= 11 Hz
ƒ Minimum pulse = 367 ns (m=98.5%)
ƒ Load current (positive toward the inverter stage)= 5 A peak-peak
Phase current
(positive entering)
Current is changing sign:
From free wheeling diode VF
to VCEON drop
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
LO duty cycle
Figure 17: 10 Ω + external diode bootstrap circuit
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Phase current
(positive entering)
Current is changing sign:
From free wheeling diode VF
to VCEON drop
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
LO duty cycle
Figure 18: Integrated bootstrap circuitry
Phase current
(positive entering)
VBS -------------Æ
VBSUV -------------Æ
(8.2 V typ., 9 V max)
LO duty cycle
Figure 19: Integrate bootstrap circuitry with 17 V VCC supply
6. Limitations of the integrated bootstrap
The integrated bootstrap FET considered above follows the assumption that the bootstrap
FET is turned on only when LO is active (and the VS pin is tied to VSS). This working
principle leads to a waste of the deadtime period, which can be used for recharging the
bootstrap capacitor during low-side freewheeling recirculation. The topology which uses
the external bootstrap diode does not suffer from this issue. In most cases, (motor drive
applications usually have a max switching frequency of around 20 kHz, with deadtime
periods less than 3 µs), the resulting loss of charge is negligible.
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A second limitation, which is related to the integrated bootstrap is for noncomplementary switching schemes.
Phase
1/fs
Low
Side
1/fm
High
Side
dVt11
dVt2
dVt12
120
Vbsnom
60
120
60
t11
t2
t12
Vbsmin
t3
t3
Figure 20: Behavior of VBS voltage for 6-step non-complementary switching scheme
As an example, we considered the 6-step switching scheme with the high-side IGBT
chopped while the low-side IGBT remains off (see Figure 20). VBS charges only during
the period in which low-side IGBT is on (t3) and the Cboot charge is never refreshed
during high side switching period (t2).
A way to overcome this problem is, while chopping the high-side switch, to switch the
low-side in a complementary way; this will allow a refresh of the bootstrap capacitor. In
the case of complementary switching, the equations developed in section 2 apply.
International Rectifier provides also devices with a different integrated bootstrap turn-on
strategy, which are suitable for non-complementary PWM schemes. This topic is not
discussed in this application note.
7. Conclusions
We considered the effects of the bootstrap resistor and capacitor on the charge of the
floating supply. The main issue introduced by the resistive bootstrap circuit is an average
voltage drop that impacts the minimum duty cycle obtainable for the application.
Examples have been shown that this effect is not preventing the use of integrated
bootstrap topology for sinusoidal drive.
The equations that have been obtained are valid in general, and must be verified by the
use to determine if the integrated bootstrap topology can match the design requirements.
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This Application Note mainly describes applications which use the 3-phase space vector
(or 3-phase sinusoidal + 3rd harmonic) modulation. Other kinds of modulations (e.g., 2phase space vector, 6-step, etc.) have to be considered separately.
Low cost applications can benefit from the integration of the bootstrap functionality by
reducing the number of external components (3 HV diodes + 1 resistor) and saving space
on the board. This solution can be particularly appealing to modules that utilize a high
degree of integration.
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