FlashFlex MCU A Microchip Technology Company SST89E54RD2A/RDA / SST89E58RD2A/RDA Programming Specification Introduction This document provides instructions to help programming vendors qualify the SST FlashFlex microcontrollers. Functional Blocks 8051 CPU Core ALU, ACC, B-Register, Instruction Register, Program Counter, Timing and Control Interrupt Control Oscillator Flash Control Unit Watchdog Timer SuperFlash EEPROM Primary Block 16K/32K x8 RAM 1K x8 8 I/O I/O Port 0 Secondary Block 8K x8 10 Interrupts 8 Security Lock I/O I/O Port 1 8 I/O I/O Port 2 8 Timer 0 (16-bit) I/O I/O Port 3 4 Timer 1 (16-bit) I/O Port 4 Timer 2 (16-bit) I/O SPI PCA Enhanced UART 1339(01) B1.0 Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. DS25115A 1 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification Flash Memory Programming The device’s internal flash memory can be programmed or erased using the External Host Programming mode. External Host Programming Mode External host programming mode allows the user to program the flash memory directly without using the CPU, see Table 1. External host mode is entered by forcing PSEN# from a logic high to a logic low while RST input is held continuously high. The device will stay in external host mode as long as RST = 1 and PSEN# = 0. A Read-ID operation is necessary to “arm” the device in external host mode, and no other external host mode commands can be enabled until a Read-ID is performed. In external host mode, the internal flash memory blocks are accessed through the re-assigned I/O port pins by an external host, such as a MCU programmer, a PCB tester, or a PC-controlled development board. See Figure 2 for I/O port pin details. Table 1: External Host Mode Commands1 P2[6] P0[7:0] P3[5:4] P2[5:0] P1[7:0] VIL VIL DO AH AL VIL VIH X X X VIH VIL VIH X X X VIL VIH VIH X AH AL VIH VIH VIH VIL DI AH AL VIH VIH VIL VIL DO AH AL Operation RST PSEN# PROG#/ ALE EA# P3[7] P3[6] P2[7] Read-ID VIH1 VIL VIH VIH VIL VIL Chip-Erase VIH1 VIL VIH VIL VIL Block-Erase VIH1 VIL VIH VIH Sector-Erase VIH1 VIL VIH VIH Byte-Program VIH1 VIL VIH Byte-Verify (Read) VIH1 VIL VIH VIH Select-Block0 VIH1 VIL VIH VIH VIL VIL VIH X 55H X Select-Block1 VIH1 VIL VIH VIH VIL VIL VIH X A5H X Prog-SC0 VIH1 VIL VIH VIH VIL VIL VIH X 5AH X Prog-SC1 VIH1 VIL VIH VIH VIL VIL VIH X AAH X Prog-SB1 VIH1 VIL VIH VIH VIH VIH VIH X X X Prog-SB2 VIH1 VIL VIH VIL VIL VIH VIH X X X Prog-SB3 VIH1 VIL VIH VIL VIH VIL VIH X X X Enable-Clock-Double VIH1 VIL VIH VIH VIL VIL VIL X 55H X T0-0.0 25115 1. External Host programming mode is guaranteed at 25°C (room temperature) only 2. Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of the above input pins are invalid and may result in unexpected behaviors. Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output. ©2011 Silicon Storage Technology, Inc. DS25115A 2 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification VSS VDD RST 0 Port 0 Input/Output Data Bus 6 7 0 0 1 1 2 2 Ready/Busy# Address Bus A15-A14 3 A14 4 A15 5 Flash Control Signals Port 2 Address Bus A13-A8 3 4 Port 3 5 6 7 Flash Control Signals 7 6 0 Port 1 Address Bus A7-A0 6 7 EA# ALE/PROG# PSEN# 1339(01) F01.0 Figure 2: I/O Pin Assignments for External Host Mode Product Identification The Read-ID command accesses the signature bytes that reads and returns the device ID and identifies the manufacturer as SST, see Table 2. External programmers primarily use these signature bytes in the selection of programming algorithms. The Read-ID command is selected by the command code of 0H on P3[7:6] and P2[7:6]. See Figure 3 for timing waveforms. Table 2: Product Identification Manufacturer’s ID Address Data 30H BFH Device ID SST89E54RD2A/RDA 31H 9FH SST89E58RD2A/RDA 31H 9BH T0-0.0 25115 Arming Command An arming command sequence must take place before any external host mode sequence command is recognized by the device. This prevents accidental triggering of external host mode commands due to noise or programmer error. The arming command is as follows: 1. PSEN# goes low while RST is high. This sets the machine in external host mode, re-configuring the pins, and turning on the on-chip oscillator. 2. A Read-ID command is issued, and after 1 ms the external host mode commands can be issued. After the above sequence, all other external host mode commands are enabled. Before the Read-ID command is received, all other external host mode commands received are ignored. ©2011 Silicon Storage Technology, Inc. DS25115A 3 12/11 FlashFlex MCU A Microchip Technology Company SST89E54RD2A/RDA / SST89E58RD2A/RDA Programming Specification External Host Mode Commands The external host mode commands are Read-ID, Chip-Erase, Block-Erase, Sector-Erase, Byte-Program, Byte-Verify, Prog-SB1, Prog-SB2, Prog-SB3, Prog-SC0, Select-Block0, Select-Block1. See Table 1 for all signal logic assignments, Figure 2 for I/O pin assignments, and Table 4 for the timing parameters. The critical timing for all Erase and Program commands is generated by an on-chip flash memory controller. The high-to-low transition of the PROG# signal initiates the Erase or Program commands, which are synchronized internally. The Read commands are asynchronous reads, independent of the PROG# signal level. A detailed description of the external host mode commands follows. The Select-Block0 command enables Block 0 to be programmed in external host mode. Once this command is executed, all subsequent external host Commands will be directed at Block 0. See Figure 4 for timing waveforms. The Select-Block1 command enables Block 1 (8 KByte Block) to be programmed. Once this command is executed, all subsequent external host Commands that are directed to the address range below 2000H will be directed at Block 1. The Select-Block1 command only affects the lowest 8 KByte of the program address space. For addresses greater than or equal to 2000H, Block 0 is accessed by default. Upon entering external host mode, Block 1 is selected by default. See Figure 4 for timing waveforms. The Chip-Erase, Block-Erase, and Sector-Erase commands are used for erasing all or part of the memory array. Erased data bytes in the memory array will be erased to FFH. Memory locations that are to be programmed must be in the erased state prior to programming. The Chip-Erase command erases all bytes in both memory blocks, regardless of any previous SelectBlock0 or Select-Block1 commands. Chip-Erase ignores the Security Lock status and will erase the Security Lock, returning the device to its Unlocked state. The Chip-Erase command will also erase the SC0 bit. Upon completion of Chip-Erase command, Block 1 will be the selected block. See Figure 5 for timing waveforms. The Block-Erase command erases all bytes in the selected memory blocks. This command will not be executed if the security lock is enabled. The selection of the memory block to be erased is determined by the prior execution Select-Block0 or Select-Block1 command. See Figure 6 for the timing waveforms. The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory is 128 Bytes. This command will not be executed if the Security lock is enabled. See Figure 7 for timing waveforms. The Byte-Program command is used for programming new data into the memory array. Programming will not take place if any security locks are enabled. See Figure 8 for timing waveforms. The Byte-Verify command allows the user to verify that the device correctly performed an Erase or Program command. This command will be disabled if any security locks are enabled. See Figure 11 for timing waveforms. The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits, the functions of these bits are described in the Security Lock section and also in Table 9-1. Once programmed, these bits can only be erased through a Chip-Erase command. See Figure 9 for timing waveforms. Prog-SC0 command programs SC0 bit, which determines the state of SFCF[0] out of reset. Once programmed, SC0 can only be restored to an erased state via a Chip-Erase command. See Figure 10 for timing waveforms. ©2011 Silicon Storage Technology, Inc. DS25115A 4 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification External Host Mode Clock Source In external host mode, an internal oscillator will provide clocking for the device, and the oscillator is unaffected by the clock doubler logic. The on-chip oscillator will be turned on as the device enters external host mode; i.e. when PSEN# goes low while RST is high. During external host mode, the CPU core is held in reset. Upon exit from external host mode, the internal oscillator is turned off. Flash Operation Status Detection Via External Host Handshake The device provides two methods for an external host to detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle can be detected by: 1. monitoring the Ready/Busy# bit at P3[3]; 2. monitoring the Data# Polling bit at P0[3]. Ready/Busy# (P3[3]) The progress of the flash memory programming can be monitored by the Ready/Busy# output signal. P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the flash programming operation is completed to indicate the ready status. Data# Polling (P0[3]) During a Program operation, any attempts to read (Byte-Verify), while the device is busy, will receive the complement of the data of the last byte loaded (logic low, i.e. “0” for an Erase) on P0[3] with the rest of the bits “0”. During a Program operation, the Byte-Verify command is reading the data of the last byte loaded, not the data at the address specified. Instructions to Perform External Host Mode Commands To program data into the memory array, apply power supply voltage (VDD) to VDD and RST pins, and perform the following steps: 1. Maintain RST high and set PSEN# from logic high to low, in sequence according to the appropriate timing diagram. 2. Raise EA# High (VIH). 3. Issue Read-ID command to enable the external host mode. 4. Verify that the memory blocks or sectors for programming is in the erased state, FFH. If they are not erased, then erase them using the appropriate Erase command. 5. Select the memory location using the address lines (P3[5:4], P2[5:0], P1[7:0]). 6. Present the data in on P0[7:0]. 7. Pulse ALE/PROG#, observing minimum pulse width. 8. Wait for low to high transition on Ready/Busy# (P3[3]). 9. Repeat steps 5 - 8 until programming is finished. 10. Verify the flash memory contents. ©2011 Silicon Storage Technology, Inc. DS25115A 5 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification Additional Read Commands in External Host Mode The procedure to issue additional read commands, shown in Table 3 below, is the same as the read ID command format, only the address is changed. Here is a short list of useful features: • • • Read the status of the security bits (SB1_i, SB2_i, SB3_i). Read the configuration bits (SC0_i) status. Read the clock mode (EDC_i) status. Note: Commands shown in Table 3 are not the ARMING type. Table 3: Additional Read Commands in External Host Mode Address Data 60H X X X X SC0_i SB1_i SB2_i 61H X X X X X X EDC_i SB3_i X T0-0.0 25115 Note: X = Don’t care ©2011 Silicon Storage Technology, Inc. DS25115A 6 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification Table 4: External Mode Flash Memory Programming/Verification Parameters1 Parameter2,3 Symbol Min Reset Setup Time TSU 3 µs Read-ID Command Width TRD 1 µs PSEN# Setup Time TES 40 µs Address, Command, Data Setup Time TADS 0 ns Chip-Erase Time TCE 150 ms Block-Erase Time TBE 100 ms Sector-Erase Time TSE 30 ms Program Setup Time Address, Command, Data Hold Max Units TPROG 1.2 µs TDH 0 ns Byte-Program Time4 TPB 50 µs Select-Block Program Time TPSB 500 ns Re-map or Security bit Program Time TPS 80 µs Verify Command Delay Time TOA 50 ns Verify High Order Address Delay Time TAHA 50 ns Verify Low Order Address Delay Time TALA 50 ns T0-0.0 25115 1. 2. 3. 4. For IAP operations, the program execution overhead must be added to the above timing parameters. Program and Erase times will scale inversely proportional to programming clock frequency. All timing measurements are from the 50% of the input to 50% of the output. Each byte must be erased before programming. ©2011 Silicon Storage Technology, Inc. DS25115A 7 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification Flash Memory Programming Timing Diagrams with External Host Mode TSU RST TES PSEN# ALE/PROG# EA# TRD TRD P2[7:6] ,P3[7:6] 0000b 0000b P3[5:4] ,P2[5:0] ,P1 0030H 0031H P0 BFH Device ID Device ID = See Table 3-2, Product Identification 1339(01) F02.0 Figure 3: Read-ID Reads chip signature and identification registers at the addressed location. TSU RST TES PSEN# TADS ALE/PROG# TPROG TDH EA# P3[3] TPSB P3[5:4], P2[5:0] A5H/55H P3[7:6], P2[7:6] 1001b 1339(01) F03.0 Figure 4: Select-Block1 / Select-Block0 Enables the selection of either of the flash memory blocks prior to issuing a Byte-Verify, Block-Erase, Sector-Erase, or Byte-Program. ©2011 Silicon Storage Technology, Inc. DS25115A 8 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification TSU RST TES PSEN# TADS ALE/PROG# TPROG TDH EA# TCE P3[3] P3[7:6], P2[7:6] 0001b 1339(01) F04.0 Figure 5: Chip-Erase Erases both flash memory blocks. Security lock is ignored and the security bits are erased too. TSU RST TES PSEN# TADS ALE/PROG# TPROG TDH EA# TBE P3[3] P3[7:6], P2[7:6] 1101b 1339(01) F05.0 Figure 6: Block-Erase Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. ©2011 Silicon Storage Technology, Inc. DS25115A 9 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# P3[3] TSE P3[7:6], P2[7:6] 1011b P3[5:4], P2[5:0] AH P1 AL 1339(01) F06.0 Figure 7: Sector-Erase Erases the addressed sector if the security lock is not activated on that flash memory block. ©2011 Silicon Storage Technology, Inc. DS25115A 10 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# P3[3] TPB P3[5:4], P2[5:0] AH P1 AL P0 DI P3[7:6], P2[7:6] 1110b 1339(01) F07.0 Figure 8: Byte-Program Programs the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte-Program operation is only allowed when the security lock is not activated on that flash memory block. TSU RST TES PSEN# TADS ALE/PROG# TPROG TDH EA# P3[3] TPS P3[7:6], P2[7:6] 1111b / 0011b / 0101b 1339(01) F08.0 Figure 9: Prog-SB1 / Prog-SB2 / Prog-SB3 Programs the Security bits SB1, SB2 and SB3 respectively. Only a Chip-Erase will erase a programmed security bit. ©2011 Silicon Storage Technology, Inc. DS25115A 11 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# P3[3] TPS P3[5:4], P2[5:0] 5AH / AAH P3[7:6], P2[7:6] 1001b 1339(01) F09.0 Figure 10:Prog-SC0 Programs the start-up configuration bit SC0. Only a Chip-Erase will erase a programmed SC0 bit. TSU RST TES PSEN# ALE/PROG# EA# TOA 1100b P3[7:6], P2[7:6] TAHA DO P0 TALA AL P1 AH P3[5:4], P2[5:0] 1339(01) F10.0 Figure 11:Byte-Verify Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. ©2011 Silicon Storage Technology, Inc. DS25115A 12 12/11 FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Programming Specification Table 5: Revision History Revision 00 01 A Description • • • • • Initial release of programming spec Removed SST89V54RD2A/RDA / SST89V58RD2A/RDA globally Applied new document format Released document under letter revision system Updated Spec number from S71339(01) to DS25115 Date Nov 2006 Feb 2008 Dec 2011 ISBN:978-1-61341-896-3 © 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com ©2011 Silicon Storage Technology, Inc. DS25115A 13 12/11