AN10273 Power MOSFET single-shot and repetitive avalanche ruggedness rating Rev. 3 — 10 December 2015 Application note Document information Info Content Keywords power MOSFET, single-shot, avalanche, ruggedness, safe operating condition Abstract Power MOSFETs are normally measured based on single-shot Unclamped Inductive Switching (UIS) avalanche energy. This application note describes in detail, the avalanche ruggedness performance, fundamentals of UIS operation and appropriate quantification method for the safe operating condition. AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating Revision history Rev Date Description 3 20151210 Section 2: added Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 1. Introduction Electronic applications have progressed significantly in recent years and have inevitably increased the demand for an intrinsically rugged power MOSFET. Device ruggedness defines the capacity of a device to sustain an avalanche current during an unclamped inductive load switching event. The avalanche ruggedness performance of a power MOSFET is normally measured as a single-shot Unclamped Inductive Switching (UIS) avalanche energy or EDS(AL)S. It provides an easy and quick method of quantifying the robustness of a MOSFET in avalanche mode. However, it does not necessarily reflect the true device avalanche capability (see Ref. 1, Ref. 2 and Ref. 3) in an application. This application note explains the fundamentals of UIS operation. It reviews the appropriate method of quantifying the safe operating condition for a power MOSFET, subjected to UIS operating condition. The application note also covers the discussions on repetitive avalanche ruggedness capability and how this operation can be quantified to operate safely. 2. Single-shot and repetitive avalanche definitions Single-shot avalanche events are avalanche events that occur due to a fault condition in the application such as electrical overstress. The application does not have an avalanche designed into its operation. However, repetitive avalanche refers to the applications where avalanche is an intended operation mode of the MOSFET. Here, avalanche is a designed function and is independent of the number of avalanche events. Any customer wishing to operate outside the current avalanche ratings may be considered on an application basis. Contact your local sales team for more information. 3. Understanding power MOSFET single-shot avalanche events The researchers and the industry have established single-shot avalanche capability of a device (see Ref. 1, Ref. 2 and Ref. 3). The test is carried out on a simple unclamped inductive load switching circuit, as shown in Figure 1. / GUDLQ JDWH JDWHYROWDJH 5 VRXUFH 9'' DDM Fig 1. Unclamped inductive load test circuit for MOSFET ruggedness evaluation 3.1 Single-shot UIS operation A voltage pulse is applied to the gate to turn on the MOSFET, as shown in Figure 2. It allows the load current to ramp up according to the inductor value (L) and the drain supply voltage (VDD). The phenomenon is shown in Figure 3 and Figure 4. At the end of the gate AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating pulse, the MOSFET is turned off. The current in the inductor continues to flow, causing the voltage across the MOSFET to rise sharply. This overvoltage is clamped at breakdown voltage (VBR) until the load current reaches zero, as illustrated in Figure 3. Typically, VBR is: V BR 1.3 V BR DSS (1) The peak load current passing through the MOSFET before turn off is the non-repetitive drain-source avalanche current (IDS(AL)S) of the UIS event. IDS(AL)S is illustrated in Figure 4. The following expression is used to determine the rate at which the avalanche current decays, which is dependent on the inductor value: dI DS AL S V BR – V DD ----------------------- = – ------------------------dt AL L (2) The peak drain-source avalanche power (PDS(AL)M) dissipated in the MOSFET is shown in Figure 5. It is a product of the breakdown voltage (VBR) and the non-repetitive drain-source avalanche current (IDS(AL)S); see Figure 3 and Figure 4. The avalanche energy dissipated is the area under the PAV waveform and is estimated from the following expression: P DS AL M t AL E DS AL S = ------------------------------------2 (3) or V BR 1 2 E DS AL S = --- -------------------------- LI DS AL S 2 V BR – V DD (4) Another crucial parameter involved in a MOSFET avalanche event is the junction temperature. After the avalanche event () has begun, the following expression is used to determine the transient junction temperature variation during device avalanche at a given time: dZ th – t T j = P AV t ---------------------- dt dt (5) 0 where Zth is the power MOSFET transient thermal impedance. Alternatively, the following expression approximates the maximum Tj: 2 T j max --- P DS AL M Z th t 2 AL 3 Assuming that Tj(max) occurs at tAL/2, Z th t (6) AL 2 is the transient thermal impedance measured at half the avalanche period tAL. Therefore, the maximum junction temperature resulting from the avalanche event is: T j max T j max + T j (7) where Tj refers to the junction temperature prior to turn off. AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 3.1.1 Single-shot UIS waveforms 9'6 9%5 9*6 9%5'66 21 9'' 2)) WLPH WLPH W$/ DDM Fig 2. Gate-source voltage, VGS Fig 3. DDM Drain-source voltage, VDS 3 ,' 3'6$/0 ,'6$/6 DUHDLQ3'6$/WULDQJOH DYDODQFKHHQHUJ\ ('6$/6GLVVLSDWHG WLPH WLPH W$/ Fig 4. 9'' W$/ DDM Drain current, ID Fig 5. DDM Peak drain-source avalanche power, PDS(AL)M 7M 7MPD[ 7MPD[ 7M WLPH W$/ Fig 6. DDM Transient junction temperature profile of MOSFET during an avalanche event 3.2 Single-shot avalanche ruggedness rating The failure mechanism for a single-shot avalanche event in a power MOSFET is due to the junction temperature exceeding the maximum temperature rating. In such a case, catastrophic damage occurs to the MOSFET. If the transient temperature resulting from an avalanche event, as shown in Figure 6, rises beyond a recommended rated value, the device risks being degraded. The recommended rated value is derated from the maximum temperature for optimum reliability. Blackburn (see Ref. 2) has discussed a general guideline in detail, on the appropriate method of quantifying the single-shot avalanche capability of a device. It takes the avalanche current and initial junction temperature into consideration. The maximum allowed avalanche current as a function of avalanche time defines the safe operation for a device single-shot UIS event. The maximum allowed avalanche current is set so that a safe maximum junction temperature, Tj(max) of 175 C, is never exceeded. Using Equation 7, Figure 7 is plotted. AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating DDM 7M & ,$/ $ 7M & Fig 7. W$/PV Single-shot avalanche ruggedness Safe Operating ARea (SOAR) curves of BUK764R0-55B limited to a Tj(max) of 175 C Figure 7 shows the SOAR curves of a device single-shot avalanche capability. The 25 C junction temperature curve shows the maximum allowable IDS(AL)S for a given tAL at an initial Tj of 25 C. This maximum IAL results to a maximum allowable junction temperature Tj(max) of 175 C, which means a Tj(max) of 150 C. The area under the SOAR curve is the Safe Operating ARea (SOAR). Similarly, the 150 C junction temperature curve is the maximum operating limit for an initial Tj of 150 C. The maximum value of IDS(AL)S induces a Tj(max) of 25 C, resulting in a Tj(max) of 175 C. Again the area under the curve is the SOAR. The maximum junction temperature resulting in catastrophic device avalanche failure is approximately 380 C, which is in excess of the rated Tj(max) of 175 C. However, operating beyond the rated Tj(max) may induce long-term detrimental effects to the power MOSFET and is not recommended. 4. Understanding power MOSFET repetitive avalanche events Repetitive avalanche refers to an operation involving repeated single-shot avalanche events, as discussed earlier. Until recently, most manufacturers have avoided the issues pertaining to the power MOSFET repetitive avalanche capability. It is primarily due to the complexity in such operations and the difficulties in identifying the underlying physical degradation process in the device. Due to the traumatic nature of the avalanche event, a repetitive avalanche operation can be hazardous for a MOSFET. It is hazardous even when the individual avalanche events are below the single-shot UIS rating. This type of operation involves additional parameters such as frequency, duty cycle, and thermal resistances (Rth(j-a) and Rth(j-mb)) of the system during the avalanche event. However, it is possible to derate the single-shot rating to define a repetitive avalanche SOAR. AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 4.1 Repetitive UIS operation The repetitive UIS test circuit is shown in Figure 1. The gate is fed with a train of voltage pulses at a frequency (f) and for a duty cycle as shown in Figure 8. The resulting breakdown voltage (VBR) and drain current (ID) passing through the load are the same as for a single-shot UIS. However, the peak ID is now denoted as repetitive drain-source avalanche current (IDS(AL)R), as shown in Figure 9. The repetitive drain-source avalanche power (PDS(AL)R) resulting from the repetitive UIS operation is shown in Figure 10. For finding the value of PDS(AL)R, it is necessary to first calculate EDS(AL)S for a single avalanche event using Equation 3. This resultant value of EDS(AL)S is substituted in the following expression, to calculate the value of PDS(AL)R: P DS AL R = E DS AL S f (8) 4.1.1 Repetitive UIS waveforms 9*6 9%5 9%5'66 ,'6$/5 9'' WLPH WLPH W$/ DDM Fig 8. Gate pulse, VGS Fig 9. DDM Drain-source voltage, VDS and repetitive drain-source avalanche current, IDS(AL)R 3 7M 3'6$/0 7MLQLW 7PE 7M 3'6$/5 7M$9 WLPH WLPH W$/ W$/ DDM Fig 10. Repetitive drain-source avalanche power, PDS(AL)R DDM Fig 11. Transient junction temperature components of MOSFET during repetitive avalanche 4.2 Temperature components The temperature rise from the repetitive avalanche mode in the power MOSFET is shown in Figure 11. The temperature (Tj(init)) comprises the mounting base temperature (Tmb) and the temperature rise resulting from any on-state temperature difference (Ton). T j init = T mb + T on (9) In addition, there is a steady-state average junction temperature variation (Tj) resulting from the average repetitive avalanche power loss. AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating T j = P DS AL R R th j-a (10) where Rth(j-a) is the thermal resistance from junction to ambient of the device in the application. The summation of Equation 9 and Equation 10 gives the average junction temperature, Tj(AV) of a power MOSFET in repetitive UIS operation. T j AV = T j init + T j (11) 5. Repetitive avalanche ruggedness rating Following extensive investigation, it is clear that there is more than one failure or wear-out mechanism involved in repetitive avalanche. Temperature is not the only limiting factor to a repetitive avalanche operation. However, by limiting temperature and the repetitive drain-source avalanche current (IDS(AL)R), an operating environment is defined such that the avalanche conditions do not activate device degradation. It allows the power MOSFET to operate under repetitive UIS conditions safely. Figure 12 shows the single-shot and repetitive avalanche SOAR curves of BUK764R0-55B, where ‘Rep. Ava’ represents the ‘repetitive avalanche SOAR curve’. DDM 7M & ,$/ $ 7M & 5HS$YD W$/PV Fig 12. Single-shot and repetitive avalanche SOAR curves of BUK764R0-55B limited to Tj(max) of 175 C and Tj(AV) of 170 C, respectively The two conditions which must be satisfied for safe operation of a power MOSFET under repetitive avalanche mode are: 1. IDS(AL)R should not exceed the repetitive avalanche SOAR curve 2. Tj(AV) should not exceed 170 C 6. Conclusion Power MOSFETs can sustain single-shot and repetitive avalanche events. Simple design rules and SOAR regions are provided. AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 7. Examples The following examples examine cases of avalanche operation acceptance: 7.1 Single-shot avalanche case • • • • • • Device: BUK764R0-55B; see Figure 12 L = 2 mH IDS(AL)S = 40 A Rth(j-a) = 5 K/W V(BR)DSS = 55 V VDD = 0 V 7.1.1 Calculation steps 1. Using the above information, tAL can be determined using Equation 2, which in this case is 1.11 ms. Transferring the IAL and tAL conditions onto Figure 12, the operating point is in between the Tj = 25 C and Tj = 150 C SOAR curves. It suggests that the operating condition may be feasible. 2. To check, calculate the Tj(max) using Equation 6, where Zth(556 s) in the data sheet is approximately 0.065 K/W. It gives a Tj(max) of 124.8 C. Based on the above calculations, the operating condition is acceptable if the device Tj < 50 C. 7.2 Repetitive avalanche case • • • • • • • • Device: BUK764R0-55B; see Figure 12 L = 0.5 mH IDS(AL)R = 6 A f = 3 kHz Rth(j-a) = 5 K/W To = 100 C V(BR)DSS = 55 V VDD = 0 V 7.2.1 Calculation steps 1. From the above information, tAL can be determined using Equation 2, which in this case is approximately 0.042 ms. Transferring the IAL and tAL conditions onto Figure 12, the operating point is under the boundary of the ‘Rep. Ava’ SOAR curve. It suggests that the operating condition is acceptable. Therefore, condition 1 is satisfied. 2. Calculate the non-repetitive drain-source avalanche energy (EDS(AL)S) using Equation 3 (EDS(AL)S = 9 mJ). 3. Calculate the repetitive drain-source avalanche power (PDS(AL)R) using Equation 8 (PDS(AL)R = 27 W). AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 4. Calculate the average Tj rise from repetitive avalanche (Tj) using Equation 10 (Tj = 135 C). 5. Determine the average junction maximum temperature in repetitive avalanche operation (Tj(AV)) using Equation 11 (Tj(AV) = 235 C). Therefore, condition 2 is not satisfied. Based on the above calculations, the operating conditions meet the first requirement but not the second requirement for safe repetitive avalanche operation. It is because the maximum Tj(AV) exceeded 170 C. To make the above operation viable, the design engineer has to satisfy the second condition by reducing Tj(AV). It can be achieved by improving the heat sinking of the device. Reducing Rth(j-a) from 5 K/W to 2.5 K/W gives a Tj(AV) of 167.5 C, satisfying condition 2 for safe repetitive avalanche operation. 8. Appendix A The following table describes the symbols used throughout this application note. Table 1. AN10273 Application note Description of symbols Symbol Description V(BR)DSS drain-source breakdown voltage EDS(AL)S non-repetitive drain-source avalanche energy ID drain current IDS(AL)S non-repetitive drain-source avalanche current IDS(AL)R repetitive drain-source avalanche current IAL avalanche current L inductance PDS(AL)M peak drain-source avalanche power PDS(AL)R repetitive drain-source avalanche power Rth(j-a) thermal resistance from junction to ambient Rth(j-mb) thermal resistance from junction to mounting base Tj(init) initial junction temperature[1] Ton on-state temperature difference Tj junction temperature Tj junction temperature variation Tj(max) maximum junction temperature variation Tj(max) maximum junction temperature Tj(AV) average junction temperature[2] Tmb mounting base temperature tAL avalanche time VBR breakdown voltage VDS drain-source voltage VGS gate-source voltage All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating Table 1. Description of symbols …continued Symbol Description Zth transient thermal impedance Z th t AL 2 VDD transient thermal impedance[3] supply voltage [1] Summation of Tmb and Ton. [2] For repetitive avalanche. [3] Measured at half the avalanche period. 9. Abbreviations Table 2. Abbreviations Acronym Description MOSFET Metal-Oxide Semiconductor Field-Effect Transistor SOAR Safe Operating ARea UIS Unclamped Inductive Switching 10. References AN10273 Application note [1] Turn-Off Failure of Power MOSFETs — D.L. Blackburn, Proc. 1985 IEEE Power Electronics Specialists Conference, pages 429 to 435, June 1985. [2] Power MOSFET failure revisited — D.L. Blackburn, Proc. 1988 IEEE Power Electronics Specialists Conference, pages 681 to 688, April 1988. [3] Boundary of power-MOSFET, unclamped inductive-switching (UIS), avalanche-current capability — Rodney R. Stoltenburg, Proc. 1989 Applied Power Electronics Conference, pages 359 to 364, March 1989. All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 11. Legal information 11.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 11.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. 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Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 11.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 12. Tables Table 1. Description of symbols . . . . . . . . . . . . . . . . . .10 Table 2. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 11 13. Figures Fig 1. Unclamped inductive load test circuit for MOSFET ruggedness evaluation. . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Gate-source voltage, VGS . . . . . . . . . . . . . . . . . . .5 Fig 3. Drain-source voltage, VDS . . . . . . . . . . . . . . . . . . .5 Fig 4. Drain current, ID . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 5. Peak drain-source avalanche power, PDS(AL)M . . .5 Fig 6. Transient junction temperature profile of MOSFET during an avalanche event. . . . . . . . . . . . . . . . . . .5 Fig 7. Single-shot avalanche ruggedness Safe Operating ARea (SOAR) curves of BUK764R0-55B limited to a Tj(max) of 175 °C . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Fig 8. Gate pulse, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Fig 9. Drain-source voltage, VDS and repetitive drain-source avalanche current, IDS(AL)R . . . . . . . .7 Fig 10. Repetitive drain-source avalanche power, PDS(AL)R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Fig 11. Transient junction temperature components of MOSFET during repetitive avalanche . . . . . . . . . .7 Fig 12. Single-shot and repetitive avalanche SOAR curves of BUK764R0-55B limited to Tj(max) of 175 °C and Tj(AV) of 170 °C, respectively . . . . . . . . . . . . . . . . .8 AN10273 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 13 of 14 AN10273 NXP Semiconductors Power MOSFET avalanche ruggedness rating 14. Contents 1 2 3 3.1 3.1.1 3.2 4 4.1 4.1.1 4.2 5 6 7 7.1 7.1.1 7.2 7.2.1 8 9 10 11 11.1 11.2 11.3 12 13 14 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Single-shot and repetitive avalanche definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Understanding power MOSFET single-shot avalanche events . . . . . . . . . . . . . . . . . . . . . . . . 3 Single-shot UIS operation. . . . . . . . . . . . . . . . . 3 Single-shot UIS waveforms . . . . . . . . . . . . . . . 5 Single-shot avalanche ruggedness rating . . . . 5 Understanding power MOSFET repetitive avalanche events . . . . . . . . . . . . . . . . . . . . . . . . 6 Repetitive UIS operation. . . . . . . . . . . . . . . . . . 7 Repetitive UIS waveforms . . . . . . . . . . . . . . . . 7 Temperature components . . . . . . . . . . . . . . . . . 7 Repetitive avalanche ruggedness rating . . . . . 8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Single-shot avalanche case . . . . . . . . . . . . . . . 9 Calculation steps . . . . . . . . . . . . . . . . . . . . . . . 9 Repetitive avalanche case . . . . . . . . . . . . . . . . 9 Calculation steps . . . . . . . . . . . . . . . . . . . . . . . 9 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 December 2015 Document identifier: AN10273