A3966 Datasheet

A3966
Dual Full-Bridge PWM Motor Driver
Features and Benefits
Description
▪ ±650 mA continuous output current
▪ 30 V output voltage rating
▪ Internal fixed-frequency PWM current control
▪ Satlington® sink drivers
▪ User-selectable blanking window
▪ Internal ground-clamp and flyback diodes
▪ Internal thermal-shutdown circuitry
▪ Crossover-current protection and UVLO protection
The A3966 is designed to drive both windings of a two-phase
bipolar stepper motor. The device includes two full-bridges
capable of continuous output currents of ±650 mA and operating
voltages to 30 V. Motor winding current can be controlled by
the internal fixed-frequency, pulse-width modulated (PWM),
current-control circuitry. The peak load current limit is set
by user selection of a reference voltage and current-sensing
resistors.
The fixed-frequency pulse duration is set by a user-selected
external RC timing network. The capacitor in the RC timing
network also determines a user-selectable blanking window that
prevents false triggering of the PWM current-control circuitry
during switching transitions.
To reduce on-chip power dissipation, the full-bridge power
outputs have been optimized for low saturation voltages. The
sink drivers feature the Allegro™ patented Satlington® output
structure. The Satlington outputs combine the low voltage drop
of a saturated transistor and the high peak current capability
of a Darlington.
Package: 16 pin SOICW (suffix LB)
For each bridge, a PHASE input controls load-current polarity
by selecting the appropriate source and sink driver pair. For
Continued on the next page…
Not to scale
Typical Application
16
1
PHASE 1
2
ENABLE 1
3
V BB
LOGIC
4
0.5 Ω
LOGIC
15
PHASE 2
14
ENABLE 2
13
5
12
0.5 Ω
+5 V
V
REF
+
47 μF
BB
Dwg. EP-047-4A
29319.25K
VCC
10
RC
9
+5 V
680 pF
7
8
10 kΩ
11
V
56 kΩ
39 kΩ
6
+24 V
A3966
Dual Full-Bridge PWM Motor Driver
Description (continued)
each bridge, an ENABLE input, when held high, disables the output
drivers. Special power-up sequencing is not required. Internal circuit
protection includes thermal shutdown with hysteresis, ground-clamp
and flyback diodes, and crossover-current protection.
The A3966 is supplied in a 16-lead plastic wide SOIC with two pins
internally fused to the die pad for enhanced thermal dissipation. These
pins are at ground potential and need no electrical isolation. The
device is lead (Pb) free, with 100% matte tin leadframe plating.
Selection Guide
Part Number
A3966SLBTR–T
Packing
Ambient Temperature Range
(°C)
1000 pieces / reel
–20 to 85
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
Load Supply Voltage
VBB
30
V
Logic Supply Voltage
VCC
7.0
V
Input Voltage
VIN
–0.3 to VCC + 0.3
V
Sense Voltage
VS
1.0
V
±750
mA
Output Current*
IOUT
±650
mA
1.87
W
Peak
Continuous
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or TJ(max)
PD
TA = 25°C; per SEMI G42-88 Specification, Thermal Test
Board Standardization for Measuring Junction-to-Ambient
Thermal Resistance of Semiconductor Packages.
Operating Ambient Temperature
TA
Range S
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Package Power Dissipation
Storage Temperature
Pin-out Diagram
OUT1A
1
PHASE 1
2
ENABLE 1
3
GROUND
4
SENSE1
5
OUT 1B
6
V
LOGIC
V
LOAD
SUPPLY
7
REFERENCE
8
BB
BB
LOGIC
V
CC
V
REF
RC
16
OUT 2A
15
PHASE 2
14
ENABLE 2
13
GROUND
12
SENSE 2
11
OUT 2B
10
LOGIC
SUPPLY
9
RC
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3966
Dual Full-Bridge PWM Motor Driver
LOAD
SUPPLY
+
OUT 2B
OUT 2A
OUT 1B
LOGIC
SUPPLY
OUT 1A
FUNCTIONAL BLOCK DIAGRAM
V CC
PHASE 2
PHASE 1
CONTROL LOGIC1
UVLO
& TSD
CONTROL LOGIC2
V BB
PWM LATCH 1
BLANKING
GATE 1
R
CURRENT-SENSE
COMPARATOR 1
SENSE 1
CURRENT-SENSE
COMPARATOR 2
SENSE 2
+
–
BLANKING
GATE 2
+
–
PWM LATCH 2
R
Q
SOURCE
ENABLE 2
ENABLE 2
SOURCE
ENABLE 1
ENABLE 1
Q
S
S
÷4
OSC
R1S
RC
RT
UVLO
& TSD
GROUND
R 2S
CT
REFERENCE
Dwg. FP-036-6
TRUTH TABLE
ENABLE
H
L
L
OUTA
Off
H
L
OUTB
Off
L
H
X = Irrelevant
Typical output saturation voltages showing
Satlington sink-driver operation.
2.5
OUTPUT SATURATION VOLTAGE IN VOLTS
PHASE
X
H
L
TA = +25°C
2.0
SOURCE DRIVER
1.5
1.0
0.5
SINK DRIVER
0
200
300
400
500
600
7 00
OUTPUT CURRENT IN MILLIAMPERES
Dwg. GP-064-1A
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3966
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25oC, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V,
VS = 0 V, 56 kŸ & 680 pF RC to Ground (unless noted otherwise)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
VCC
—
30
V
Output Drivers
Load Supply Voltage Range
V BB
Operating, IOUT = p650 mA, L = 3 mH
Output Leakage Current
ICEX
VOUT = 30 V
—
<1.0
50
MA
VOUT = 0 V
—
<-1.0
-50
MA
Source Driver, IOUT = -400 mA
—
1.7
2.0
V
Source Driver, IOUT = -650 mA
—
1.8
2.1
V
Sink Driver, IOUT = +400 mA, VS = 0.5 V
—
0.3
0.5
V
Sink Driver, IOUT = +650 mA, VS = 0.5 V
—
0.7
1.3
V
IF = 4 0 0 m A
—
1.1
1.4
V
IF = 6 5 0 m A
—
1.4
1.6
V
IBB(ON)
VENABLE1 = VENABLE2 = 0.8 V
—
3.0
5.0
mA
IBB(OFF)
VENABLE1 = VENABLE2 = 2.4 V
—
<1.0
200
MA
4.75
—
5.50
V
Output Saturation Voltage
Clamp Diode Forward Voltage
Motor Supply Current
(No Load)
VCE(SAT)
VF
Control Logic
Logic Supply Voltage Range
VCC
Operating
Logic Input Voltage
VIN(1)
2.4
—
—
V
VIN(0)
—
—
0.8
V
IIN(1)
VIN = 2.4 V
—
<1.0
20
MA
IIN(0)
VIN = 0.8 V
—
<-20
-200
MA
Reference Input Volt. Range
VREF
Operating
0.1
–
2.0
V
Reference Input Current
IREF
-2.5
0
1.0
MA
Reference Divider Ratio
VREF/VTRIP
3.8
4.0
4.2
—
Logic Input Current
Current-Sense Comparator
Input Offset Voltage
VIO
VREF = 0 V
-6.0
0
6.0
mV
Current-Sense Comparator
Input Voltage Range
VS
Operating
-0.3
—
1.0
V
Sense-Current Offset
ISO
IS – IOUT, 50 mA b IOUT b 650 mA
12
18
24
mA
NOTES:1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3966
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25oC, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V,
VS = 0 V, 56 kŸ & 680 pF RC to Ground (unless noted otherwise) (cont.)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
CT = 680 pF, RT = 56 k7
22.9
25.4
27.9
kHz
Comparator Trip to Source OFF
—
1.0
1.4
Ms
Cycle Reset to Source ON
—
0.8
1.2
Ms
Control Logic (continued)
PWM RC Frequency
PWM Propagation Delay Time
fosc
t PWM
Cross-Over Dead Time
tcodt
1 kŸ Load to 25 V
0.2
1.8
3.0
Ms
Propagation Delay Times
t pd
IOUT = p650 mA, 50% to 90%:
ENABLE ON to Source ON
ENABLE OFF to Source OFF
ENABLE ON to Sink ON
ENABLE OFF to Sink OFF
PHASE Change to Sink ON
PHASE Change to Sink OFF
PHASE Change to Source ON
PHASE Change to Source OFF
—
—
—
—
—
—
—
—
100
500
200
200
2200
200
2200
200
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
TJ
—
165
—
oC
$TJ
—
15
—
oC
—
4.1
4.6
V
0.1
0.6
—
V
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
VT(UVLO)+
Increasing VCC
VT(UVLO)hys
ICC(ON)
VENABLE 1 = VENABLE 2 = 0.8 V
—
—
50
mA
ICC(OFF)
VENABLE 1 = VENABLE 2 = 2.4 V
—
—
9.0
mA
NOTES:1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3966
Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3966 dual fullbridges are designed to drive both windings of a bipolar
stepper motor. Load current can be controlled in each motor
winding by an internal fixed-frequency PWM control circuit. The current-control circuitry works as follows: when
the outputs of the full-bridge are turned on, current increases in the motor winding. The load current is sensed by the
current-control comparator via an external sense resistor
(RS). Load current continues to increase until it reaches
the predetermined value, set by the selection of external
current-sensing resistors and reference input voltage (VREF)
according to the equation:
ITRIP = IOUT + ISO = VREF/(4 RS)
where ISO is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the source-enable latch, turning off the source driver of that full-bridge.
The source turn-off of one full-bridge is independent of
the other full-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp diode.
The current decreases until the internal clock oscillator sets
the source-enable latches of both Full-bridges, turning on
the source drivers of both bridges. Load current increases
again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
the external timing components RTCT. The frequency can
be approximately calculated as:
fosc = 1/(RT CT + tblank)
where tblank is defined below.
The range of recommended values for RT and CT are
20 to 100 k and 470 to 1000 pF respectively. Nominal
values of 56 k and 680 pF result in a clock frequency of
25 kHz.
Current-Sense Comparator Blanking. When the
source driver is turned on, a current spike occurs due to the
reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load.
To prevent this current spike from erroneously resetting the
source enable latch, the current-control comparator output
is blanked for a short period of time when the source driver
is turned on. The blanking time is set by the timing component CT according to the equation:
tblank = 1900 CT (μs).
A nominal CT value of 680 pF will give a blanking time
of 1.3 μs.
The current-control comparator is also blanked when
the Full-bridge outputs are switched by the PHASE or
ENABLE inputs. This internally generated blank time is
approximately 1 μs.
V
BB
V PHASE
See Enlargement A
BRIDGE
ON
+
I
OUT
BRIDGE ON
ALL
OFF
0
SOURCE OFF
–
ALL OFF
BRIDGE
ON
I TRIP
Enlargement A
SOURCE
OFF
td
t
INTERNAL
OSCILLATOR
R TC T
RS
blank
Dwg. WM-003-2
Dwg. EP-006-16
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3966
Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
Load Current Regulation. Due to internal logic and
switching delays, td , the actual load current peak will be
slightly higher than the ITRIP value. These delays, plus the
blanking time, limit the minimum value the current control
circuitry can regulate. To produce zero current in a winding, the ENABLE terminal should be held high, turning off
all output drivers for that full-bridge.
Logic Inputs. A logic high on the PHASE input results
in current flowing from OUTA to OUTB of that full-bridge.
A logic low on the PHASE input results in current flowing
from OUTB to OUTA. An internally generated dead time,
tcodt , of approximately 1 μs prevents crossover-current
spikes that can occur when switching the PHASE input.
A logic high on the ENABLE input turns off all four
output drivers of that full-bridge. This results in a fast current decay through the internal ground clamp and flyback
diodes. A logic low on the ENABLE input turns on the
selected source and sink driver of that full-bridge.
The ENABLE inputs can be pulse-width modulated
for applications that require a fast current-decay PWM. If
external current-sensing circuitry is used, the internal current-control logic can be disabled by connecting the RTCT
terminal to ground.
The REFERENCE input voltage is typically set with a
resistor divider from VCC. This reference voltage is internally divided down by 4 to set up the current-comparator
trip-voltage threshold. The reference input voltage range is
0 to 2 V.
Output Drivers. To minimize on-chip power dissipation, the sink drivers incorporate a Satlington structure.
The Satlington output combines the low VCE(sat) features
of a saturated transistor and the high peak-current capability of a Darlington (connected) transistor. A graph showing
typical output saturation voltages as a function of output
current is on page 5.
Miscellaneous Information. Thermal protection
circuitry turns off all output drivers should the junction
temperature reach 165 °C typical. This is intended only to
protect the device from failures due to excessive junction
temperatures and should not imply that output short circuits
are permitted. Normal operation is resumed when the junction temperature has decreased about 15°C.
The A3966 current control employs a fixed-frequency,
variable duty cycle PWM technique. As a result, the current-control regulation may become unstable if the duty
cycle exceeds 50%.
To minimize current-sensing inaccuracies caused by
ground trace IR drops, each current-sensing resistor should
have a separate return to the ground terminal of the device.
For low-value sense resistors, the I x R drops in the printedwiring board can be significant and should be taken into account. The use of sockets should be avoided as their contact
resistance can cause variations in the effective value of RS.
The LOAD SUPPLY terminal, VBB, should be decoupled with an electrolytic capacitor (47 μF recommended)
placed as close to the device as physically practical. To
minimize the effect of system ground I x R drops on the
logic and reference input signals, the system ground should
have a low-resistance return to the load supply voltage.
The frequency of the clock oscillator will determine the
amount of ripple current. A lower frequency will result in
higher current ripple, but reduced heating in the motor and
driver IC due to a corresponding decrease in hysteretic core
losses and switching losses respectively. A higher frequency will reduce ripple current, but will increase switching
losses and EMI.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A3966
Dual Full-Bridge PWM Motor Driver
Package LB, 16-pin SOICW
10.30±0.20
4° ±4
16
1.27
0.65
+0.07
0.27 –0.06
10.30±0.33
7.50±0.10
9.50
A
+0.44
0.84 –0.43
2.25
1
2
0.25
16X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
B
PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20 ±0.10
For Reference Only
Pins 4 and 13 fused internally
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©1998-2013, Allegro MicroSystems, LLC
Satlington® is a registered trademark of Allegro MicroSystems, LLC (Allegro), and Satlington devices are manufactured under U. S. Patent
No. 5,684,427.
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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