A3977 Microstepping DMOS Driver with Translator FEATURES AND BENEFITS • • • • • • • • • ±2.5 A, 35 V output rating Low RDS(on) outputs, 0.28 Ω source, 0.22 Ω sink typical Automatic current decay mode detection/selection 3.0 to 5.5 V logic supply voltage range Mixed, fast, and slow current decay modes Home output Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Package: 28-pin TSSOP (suffix LP) with Exposed Thermal Pad DESCRIPTION The A3977 is a complete microstepping motor driver, with built-in translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. Simply inputting one pulse on the STEP input drives the motor one step (two logic inputs determine if it is a full-, half-, quarter-, or eighth-step). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex microprocessor is unavailable or over-burdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. Not to scale The A3977 is supplied in a thin (<1.2 mm), 28-pin TSSOP with an exposed thermal pad (suffix LP). The A3977 is a lead (Pb) free, with 100% matte tin leadframe plating. Pin-out Diagram A3977-DS, Rev. 12 A3977 Microstepping DMOS Driver with Translator SPECIFICATIONS Selection Guide Part Number A3977SLPTR-T Packing Package 4000 per reel 28-pin TSSOP Ambient Temperature, TA (°C) –20 to 85 Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage VBB Logic Supply Voltage VDD Logic Input Voltage Range Reference Voltage Sense Voltage (DC) Output Current VIN Notes Units 35 V 7.0 V Pulsed, tw > 30 ns –0.3 to VDD+ 0.3 V Pulsed, tw < 30 ns –1.0 to VDD+ 1 V VDD V 0.5 V ±2.5 A Range K –40 to 125 ºC Range S –20 to 85 ºC VREF VSENSE IOUT Rating Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Value Units 28 ºC/W Storage Temperature Thermal Characteristics Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Package LP, on 4-layer PCB based on JEDEC standard *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3977 Microstepping DMOS Driver with Translator VREG LOGIC SUPPLY 2V UVLO AND FAULT VDD REF. SUPPLY DAC SENSE1 CP1 CHARGE PUMP REGULATOR BANDGAP REF CP2 LOAD SUPPLY VCP VBB1 VCP DMOS H BRIDGE + OUT 1A RC1 PWM LATCH BLANKING OUT1B MIXED DECAY PWM TIMER 4 STEP HOME SLEEP VPFD GATE DRIVE MS 1 MS 2 CONTROL LOGIC RESET SENSE1 TRANSLATOR DIR DMOS H BRIDGE OUT 2A SR OUT2B ENABLE PFD VBB2 PWM TIMER PWM LATCH BLANKING MIXED DECAY 4 RC 2 + - DAC SENSE2 Dwg. FP-050-2 Functional Block Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3977 Microstepping DMOS Driver with Translator Pin-out Diagram and Terminal List Table LP Package, 28-Pin TSSOP Pin-out Digram Terminal List Table Terminal Name Terminal Number GND – Analog and Power Ground SENSE1 1 Sense Resistor for Bridge 1 HOME 2 Logic Output DIR 3 Logic Input OUT1A 4 DMOS H Bridge 1 Output A NC – No (internal) Connection PFD 5 Mixed Decay Setting RC1 6 Analog Input for Fixed Offtime – Bridge 1 GND – Analog and Power Ground AGND 7* REF 8 RC2 Terminal Description Terminal Name Terminal Number LOAD SUPPLY2 15 VBB2, the Load Supply for Bridge 2 Terminal Description SR 16 Logic Input RESET 17 Logic Input OUT2B 18 DMOS H Bridge 2 Output B NC – No (internal) Connection STEP 19 Logic Input VREG 20 Regulator Decoupling PGND 21* Power Ground GND – Analog and Power Ground Analog Ground VCP 22 Reservoir Capacitor Gm Reference Input CP1 23 Charge Pump Capacitor 9 Analog Input for Fixed Offtime – Bridge 2 CP2 24 Charge Pump Capacitor LOGIC SUPPLYNC 10 VDD, the Logic Supply Voltage NC – No (internal) Connection OUT2A 11 DMOS H Bridge 2 Output A MS2 12 Logic Input MS1 13 Logic Input SENSE2 14 Sense Resistor for Bridge 2 GND – Analog and Power Ground NC – No (internal) Connection OUT1B 25 DMOS H Bridge 1 Output B ENABLE 26 Logic Input SLEEP 27 Logic Input LOAD SUPPLY1 28 VBB1, the Load Supply for Bridge 1 *AGND and PGND on the TSSOP package must be connected together externally. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3977 Microstepping DMOS Driver with Translator Maximum Power Dissipation, PD(max) 5.0 4.5 Power Dissipation, PD (W) 4.0 H (R igh- K = PCB 28 2La ºC ye /W rP ) C (R B w ith θJ A = 3 32 .8 in 2 ºC co /W pp er ) p 3.5 θJ 3.0 2.5 2.0 A er 1.5 sid e 1.0 0.5 0.0 20 40 60 80 100 120 Temperature (°C) 140 160 Table 1: Microstep Resolution Truth Table MS1 MS2 Resolution Full Step (2 Phase) L L H L Half Step L H Quarter Step H H Eighth Step Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3977 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Units 8.0 – 35 V Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance VBB IDSS RDS(on) Body Diode Forward Voltage VF Motor Supply Current IBB Operating During sleep mode 0 – 35 V VOUT = VBB – <1.0 20 µA VOUT = 0 V – <1.0 -20 µA Source driver, IOUT = -2.5 A – 0.28 0.335 Ω Ω Sink driver, IOUT = 2.5 A – 0.22 0.265 Source diode, IF = -2.5 A – – 1.4 V Sink diode, IF = 2.5 A – – 1.4 V fPWM < 50 kHz – – 8.0 mA Operating, outputs disabled – – 6.0 mA Sleep mode – – 20 µA 3.0 5.0 5.5 V 0.7VDD – – V Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current Maximum STEP Frequency HOME Output Voltage Blank Time Fixed Off Time Mixed Decay Trip Point VDD VIN(0) IIN(1) VIN = 0.7VDD IIN(0) VIN = 0.3VDD fSTEP – – 0.3VDD V -20 <1.0 20 µA -20 <1.0 20 µA 500* – – kHz VOH IOH = -200 µA 0.7VDD – – V VOL IOL = 200 µA – – 0.3VDD V 950 1200 ns tBLANK Rt = 56 kΩ, Ct = 680 pF 700 toff Rt = 56 kΩ, Ct = 680 pF 30 38 46 µs – 0.6VDD – V PFDH PFDL Ref. Input Voltage Range VREF Reference Input Current IREF Gain (Gm) Error (note 3) Operating VIN(1) EG – 0.21VDD – V Operating 0 – VDD V – 0 ±3.0 µA VREF = 2 V, Phase Current = 38.27% – – ±10 % VREF = 2 V, Phase Current = 70.71% VREF = 2 V, Phase Current = 100.00% – – ±5.0 % – – ±5.0 % Crossover Dead Time tDT 100 475 800 ns Thermal Shutdown Temp. TJ – 165 – °C ∆TJ – 15 – °C 2.45 2.7 2.95 V 0.05 0.10 – V Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current VUVLO ∆VUVLO IDD SR enabled Increasing VDD fPWM < 50 kHz – – 12 mA Outputs off – – 10 mA Sleep mode – – 20 µA * Operation at a step frequency greater than the specified minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = ([VREF/8] – VSENSE)/(VREF/8) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3977 Microstepping DMOS Driver with Translator FUNCTIONAL DESCRIPTION Device Operation Step Input (STEP) The A3977 is a complete microstepping motor driver with built in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter- and eighth-step modes. The current in each of the two output full-bridges, all N-channel DMOS, is regulated with fixed off-time pulse-width modulated (PWM) control circuitry. The full-bridge current at each step is set by the value of an external current sense resistor (RS), a reference voltage (VREF), and the DACs output voltage controlled by the output of the translator. A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see table 1). At power up, or reset, the translator sets the DACs and phase current polarity to initial home state (see figures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in table 1. If the new DAC output level is lower than the previous level the decay mode for that full-bridge will be set by the PFD input (fast, slow, or mixed decay). If the new DAC level is higher or equal to the previous level then the decay mode for that full-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Reset Input (RESET) The RESET input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the DMOS outputs. The HOME output goes low and all STEP inputs are ignored until the RESET input goes high. Home Output (HOME) The HOME output is a logic output indicator of the initial state of the translator. At power up the translator is reset to the home state (see figures for home state conditions). Microstep Select (MS1 and MS2) Input terminals MS1 and MS2 select the microstepping format per table 1. Changes to these inputs do not take effect until the STEP command (see figure). Direction Input (DIR) The state of the DIRECTION input will determine the direction of rotation of the motor. Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM currentcontrol circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RS. When the voltage across the current-sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF/8RS The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax/100) x ITRIPmax It is critical to ensure that the maximum rating (0.5 V) on the SENSE terminal is not exceeded. For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 0.707 x VREF/8. In all other modes VREF should not exceed 4 V. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3977 Microstepping DMOS Driver with Translator Fixed Off-Time Shutdown The internal PWM current-control circuitry uses a one shot to control the time the drivers remain off. The one shot off-time, toff, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off-time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: In the event of a fault (excessive junction temperature, or low voltage on VCP) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the HOME state. toff = RTCT RC Blanking In addition to the fixed off-time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/or switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by: tBLANK = 1400CT Charge Pump. (CP1 and CP2) The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor is required between VCP and VBB to act as a reservoir to operate the high-side DMOS devices. VREG This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE) Sleep Mode (SLEEP) An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. A logic high allows normal operation and startup of the device in the home position. When coming out of sleep mode, wait 1 ms before issuing a STEP command to allow the charge pump (gate drive) to stabilize. Percent Fast Decay Input (PFD) When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6 VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21 VDD then fast-decay mode is selected. Mixed decay is between these two levels. This terminal should be decoupled with a 0.1 µF capacitor. Mixed Decay Operation If the voltage on the PFD input is between 0.6VDD and 0.21VDD, the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: tFD = RTCTIn (0.6VDD/VPFD) After this fast decay portion, tFD, the device will switch to slowdecay mode for the remainder of the fixed off-time period. This active-low input enables all of the DMOS outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS1, MS2) are all active independent of the ENABLE input state. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3977 Microstepping DMOS Driver with Translator Synchronous Rectification Active Mode When a PWM off-cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low RDS(on) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. The synchronous rectification can be set in either active mode or disabled mode. Disabled Mode When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3977 package to the external diodes. A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) B. Minimum Command Active Time After Step Pulse (Data Hold Time) C. Minimum STEP Pulse Width D. Minimum STEP Low Time E. Maximum Wake-Up Time 200 ns 200 ns 1.0 µs 1.0 µs 1.0 ms Figure 1: Timing Requirements (TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3977 Microstepping DMOS Driver with Translator APPLICATIONS INFORMATION Layout. Current Sensing The printed wiring board should use a heavy ground plane. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (RS) should have an independent ground return to the star ground of the device. This path should be as short as possible. For lowvalue sense resistors the IR drops in the printed wiring board sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 µF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding A star ground system located close to the driver is recommended. The 44-lead PLCC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35). Allegro MicroSystems recommends a value of RS given by RS = 0.5/ITRIPmax Thermal Protection Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. On the 28-lead TSSOP package, the analog ground (lead 7) and the power ground (lead 21) must be connected together externally. The copper ground plane located under the exposed thermal pad is typically used as the star ground. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A3977 Microstepping DMOS Driver with Translator Table 2: Step Sequencing (DIR = H) Full Step # Phase 2 Current [%Itripmax] Step Angle (º) Half Step # Quarter Step # Eighth Step # Phase 1 Current [%Itripmax] 1 1 1 100.00 0.00 0 2 98.08 19.51 11.25 3 92.39 38.27 22.50 4 83.15 55.56 33.75 5* 70.71* 70.71* 45* 6 55.56 83.15 56.25 7 38.27 92.39 67 8 19.51 98.08 78.75 9 0.00 100.00 90 2 1* 2* 3* 4 3 2 4 5 10 -19.51 98.08 101.25 6 11 -38.27 92.39 112.50 12 -55.56 83.15 123.75 7 13 -70.71 70.71 135 14 -83.15 55.56 146.25 15 -92.39 38.27 157.50 16 -98.08 19.51 168.75 17 -100.00 0.00 180 18 -98.08 -19.51 191.25 8 5 9 10 3 6 11 12 7 13 14 4 8 19 -92.39 -38.27 202.50 20 -83.15 -55.56 213.75 21 -70.71 -70.71 225 22 -55.56 -83.15 236.25 23 -38.27 -92.39 247.50 24 -19.51 -98.08 258.75 25 0.00 -100.00 270 26 19.51 -98.08 281.25 27 38.27 -92.39 292.50 28 55.56 -83.15 303.75 15 29 70.71 -70.71 315 30 83.15 -55.56 326.25 16 31 92.39 -38.27 337.50 32 98.08 -19.51 348.75 *Home state; HOME output low. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A3977 Microstepping DMOS Driver with Translator Figure 2: Full-Step Operation MS1 = MS2 = L, DIR = H The vector addition of the output currents at any step is 100%. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A3977 Microstepping DMOS Driver with Translator Figure 3: Half-Step Operation MS1 = H, MS2 = L, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A3977 Microstepping DMOS Driver with Translator Figure 4: Quarter-Step Operation MS1 = L, MS2 = H, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A3977 Microstepping DMOS Driver with Translator Figure 5: 8 Microstep/Step Operation MS1 = MS2 = H, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A3977 Microstepping DMOS Driver with Translator CUSTOMER PACKAGE DRAWINGS For Reference Only – Not for Tooling Use (Reference MO-153 AET) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 9.70 ±0.10 5.08 NOM 8º 0º 28 0.20 0.09 B 3 NOM 4.40±0.10 6.40±0.20 A 0.60 ±0.15 1.00 REF 1 2 Branded Face 0.25 BSC C 28X 1.20 MAX 0.10 C 0.30 0.19 SEATING PLANE SEATING PLANE GAUGE PLANE 0.65 BSC 0.15 0.00 0.65 0.45 28 1.65 A Terminal #1 mark area B Exposed thermal pad (bottom surface) 3.00 6.10 C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 1 2 5.00 C PCB Layout Reference View Figure 6: LP Package, 28-pin TSSOP Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A3977 Microstepping DMOS Driver with Translator Revision History Revision No. Revision Date 11 April 23, 2013 12 October 30, 2014 Description of Revision Update product selection and applications component recommendations Removed ED package, Revised Table 2 title, reformatted document Copyright ©2002-2014, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17