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TPH3207WS
Preliminary
PRODUCT SUMMARY (TYPICAL)
VDS (V)
650
RDS(on) (m)
35
Qrr (nC)
175
GaN Power
Low-loss Switch
Features






S
Low Qrr
Free-wheeling diode not required
Quiet Tab™ for reduced EMI at high dv/dt
GSD pin layout improves high speed design
RoHS compliant
High frequency operation
S
G
Applications




D
Compact DC-DC converters
AC motor drives
Battery chargers
Switch mode power supplies
TO-247 3L Package
Absolute Maximum Ratings (TC=25 °C unless otherwise stated)
Symbol
Parameter
Limit Value
Unit
ID25°C
Continuous Drain Current @TC=25 °C
47
A
ID100°C
Continuous Drain Current @TC=100 °C
34
A
Pulsed Drain Current (pulse width:10 s)
220
A
VDSS
Drain to Source Voltage
650
V
VTDS
Transient Drain to Source Voltage a
800
V
VGSS
Gate to Source Voltage
±18
V
PD25°C
Maximum Power Dissipation
150
W
Case
-55 to 150
°C
Junction
-55 to 175
°C
-55 to 150
°C
260
°C
Typical
Unit
IDM
TC
TJ
TS
TCsold
Operating Temperature
Storage Temperature
Soldering peak Temperature b
Thermal Resistance
Symbol
Parameter
RΘJC
Junction-to-Case
0.7
°C /W
RΘJA
Junction-to-Ambient
40
°C /W
Notes
a: In off state, spike duty cycle D<0.1, duration <1us
b: For 10 sec, 1.6mm from the case
Preliminary Data
Jan. 18, 2016 YW
TPH3207WS
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TPH3207WS
Electrical Characteristics
Symbol
(TC=25 °C unless otherwise stated)
Parameter
Min
Typical
Max
Unit
Test Conditions
650
-
-
V
VGS=0 V
1.6
2.1
2.6
V
VDS=VGS, ID=0.7mA
-
35
41
mΩ
VGS=8V, ID =32A, TJ = 25 °C
-
84
-
mΩ
VGS=8V, ID =32A,TJ = 175 °C
-
5
50
µA
VDS=650V, VGS=0V, TJ = 25 °C
-
10
-
µA
VDS=650V, VGS=0V, TJ = 150 °C
-
-
400
Static
VDSS-MAX
VGS(th)
RDS(on)
RDS(on)
IDSS
IDSS
IGSS
Maximum Drain-Source Voltage
Gate Threshold Voltage
Drain-Source On-Resistance
(TJ = 25 °C)
Drain-Source On-Resistance
(TJ = 175 °C)
Drain-to-Source
Leakage Current, TJ = 25 °C
Drain-to-Source
Leakage Current, TJ = 150 °C
Gate-to-Source Forward
Leakage Current
Gate-to-Source Reverse
Leakage Current
VGS= 18 V
nA
-
-
-400
VGS= -18 V
Dynamic
CISS
Input Capacitance
-
2150
-
COSS
Output Capacitance
-
TBD
-
CRSS
Reverse Transfer Capacitance
-
TBD
-
CO(er)
Output Capacitance,
energy related a
-
280
-
CO(tr)
Output Capacitance,
time related b
-
430
-
Qg
Total Gate Charge
-
28
42
Qgs
Gate-Source Charge
-
TBD
-
Qgd
Gate-Drain Charge
-
TBD
-
td(on)
tr
Td(off)
tf
Turn-On Delay
Rise Time
Turn-Off Delay
Fall Time
-
TBD
TBD
TBD
TBD
VGS=0 V, VDS=400 V, f =1 MHz
pF
VGS=0 V, VDS=0 V to 400 V
nC
VDS =400 V VGS= 0-8 V, ID = 32 A
-
ns
VDS =400 V , VGS= 0-10 V, ID = 32 A,
RG = 2Ω
Reverse operation
IS
Reverse Current
-
-
32
A
VGS=0 V, TJ=100 oC
VSD
Reverse Voltage
-
TBD
TBD
V
VGS=0 V, IS=32 A, TJ=25 oC
VSD
Reverse Voltage
-
TBD
TBD
V
VGS=0 V, IS=16 A, TJ=25 oC
trr
Reverse Recovery Time
-
TBD
-
ns
Qrr
Reverse Recovery Charge
-
175
-
nC
IS=32A, VDD=400 V, di/dt =1000 A/s,
TJ=25 oC
Notes
a: Equivalent capacitance to give same stored energy from 0 to 400V
b: Equivalent capacitance to give same charging time from 0 to 400V
Preliminary Data
Jan. 18, 2016 YW
TPH3207WS
www.transphormusa.com
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TPH3207WS
Test Circuits and Waveforms
VDS
VGS
90%
10%
td(on)
tr
td(off)
ton
D.U.T.
3M
toff
Fig. 2. Switching Time Waveform
Fig. 1. Switching Time Test Circuit
750V
tf
Tpulse
+
VDS
Tpulse ≥ 1 uS
750V
750V
-
900V MOSFET
0V
≥ 1 uS
Duty Ratio = 0.1
10Tpulse
Fig. 4. Spike Voltage Waveform
Fig. 3. Spike Voltage Test Circuit
i, V
ID
D.U.T.
0V
diF/dt
A
trr
IF
tF
tS
t
10% IRRM
IRRM
dirr/dt
VRRM
trr = tS + tF
Qrr = QS +QF
Fig. 5. Test Circuit for Diode Characteristics
Jan. 18, 2016 YW
QF
90% IRRM
VDS
Preliminary Data
QS
Fig. 6. Diode Recovery Waveform
TPH3207WS
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TPH3207WS
Preliminary Data
Jan. 18, 2016 YW
TPH3207WS
www.transphormusa.com
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TPH3207WS
Important Notice
Transphorm Gallium Nitride (GaN) Switches provide significant advantages over silicon (Si)
Superjunction MOSFETs with lower gate charge, faster switching speeds and smaller reverse recovery charge. GaN Switches exhibit in-circuit switching speeds in excess of
150 V/ns and can be even pushed up to 500V/ns, compared to current silicon technology
usually switching at rates less than 50V/ns.
The fast switching of GaN devices reduces current-voltage cross-over losses and enables
high frequency operation while simultaneously achieving high efficiency. However, taking full
advantage of the fast switching characteristics of GaN Switches requires adherence to specific PCB layout guidelines and probing techniques .
Transphorm suggests visiting application note “Printed Circuit Board Layout and Probing for
GaN Power Switches” before evaluating Transphorm GaN switches. Below are some practical rules that should be followed during the evaluation.
When Evaluating Transphorm GaN Switches
DO
DO NOT
Minimize circuit inductance by keeping
traces short, both in the drive and power
loop
Minimize lead length of TO-220 and TO247 package when mounting to the PCB
Twist the pins of TO-220 or TO-247 to accommodate GDS board layout
Use shortest sense loop for probing. Attach the probe and its ground connection
directly to the test points
Use differential mode probe, or probe
ground clip with long wire
Preliminary Data
Jan. 18, 2016 YW
Use long traces in drive circuit, long lead
length of the devices
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