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M
AN691
Optimizing Digital Potentiometer Circuits to Reduce
Absolute and Temperature Variations
Author:
The two modes that a potentiometer can be configured
in are the Rheostat mode and Voltage Divider mode.
When used in the Rheostat mode, the wiper (terminal
PW), is shorted to either the PA or PB terminal of the
device. This configuration is shown in Figure 2. When
a digital potentiometer is used in the Voltage Divider
mode (Figure 2.b) all three terminals are connected to
differing nodes in the circuit.
Bonnie C. Baker,
Microchip Technology Inc.
INTRODUCTION
Mechanical potentiometers are typically used to adjust
system reference levels, gain errors and offset errors.
Digital potentiometers can be used for the same functions while offering the added capability of digital
adjustment control. Devices, such as Microchip’s
MCP41XXX and MCP42XXX digital potentiometer
families, can be used much like a mechanical potentiometer in that they have three resistive terminals for
the single versions (MCP41010, MCP41050, and
MCP41100) and six resistive terminals for the dual versions (MCP42010, MCP42050, and MCP42100) as
illustrated in Figure 1.
PA0
PW0
PB0
In both of these configurations, the digital potentiometer will have a nominal resistance and temperature
coefficient error that may affect the overall application
unless precautions are taken. In this application note,
circuit ideas will be presented that use the necessary
design techniques to mitigate these errors, consequently optimizing the performance of the digital potentiometer.
PA1
PW1
PB1
PA PW PB
RDAC2
RDAC1
Data Register 1
Data Register 0
D7
D7
D0
Digital
Potentiometer
Model
D0
RS
Decode
Logic
CS
D7
D0
PA PW PB
16-bit Shift Register
SCK
SI
SO
SHDN
Mechanical
Potentiometer
Model
Dual Digital Potentiometer
FIGURE 1: The operation of the digital potentiometer as compared to the mechanical potentiometer is functionally
the same. The adjustment of the digital potentiometer is done with a serial code to the device. Although the mechanical
potentiometer provides simplicity, the digital potentiometer provides flexibility and reliability.
 2001 Microchip Technology Inc.
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Rheostat Mode Operation and Specifications
n is the number of digital potentiometer bits. For
the MCP4XXXX family of potentiometers, the
number of bits is eight.
In the Rheostat mode, either terminal PA or PB are connected to the wiper terminal as shown in Figure 2.a. In
this mode, the output resistance is digitally adjusted
from the maximum nominal value, minus one LSB,
down to zero ohms. The nominal resistance of the element in the Rheostat mode is calculated with the following formulas:
Dn is the digital code in decimal form that is used
to program the digital potentiometer. With the
MCP4XXXX 8-bit digital potentiometers the programmable digital code ranges from 0 to 28 - 1 or
255.
RAB ( D N )
RBW = ------------------------ + R W
2N
RW is the parasitic resistance through the wiper.
As summarized in the table in Figure 2, the nominal
resistance of the digital potentiometer varies, depending on the device selected. Additionally, the part to part
variation of the nominal resistance is specified to be
within a given percentage. For example, the nominal
resistance of the MCP4X010 is 10 kΩ ±20%. The resistance variation of these digital potentiometers is primarily dependent on the process variation of the sheet-rho
of a diffused p-silicon layer and the on-resistance of the
internal switches.
or
R AB 2 – D N 
R
= ---------------------------------------- + R
AW
W
N
2
N
where:
RAW is the resistance between pin A and pin W of
the digital potentiometer.
The temperature variance of the digital potentiometers
element is also shown in Figure 2. For instance, the
variance of the MCP41010 (10 kΩ) digital potentiometer is 800 ppm/°C (typical). With this specification, the
expected change of the total resistance of the
MCP41010 is from 10 kΩ at 25°C to 9.52 kΩ at 85°C.
RAB is the nominal resistance across the entire
potentiometer, from pin A to pin B.
RBW is the resistance between pin B and pin W of
the digital potentiometer.
PW
PA
PA
PB
PB
a. Rheostat Mode
Device
Nominal
RAB
Resistance
(typ)
PW
b. Voltage Divider Mode
RAB Change
RA, RB
with
Relative
Nominal
Temperature Resistance Accuracy INL
(typ)
(typ)
Match (typ)
Tempco
Variance
Between RA
and RB (typ)
Code to Code
Variance
DNL (typ)
MCP41010
(single)
10 KΩ ±20%
800 ppm/°C
-----
±0.25 LSB
1%
±0.25 LSB
MCP42010 (dual)
10 KΩ ±20%
800 ppm/°C
0.2%
±0.25 LSB
1%
±0.25 LSB
MCP41050
(single)
50 KΩ ±30%
800 ppm/°C
-----
±0.25 LSB
1%
±0.25 LSB
MCP42050 (dual)
50 KΩ ±30%
800 ppm/°C
0.2%
±0.25 LSB
1%
±0.25 LSB
MCP41100
(single)
100 KΩ ±30%
800 ppm/°C
-----
±0.25 LSB
1%
±0.25 LSB
MCP42100 (dual)
100 KΩ ±30%
800 ppm/°C
0.2%
±0.25 LSB
1%
±0.25 LSB
FIGURE 2:
The resistive elements of the digital potentiometer can be configured in (a.) the Rheostat mode or (b.) the Voltage
Divider mode. Each mode has its own set of performance specifications.
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Digital Potentiometer Circuits Configured in the
Rheostat Mode
The level of nominal resistive matching that is shown in
Figure 2 can be acceptable for some applications.
However, if a degree of precision is desired, the dual
potentiometer can be used to an advantage in the
Rheostat mode. With the dual digital potentiometer, the
nominal resistances between the two potentiometers
are ratio matched to a very small percentage as shown
in Figure 2. For instance, the matching of the two resistive potentiometer elements in the MCP42010 (dual,
10 kΩ) is guaranteed to be less than ±0.2% (typ). This
close relationship between the two resistor arrays can
be used to a distinct advantage.
One circuit that takes advantage of the relationship
between the two potentiometers in the dual,
MCP42100 is shown in Figure 3.
R2 (1/2 of MCP42100)
PW
PA
VIN VIN +
R1=1 KΩ
PB
VOUT
R3=1 KΩ
+
PW PA
PB
R4 (1/2 of MCP42100)
VREF
FIGURE 3: The digital potentiometers in this
differential amplifier can be programmed to change
the gain of the circuit as well as enhance the commonmode rejection. The common-mode rejection of this
circuit is fairly immune to temperature changes.
In Figure 3, the arrangement of the resistors around an
operational amplifier is called the difference amplifier or
op amp subtractor. The DC transfer function of this circuit is equal to:
V 1 R 4 ( R1 + R2 )
(R + R )
 R 2
1
2
V OUT = ------------------------------------------- – V 2  ------- + V REF R 3 ---------------------------------------R 1
((R + R )R )
((R + R )R )

3
4 1
3
4 1
The fact that R1/R2 is equal to R3/R4 simplifies the
mathematics in this system considerably. Since the
gain of both input signals are the same, the commonmode voltage (CMV) of the two signals is conveniently
subtracted from the output results.
Ideally, CMV changes are rejected by this circuit. The
calculated common-mode rejection (CMR) error that is
attributed to resistor mismatches in this circuit is equal
to:
 R1 
 1 + ------- 
 R2 
CMR = 100 ----------------------------------------------------% of mismatch error
where (% of mismatch error) is the mismatch in the
equation R1/R2 = R3/R4.
An example of the impact of this error is demonstrated
with a 12-bit, 5V system, where the gain of the circuit is
100V/V, the common-mode voltage ranges 0 to 5V and
the matching error is ±0.2%. Using the formula above,
the contributed error of this type of common-mode
excursion is equal to 0.2 mV. This voltage is five times
less than 1 LSB.
Adjustable gain is easily implemented by making the
discrete resistors equal (R1=R3) and changing both
potentiometers together as desired. Although, any digital potentiometer can be used in the R2 and R4 position
in this circuit, the higher the nominal value of the digital
potentiometer, the wider the adjustable gain range will
be.
In a single supply environment, a voltage reference is
used to center the output signal between ground and
the power supply. This voltage is represented in this circuit as VREF. The VREF circuit function can be implemented with a precision voltage reference or with an
adjustable voltage reference circuit that uses a digital
potentiometer as shown in Figures 5, 6 and 7. The
adjustable voltage reference designs offer the flexibility
of removing offset system errors.
An alternative to the circuit shown in Figure 3 is illustrated in Figure 4. In this circuit configuration, the differential inputs are high impedance and the output is
differential. There are three resistors used in this circuit, two of which are 1/2 of a dual potentiometer.
If R1/R2 is equal to R3/R4, the system gain of this circuit
equals:
R2
V OUT = ( V 1 – V 2 )  -------  + V REF
R1
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VIN1
+
VOUT1
PW
PA
PB
R2 (1/2 of a dual Digital Potentiometer)
R3 (1/2 of a dual Digital Potentiometer)
R1
PW
PA
PB
VOUT2
VIN2
+
FIGURE 4: This differential in and differential out
circuit uses two digital potentiometers in the Rheostat
mode. When the two digital potentiometers are set to
be equal, the gains on the two input signals are equal.
If R2 = R3, the transfer function of this circuit is:
(V
OUT1
–V
OUT2
) = (V
IN1
–V
2R 

2
-
IN2 )  1 + ---------R1 
This flexible gain circuit uses the matching of nominal
resistance and thermal shifts of the dual potentiometer
to an advantage.
Voltage Divider Mode: Operation and
Specifications
In the Voltage Divider mode shown in Figure 2, all three
terminals to the potentiometer are connected to separate nodes in the circuit. In this mode, the total resistance of the device is separated into two resistors. The
first being the resistance from terminal PB to the wiper
(PW) and the second is between terminal PA to the
wiper. The relationship between these two resistors is
equal to:
(D )
n
R B = R AB -----------2n
 2n – D 
n

R A = R AB -------------------------n
2
where:
There is a third resistance from the digital potentiometers element to the wiper terminal. This resistance is
called the wiper resistance or RW. If the wiper of the
digital potentiometer is followed by a high impedance
node, errors caused by the wiper resistance are eliminated.
The absolute value of these resistances will still vary
between ±20% and ±30% (depending on the device
used), however as shown in the table in Figure 2, the
ratio between the two elements will be much lower. In
the case of the MCP4X010, the maximum mismatch
error between RB and RA is ±0.098% (DNL specification).
The related temperature performance of these two
resistors is also lower than the absolute temperature
behavior at a typical 1 ppm/°C. Since the resistive elements of RB and RA are manufactured with the same
material on the same chip, the ratio of the thermal
changes with temperature is considerably better as
compared to the single resistive element in the Rheostat mode.
Digital Potentiometer Circuits Configured in the
Voltage Divider Mode
The digital potentiometer can be used very effectively
in a variety of circuits when it is configured in the Voltage Divider mode. All of the following circuits take
advantage of the resistive ratio matching of the two
resistive elements (RB and RA).
Voltage Reference Circuits
One form of offset voltage adjustment is implemented
with a voltage reference. This type of adjustment usually compensates for all of the system offset errors in
the signal path.
In Figure 5, a digital potentiometer is used to design an
adjustable voltage reference. In Figure 5.a, the potentiometer is placed between the positive power supply
and ground. The output voltage of the adjustable reference is equal to:
V DD R POT B
–
V REF = ----------------------------------------R POT – AB
The resolution of this reference circuit is dependent on
the number of programmable bits of the digital potentiometer and the value of VDD. When using any of the 8bit digital potentiometers from Microchip and a 5V supply, the nominal LSB size would be 19.53 mV.
RB is equal to the resistance between the PB
terminal and PW terminal minus the wiper
resistance.
RA is equal to the resistance between the PA
terminal and PW terminal minus the wiper
resistance.
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If a smaller LSB size is required for an adjustable voltage reference that has the full dynamic range of the
power supply voltage, the circuit in Figure 6 can be
used.
VDD
RPOT
VDD
RA
+
VDD = 5V
-
RB
MCP606
A1
½ MCP602
RA
RPOT1
+
-
VREF-A
VREF-A
RB
RA
VREF-C
RB
V
V
R
DD ( POT – B )
= ---------------------------------------------REF – A
( R POT – AB )
VDD
RA
RPOT2
VDD
V DD ( R POTx – B )
V REF – A and V REF – B = ------------------------------------------------( R POTx – AB )
RA
+
MCP606
b.)
-
R3
VREF-B
+
R2
RB
A2
½ MCP602
RB
VDD
RPOT
RPOT3
-
a.)
V
VREF-B
V DD ( R POT B + R 3 )
–
V REF – B = ----------------------------------------------------------------(R + R
2
POT – AB + R 3 )
FIGURE 5: A digitally adjustable reference can be
designed using the power supply across the digital
potentiometer (a). Higher accuracy can be achieved
by using additional resistors (b) in series with the
digital potentiometer.
In this circuit, the operational amplifier acts to isolate or
buffer the digital potentiometer resistance from following stages.
The absolute accuracy and over temperature performance of the voltage presented to the input of the
amplifier is dependent on the matching of the digital
potentiometer resistive elements as well as the stability
of the power supply.
As an example of the effects of the digital potentiometer errors, the MCP4X010 (10 kΩ digital potentiometer)
would perform with an absolute accuracy less than
±0.25 LSB (typ) or ±3.9065 mV at 25°C. Over temperature, the output voltage would typically vary 1% due to
resistance matching. This translates into a typical variance over temperature (-40°C to +85°C) of 1.172 mV
or ±0.585 mV. Adding this to the error at room temperature, the total possible error becomes ±4.99 mV. In
this example, it is assumed that the power supply is a
stable 5V.
 2001 Microchip Technology Inc.
REF – C
(V
–V
)(R
)
REF – A
REF – B
POT3 – B
= -----------------------------------------------------------------------------------------------------( R POT3 – AB )
FIGURE 6: Three
digital
potentiometers
in
combination with a dual amplifier can be configured for
a wide dynamic range, adjustable voltage reference
that has an ideal LSB size of VDD / 22n, where n is the
number of digital potentiometer bits.
In this circuit, the wiper voltage of RPOT1 is buffered
with A1, a single supply, CMOS amplifier and RPOT2 is
buffered with A2. The dynamic range of the output of A1
and A2 is equal to approximately (GND+50 mV) to
(VDD−1.2V). The positive output swing range is primarily restricted by the amplifiers maximum input common
mode voltage. The theoretical LSB size of the voltages
at VREF-A and VREF-B are equal to VDD/2n or 19.53 mV.
The voltage difference of VREF-A and VREF-B is
impressed across RPOT3. The difference of these voltages are then divided again by the third digital potentiometer to have an ideal LSB size equal to:
n
( V DD ⁄ 2 )
V REF – C = -----------------------------n
2
V REF
–C
V DD
= ------------2n
2
The configuration in Figure 6 provides an theoretical
output resolution of 16 bits. When VDD is equal to 5V,
the theoretical LSB size is 76.29 µV.
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The value of the output of this precision adjustable reference is compromised by the absolute matching resistance and temperature coefficient of the digital
potentiometers.
In the error analysis of this circuit, it can quickly be
found that at 25°C, the nominal errors of the digital
potentiometer have the highest potential to create the
largest errors. This in shown in Table 1.
In this circuit, the variability of the power supply is stabilized with a precision voltage reference. Since the
digital potentiometer is configured in the Voltage
Divider mode, the errors at the output of the amplifier is
similar to the errors discussed in Figure 5. The only difference being that the power supply is replaced with a
precision reference. This configuration is often used
when the digital potentiometer is used as a DAC.
Offset Adjustment Circuits
Room
Temp.
Over -40°C
to 85°C
range
RPOT1
(±0.25 LSB typical error)
±0.019 mV
±0.003 mV
Offset adjustment can be implemented in the analog
circuit by injecting a voltage into the signal path with a
simple voltage divider or a complete adjustable voltage
reference.
RPOT2
(±0.25 LSB typical error)
±0.019 mV
±0.003 mV
In Figures 8 and 9, a digital potentiometer is used to
change the offset errors of a simple amplifier circuit.
RPOT3
(±0.25 LSB typical error)
±0.019 mV
±0.003 mV
Total typical error
at VREF-C
±0.057 mV
±0.009 mV
TABLE 1:
This table shows the nominal and
temperature errors effecting adjustable voltage
reference shown in Figure 6. Calculations assume A1
and A2 are ideal amplifiers, the MCP4X010 digital
potentiometers are used and VDD = 5V. All values are
referred to the output, VREF-C.
The errors of the first stage (including the amplifiers)
are divided down by the second stage. Given this error
analysis, the circuit in Figure 6 is accurate to 13.3 bits
or ±0.057 mV. This analysis does not take into account
variations in VDD over temperature.
Another technique that can be used to design a precision adjustable voltage reference is shown in Figure 7.
R1 <10 KΩ
VIN
R2 = 10 KΩ
VDD
VOFF
R4 =
10 KΩ
RW
RA
RB
MCP41010
R3 = 100 KΩ
VDD
10 KΩ
R5 =
10 KΩ
MCP601
+
VOUT
10 KΩ
FIGURE 8: A high resolution offset adjust circuit is
implemented in this standard inverting amplifier
configuration with the addition of a digital
potentiometer, R3, R4 and R5.
In this circuit, the amplifier is configured in a inverting
configuration. The transfer function for the input signal,
VIN is equal to:
R 2  V DD
V OUT = – V IN -------  + ------------2
R 1 
VDD
An offset voltage is injected with the same voltage
divider that was used in the circuit in Figure 5.b. The
transfer function of the offset voltage, VOFF is:
R1
VZ = 2.5V ±2.0%
RA
RPOT
VREF
or
DAC
Output
+
LM4040-2.5
(Precision
Voltage
Reference)
RB
MCP606
-
FIGURE 7: A precision adjustable reference can be
configured using a precision reference that is not
adjustable along with a digital potentiometer. The
value of R1 is set so that the current through the
LM4040 does not go below its minimum operating
current.
DS00691A-page 6
R2 
------V OUT = – V
OFF  R 
3
With the resistor values shown in the figure, the gain on
the VIN is 10V/V and the gain on VOFF is 0.1V/V. With
VDD = 5V, the LSB size of the offset adjust circuitry is
651 µV.
With this configuration, the nominal errors and over
temperature errors that are generated by the digital
potentiometer is 10X smaller than the errors discussed
in Figure 5.b.
Another method of implementing an analog offset
adjustment with a digital potentiometer is shown in
Figure 9.
 2001 Microchip Technology Inc.
AN691
R1<10 KΩ
VIN
R2=10 KΩ
VIN
RA
RPOT1
+
-
MCP41100
VOUT
RB
+
VOUT
-
10 KΩ
R2=10 KΩ
RA
RB
R3=100 KΩ
10 KΩ
MCP41010
FIGURE 10: An amplifier circuit designed with an
adjustable noninverting gain.
FIGURE 9: A lower resolution offset adjust circuit
using a digital potentiometer can be used to adjust
large system offsets.
In this circuit, the gain of the signal is equal to:
 R2 
V OUT = – V IN  ------- 
 R1 
And the gain of the offset adjust circuitry is equal to:
R 

2
 1 + ------- 
R1 

V OUT = V DD R POT B ----------------------------------------------------------------– (R
POT – AB + R 2 + R 3 )
The offset adjustment circuit used in this application
has the same topology as the circuit in Figure 5.b. Consequently, the errors due to this configuration is consistent with previous discussions.
Gain Adjust Amplifier Circuits
Circuit gain errors can compromise the analog dynamic
range of a circuit. These types of errors can be easily
calibrated out of the system digitally with the microcontroller, however, the analog dynamic range is never
fully utilized. Consequently, analog gain adjustments
are done where the full dynamic analog range is
needed.
In this circuit, the transfer function is:
R 

3
 1 + ------- 
R 

2
V OUT = V IN ------------------------------------------ R POT1 – B 
 ------------------------------------ 
 R POT1 – AB 
The adjustable gain is implemented with the digital
potentiometer, RPOT. Digital potentiometers that have
higher nominal values are best suited for this circuit.
Higher value resistances minimize the error that is contributed by the source resistance of VIN.
The maximum gain is equal to:
R 3   2 n – 1

Gain (max) =  1 + -------  –  ----------------
R2   n 

2
Using the values of resistors in Figure 10:
Gain (max) = (1 + 100kΩ/1kΩ) − (28 −1)/28
= 101.996V/V
At room temperature, the digital potentiometer’s DNL
error effects the circuit gain accuracy with gains that
are lower 10% of the range (assuming DNL (max) =
±0.25 LSB). This relationship is shown graphically in
Figure 11.
An example of an amplifier circuit that has an adjustable positive (noninverted) gain is shown in Figure 10.
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The circuit transfer function is:
R POT2 – A
R POT2 – A
V OUT = V IN  -------------------------  + V REF  -------------------------  + 1
R4 – B
R POT2 – B
With this circuit, the gain function versus digital potentiometer code is nonlinear as shown in Figure 13.
FIGURE 11: For the circuit in Figure 10, the gain vs.
digital code is linear. The maximum possible gain error
is logarithmic, decreasing with higher digital
potentiometer codes.
In terms of temperature effects on the digital potentiometer in this configuration, the changes of RA and RB
over temperature track at a rate of 800 ppm/°C (typ).
Since these elements are configured as a mathematical ratio, this error is cancelled. The variance between
the two elements over temperature is 1% (typ). This
variance will be directly translated into gain error over
temperature.
Another amplifier gain circuit that uses a digital potentiometer is shown in Figure 12. In this circuit, the amplifier circuit executes an inverting adjustable gain
function.
VDD
VREF
+
MCP601
-
VIN
RA
RB
RPOT2
FIGURE 13: The transfer function of VOUT to VIN of
the circuit shown in Figure 12 has a nonlinear
response over the code span of the digital
potentiometer. This phenomena creates a circuit that
gains the input signal below digital potentiometer
codes of 128 and attenuates the signal with codes
above 128.
The nominal accuracy of this gain cell is minimized
because the two sides of the digital potentiometer are
ratioed in the circuit transfer function. Any gain error at
room temperature is due to the DNL error of the digital
potentiometer. The maximum effects of the error is
shown graphically in Figure 13.
In terms of temperature effects on the digital potentiometer in this configuration, RA and RB are configured as
a mathematical ratio in the transfer function. This cancels the change in the 800 ppm/°C (typ) resistive element. The variance between the two elements over
temperature is 1% (typ). This variance will be directly
translated into gain error over temperature.
The circuits in Figure 10 and Figure 12 can be combined to build an adjustable gain difference amplifier
much like the circuit shown in Figure 3. This configuration is shown Figure 14.
 R POT2 – B

 R POT2 – B 
V OUT = V REF  ------------------------------- + 1 – V IN  ------------------------------- 
R
 POT2 – A

 R POT2 – A 
FIGURE 12: This amplifier circuit uses a digital
potentiometer to implement an adjustable inverting
gain.
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Once again, the common-mode rejection (CMR) error
that is attributed to resistor mismatches in this circuit is
equal to:
VIN+
VDD
1 + R
------1- 

R2 
CMR = 100 ---------------------------------------------------% of mismatch error
RA
+
RB
RPOT1
MCP601
VOUT
VREF
where (% of mismatch error) is the mismatch in the
equation R1/R2 = R3/R4.
CONCLUSION
VIN-
RA
RB
RPOT2
FIGURE 14: A difference amplifier that has stable
resistor matching and temperature coefficients.
If the digital code setting for RPOT1 and RPOT2 are
equal, the transfer function for this circuit is:
The digital potentiometer has entered the market with
clear advantages over the mechanical potentiometer.
Its programmability allows to change the offset, gain
and voltage references reliably as well as on the fly.
The effects of variances of the absolute resistances
and temperature drifts can be minimized if good circuit
design techniques are used.
R POTX – B
V OUT = ( V 1 – V 2 )  --------------------------  + V REF
 RX – A 
The gain of this circuit (VOUT/(V1-V2)) versus the digital
potentiometer code is shown graphically in Figure 15.
FIGURE 15: The gain of circuit in Figure 14 is greater
than one with digital code settings larger than 128 and
between zero and one for digital code settings less
than 128. The gain error, due to typical DNL errors, is
less than 1% between 28 and 229.
The temperature performance of this circuit is significantly improved over the circuit shown in Figure 3
because all of the resistors in this circuit are elements
of the digital potentiometers.
 2001 Microchip Technology Inc.
DS00691A-page 9
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NOTES:
DS00691A-page 10
 2001 Microchip Technology Inc.
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“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publication regarding device applications and the
like is intended through suggestion only and may be
superseded by updates. No representation or warranty
is given and no liability is assumed by Microchip
Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchip. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other countries. All
rights reserved. All other trademarks mentioned herein
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Embedded Control
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
Select Mode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respective companies.
© 2001, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
 2001 Microchip Technology Inc.
DS00691A-page 11
M
WORLDWIDE SALES AND SERVICE
AMERICAS
New York
Corporate Office
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Rocky Mountain
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Austin
Analog Product Sales
8303 MoPac Expressway North
Suite A-201
Austin, TX 78759
Tel: 512-345-2030 Fax: 512-345-6085
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Boston
Analog Product Sales
Unit A-8-1 Millbrook Tarry Condominium
97 Lowell Road
Concord, MA 01742
Tel: 978-371-6400 Fax: 978-371-0050
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Two Prestige Place, Suite 130
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Mountain View
Analog Product Sales
1300 Terra Bella Avenue
Mountain View, CA 94043-1836
Tel: 650-968-9241 Fax: 650-967-1590
ASIA/PACIFIC (continued)
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
EUROPE
China - Beijing
Denmark
Microchip Technology Beijing Office
Unit 915
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Germany
Analog Product Sales
Lochhamer Strasse 13
D-82152 Martinsried, Germany
Tel: 49-89-895650-0 Fax: 49-89-895650-22
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/30/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 5/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS00691A-page 12
 2001 Microchip Technology Inc.
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