CD4033BMS CMOS Decade Counter/Divider December 1992 Features Description • High Voltage Types (20V Rating) CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display. • Decoded 7 Segment Display Outputs and Ripple Blanking • Counter and 7 Segment Decoding in One Package • Easily Interfaced with 7 Segment Display Types • Fully Static Counter Operation DC to 6MHz (typ.) at VDD = 10V • Ideal for Low-Power Displays • “Ripple Blanking” and Lamp Test • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Schmitt-Triggered Clock Inputs • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device’s Applications This device is particularly advantageous in display applications where low power dissipation and/or low package count is important. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7 segment outputs go high on selection. • Decade Counting 7 Segment Decimal Display • Frequency Division 7 Segment Decimal Displays • Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/ Display • Counter/Display Driver For Meter Applications Functional Diagram Pinout VDD 16 1 CLOCK 1 CLOCK INHIBIT 2 RIPPLE BLANKING IN 3 15 RESET 13 c CARRY OUT 5 12 b f 6 11 e g 7 10 a VSS 8 9 d 12 b 13 c 2 CLOCK INHIBIT 14 LAMP TEST RIPPLE BLANKING OUT 4 10 a CLOCK 16 VDD 9 d 11 e 15 RESET LAMP TEST 6 7 g 14 3 RIPPLE BLK IN f 7 DECODED OUTPUTS CD4033BMS TOP VIEW 8 5 CARRY OUT 4 RIPPLE BLK OUT VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-826 File Number 3301 CD4033BMS The CD4033BMS has provisions for automatic blanking of the non-significant zeros in a multi-digit decimal number which results in an easily readable display consistent with normal writing practice. For example, the number 0050.0700 in an eight digit display would be displayed as 50.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the CD4033BMS associated with the most significant digit in the display to a low-level voltage and connecting the RBO terminal of that stage to the RBI terminal of the CD4033BMS in the next-lower significant position in the display. This procedure is continued for each succeeding CD4033BMS on the interger side of the display. On the fraction side of the display the RBI of the CD4033BMS associated with the least significant bit is connected to a low-level voltage and the RBO of that CD4033BMS is connected to the RBI terminal of the CD4033BMS in the next more-significant-bit position. Again, this procedure is continued for all CD4033BMS’s on the fraction side of the display. In a purely fractional number the zero immediately preceding the decimal point can be displayed by connecting the RBI of that stage to a high level voltage (instead of to the RBO of the next more-significant-stage). For example: optional zero → 0.7346. Likewise, the zero in a number such as 763.0 can be displayed by connecting the RBI of the CD4033BMS associated with it to a high-level voltage. Ripple blanking of non-significant zeros provides an appreciable savings in display power. The CD4033BMS has a LAMP TEST input which, when connected to a high-level voltage, overrides normal decoder operation and enables a check to be made on possible display malfunctions by putting the seven outputs in the high state. The CD4033BMS are supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H2R H6W Logic Diagram *LAMP TEST COUT (CLOCK 5 14 15* D Q CL CL Q R D Q CL CL Q R D Q CL CL Q R D Q CL CL Q R D Q CL CL Q R ÷ 10) 10 a 12 RESET b 13 c 9 d *CLOCK 11 1 e CL *CLOCK 6 INHIBIT 2 f 7 g *RBI 3 4 16 RBO a VDD VDD 8 GND *ALL INPUTS PROTECTED f BY CMOS INPUT PROTECTION NETWORK g e VSS FIGURE 1. CD4033BMS 7-827 b c d SEGMENT DESIGNATIONS Specifications CD4033BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 - 10 µA +125oC - 1000 µA 3 -55oC - 10 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 1 -55oC VDD = 18V MAX 2 oC 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-828 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4033BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock To Carry Out SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Reset To Carry Out TPLH3 VDD = 5V, VIN = VDD or GND Transition Time Maximum Clock Input Frequency 9 10, 11 Propagation Delay Clock To Decode Out Propagation Delay Reset To Decode Out GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 9 10, 11 FCL VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 500 ns - 675 ns - 700 ns - 945 ns - 550 ns - 743 ns - 600 ns - 810 ns - 200 ns - 270 ns 2.5 - MHz 1.85 - MHz NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 -55 C, +25 C - 10 µA +125oC - 300 µA - 10 µA o -55oC, o +25oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA oC +125 Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 7-829 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -2.6 mA Specifications CD4033BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Output Current (Source) IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -2.4 mA o -55 C - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V Propagation Delay Clock To Carry Out TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 150 ns o - 250 ns o Propagation Delay Clock To Decode Out TPHL2 TPLH2 VDD = 10V VDD = 15V 1, 2, 3 +25 C - 180 ns Propagation Delay Reset To Carry Out TPLH3 VDD = 10V 1, 2, 3 +25oC - 240 ns VDD = 15V 1, 2, 3 +25oC - 160 ns Propagation Delay Reset To Decode Out TPHL4 TPLH4 VDD = 10V 1, 2, 3 +25oC - 250 ns 1, 2, 3 +25oC - 180 ns Transition Time TTHL TTLH Maximum Clock Input Frequency FCL Minimum Reset Pulse Width TW VDD = 15V TREM 1, 2, 3 +25 C - 100 ns 1, 2, 3 +25oC - 50 ns 1, 2, 3 +25oC 5.5 - MHz VDD = 15V 1, 2, 3 +25 oC 8 - MHz VDD = 5V 1, 2, 3 +25oC - 120 ns 1, 2, 3 o +25 C - 100 ns VDD = 15V 1, 2, 3 +25 oC - 50 ns VDD = 5V 1, 2, 3 +25oC - 30 ns 1, 2, 3 +25 oC - 15 ns VDD = 15V 1, 2, 3 +25oC - 10 ns VDD = 5V 1, 2, 3 +25oC - 220 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7 pF VDD = 10V VDD = 15V Input Capacitance CIN o VDD = 15V VDD = 10V TW +25 C VDD = 10V VDD = 10V Minimum Reset Removal Time Minimum Clock Pulse Width 1, 2, 3 Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC MIN MAX UNITS - 25 µA -2.8 -0.2 V - ±1 V N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND 7-830 Specifications CD4033BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Propagation Delay Time TPHL TPLH CONDITIONS VDD = 5V NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test 1, 7, 9 100% 5004 1, 7, 9, Deltas IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group B 100% 5004 Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9( Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 4 - 7, 9 - 14 1 - 3, 8, 15 16 Static Burn-In 2 (Note 1) 1, 2, 14, 15 3 - 6, 8, 10 - 13 7, 9, 16 Dynamic BurnIn (Note 1) - 2, 8, 15 3, 16 4 - 7, 9 - 14 8 1 - 3, 15, 16 9V ± -0.5V 50kHz 4 - 7, 9 - 13 1 PART NUMBER Irradiation (Note 2) PART NUMBER CD4033BMS 7-831 25kHz Specifications CD4033BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 4 - 7, 9 - 13 1 - 3, 8, 14, 15 16 Static Burn-In 2 Note 1 4 - 7, 9 - 13 8 1 - 3, 14 - 16 Dynamic BurnIn Note 1 - 2, 3, 8, 14, 15 16 4 - 7, 9 - 13 8 1 - 3, 14 - 16 Irradiation Note 2 9V ± -0.5V 50kHz 4 - 7, 9 - 13 1 25kHz NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Timing Diagram CLOCK RESET R CLOCK INHIBIT CL CL LAMP TEST p p D RBI COUT (CLOCK ÷ 10) n CL a CL CL b D c CL Q e R f CL g ≡ Q CL p p n n CL CL Q d Q n CL CL RBO 0 1 234 5 6 78 9 0 1 8 4 56 7 8 9 12 FIGURE 2. CD4033BMS TIMING DIAGRAM FIGURE 3. DETAIL OF TYPICAL FLIP-FLOP STAGE 7-832 CD4033BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 15 5V 0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 5. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V SUPPLY VOLTAGE (VDD) = 5V 400 200 10V 15V 0 20 40 60 80 -10 -15V -15 FIGURE 7. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (µs) PROPAGATION DELAY TIME (tPLH, tPHL) (µs) 600 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 6. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 100 AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 LOAD CAPACITANCE (CL) (pF) 20 40 60 80 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FOR DECODED OUTPUTS FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FOR CARRY-OUT OUTPUTS 7-833 100 CD4033BMS 105 20 o AMBIENT TEMPERATURE (TA) = +25 C tr = tf = 20ns POWER DISSIPATION (PD) (µW) MAXIMUM CLOCK INPUT - FREQUENCY (fCL) (MHz) Typical Performance Characteristics (Continued) 15 10 5 AMBIENT TEMPERATURE (TA) = +25oC 8 6 4 2 104 SUPPLY VOLTAGE (VDD) = 5V 8 6 4 2 103 10V 8 6 4 10V 15V 2 102 8 6 4 (CL) = 15pF LOAD CAPACITANCE (CL) = 50pF 2 10 0 2 4 6 8 10 12 14 16 2 4 68 1 2 4 68 SUPPLY VOLTAGE (VDD) (V) 2 102 10 4 68 103 2 4 68 104 2 4 68 105 INPUT PULSE FREQUENCY (fCL) (MHz) FIGURE 10. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 11. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY Light Emitting Diode Displays MONSANTO MAN 3 OR EQUIVALENT (LOW POWER) VDD IB VDD 1/7 CA3082 OR EQUIVALENT A CLOCK INHIBIT R 7 SEGMENTS CD4033BMS CLOCK A G G R VSS G R VDD ≥ 3.5V IF ≈ 5mA/SEGMENT 100% DUTY CYCLE VP - VBE - VF(LED) R= ILED IF IB R G VSS A IB G VDD 5V (MIN) IB 0.4mA IF 12mA/Seg.(100% DUTY CYCLE) bdc(MIN) 30 VCE(SAT) £ 0.5V WHERE VP = INPUT PULSE VF = FORWARD DROP ACROSS DIODE R= VDD - VCE(sat)-VF(LED) ILED WHERE VF = FORWARD DROP ACROSS DIODE FIGURE 12. INTERFACING THE CD4033BMS WITH COMMERCIALLY AVAILABLE LIGHT EMITTING DIODE DISPLAYS 7-834 A R RESET IF IB A 7 SEGMENTS INHIBIT RESET VDD MAN 1 R VDD MAN 3 A CD4033BMS 1/7 CA3082 OR EQUIVALENT MONSANTO MAN 1 OR EQUIVALENT G CD4033BMS 7-Segment Display Devices 1/7 SEGMENTS INCANDESCENT READOUTS Numitron DR2000 Series TUBE REQUIREMENTS VT = 3.5 - 5V IT = 24mA Segment VT IB IT VDD CD4033BMS CLOCK INHIBIT ASSUMED TRANSISTOR CHARACTERISTICS 1/7 CA3081 OR EQUIVALENT 7 SEGMENTS VT RESET VCC VSS 1 OF 7 SEGMENTS 1/6 CA4049UB LOW-POWER INCANDESCENT READOUTS PINLITES INC-Series O and R TUBE REQUIREMENTS 0-03-15 0-04-30 0-06-30 R-R3-20 R-R4-30 VT(V) 1.5 3 3 2 3 mA/Segment 8 8 8 4.3 4.3 βdc (min) ≥ 25 VCE (sat) ≤ 0.5V VDD = 8V (min) IB = 1mA (min) IT = 24mA (min) CD4049UB at VCC = 10V (min) Vo “0” ≤ 2V IT = 8mA (min) VT ≈ 3.5V to 6V CD4049UB at VCC = 10V (min) Vo “0” ≤ 0.6V IT = 8mA (min) IT ASSUMED TRANSISTOR CHARACTERISTICS at VCC = 6V (min) Vo “0” ≤ 1V IT = 5mA (min) VT ≈ 1.5V to 3.5V βdc (min) ≥ 30 VCE (sat) ≤ 0.5V VCC ≥ 3.5V (min) IB ≥ 0.25mA (min) IT ≤ 7.5mA (min) *The interfacing buffers shown, while a necessity with the CD4033A, are not required when using the “B” devices; the “B” outputs (≈ 10 times the “A” outputs) can drive most display devices directly especially at voltages above 10V. VDD VT ª 170V DC VDD CLOCK INHIBIT 1 OF 7 SEGMENTS CD4033BMS CLOCK 7 SEGMENTS 13.5V LOGIC VOLTAGE RESET CD4033BMS INHIBIT RESET 7 SEGMENTS VSS e VSS d c f b g a ≈ 4.5V WITH VON = 18V MEDIUM BRIGHTNESS IN LOW AMBIENT LIGHT BACKGROUND WILL RESULT. THE POINT OF NO NOTICEABLE GLOW IS VOFF ≈ 4.5V NEON READOUT (NIXIE TUBE**) 1. Alco Electronics - MG19 2. Burroughs - B5971, B7971, B8971 TUBE REQUIREMENTS Alco MG19 Burroughs B5971 Burroughs B7971, B8971 VT(Vdc) 180 170 170 **(Trademark) Burroughs Corp. TRANSISTOR CHARACTERISTICS Leakage with transistor cutoff - 0.05mA V(BR)CER βdc (min) ≥ 30 mA/Segment 0.5 3 6 1.6V AC OR DC LOW VOLTAGE VACUUM FLORESCENT READOUTS 1. Tung-Sol DIGIVAC S/G ‡ Type DT1704A or DT1705C 2. Nippon Electric (NEC): Type DG12E or LD915 TUBE REQUIREMENTS: 100 to 300 µA/segment at tube voltages of 12V to 25V depending on required brightness Filament requirement 45mA at 1.6V, ac or dc. >VT ‡ (Trademark) Wagner Electric Co. FIGURE 13. INTERFACING THE CD4033BMS WITH COMMERCIALLY AVAILABLE 7-SEGMENT DISPLAY DEVICES* 7-835 CD4033BMS Chip Dimensions and Pad Layouts Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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