IDT ICS853111AYLF

ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TOLVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853111A is a low skew, high perforICS
mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™
E C L Fa n o u t B u f fe r a n d a m e m b e r o f t h e
H i Pe r C l o ckS ™ fa m i l y o f H i g h Pe r fo r m a n c e
Clock Solutions from I DT. The ICS853111A
is characterized to operate from either a 2.5V, 3.3V or a
5V power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS853111A ideal for those clock
distribution applications demanding well defined performance and repeatability.
• Ten differential LVPECL outputs
• Two selectable differential LVPECL PCLK/nPCLK clock inputs
• PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nPCLK input
• Additive phase jitter, RMS: <0.3ps (typical)
• Output skew: 23ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: 705ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Q1
nQ1
nQ6
Q6
nQ5
VCCO
15
Q7
Q2
27
14
nQ7
Q3
nQ3
nQ1
28
13
Q8
Q1
29
12
nQ8
Q4
nQ4
nQ0
30
11
Q9
Q0
31
10
nQ9
Q5
nQ5
VCCO
32
9
VCCO
1
2
3
4
5
6
7
8
PCLK1
nPCLK1
VEE
Q7
nQ7
ICS853111A
VBB
Q6
nQ6
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
Q8
nQ8
Q9
nQ9
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
Q5
16
26
nPCLK0
VBB
nQ4
25
nQ2
Q2
nQ2
CLK_SEL
Q4
24 23 22 21 20 19 18 17
VCCO
PCLK0
1
Q3
PCLK1
nPCLK1
Q0
nQ0
VCC
0
CLK_SEL
PCLK0
nPCLK0
PIN ASSIGNMENT
nQ3
BLOCK DIAGRAM
1
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VCC
Power
Type
Description
2
CLK_SEL
Input
Pulldown
3
PCLK0
Input
Pulldown
4
nPCLK0
Input
Pullup/Pulldown
5
V BB
Output
6
PCLK1
Input
Pulldown
7
nPCLK1
Input
Pullup/Pulldown
8
V EE
Power
Positive supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
Inver ting differential LVPECL clock input.
VCC/2 default when left floating.
Bias voltage.
Non-inver ting differential clock input.
Inver ting differential LVPECL clock input.
VCC/2 default when left floating.
Negative supply pin.
9, 16, 25, 32
VCCO
Power
Output supply pins.
10, 11
nQ9, Q9
Output
Differential output pair. LVPECL interface levels.
12, 13
nQ8, Q8
Output
Differential output pair. LVPECL interface levels.
14, 15
nQ7, Q7
Output
Differential output pair. LVPECL interface levels.
17, 18
nQ6, Q6
Output
Differential output pair. LVPECL interface levels.
19, 20
nQ5, Q5
Output
Differential output pair. LVPECL interface levels.
21, 22
nQ4, Q4
Output
Differential output pair. LVPECL interface levels.
23 , 2 4
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
26, 27
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
28, 29
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
30, 31
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
RPULLDOWN
Input Pulldown Resistor
75
kΩ
RVCC/2
Pullup/Pulldown Resistors
50
kΩ
Outputs
PCLKx
nPCLKx
Q0:Q9
nQ0:Q9
0
1
LOW
HIGH
1
0
1
0
Biased;
NOTE 1
Biased;
NOTE 1
Maximum
Units
TABLE 3B. CONTROL INPUT
FUNCTION TABLE
TABLE 3A. CLOCK INPUT FUNCTION TABLE
Inputs
Typical
Input to Output Mode
Polarity
Differential to Differential
Non Inver ting
CLK_SEL
Selected Source
0
PCLK0, nPCLK0
1
PCLK1, nPCLK1
HIGH
LOW
Differential to Differential
Non Inver ting
LOW
HIGH
Single Ended to Differential
Non Inver ting
HIGH
LOW
Single Ended to Differential
Non Inver ting
Inputs
Biased;
0
HIGH
LOW
Single Ended to Differential
Inver ting
NOTE 1
Biased;
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
2
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
6V (LVPECL mode, VEE = 0)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
-6V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5 V
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
50mA
Surge Current
yond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating con-
Outputs, IO
Continuous Current
100mA
ditions for extended periods may affect product reliability.
VBB Sink/Source, IBB
± 0.5mA
Operating Temperature Range, TA
-40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
37.8°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol
Parameter
VCC
Positive Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
3.3
5.25
V
85
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol
Parameter
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.37
2.295
2.33
2.365
V
VOL
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VIH
Input High Voltage, Single-Ended
2.075
2.36
2.075
2.36
2.075
2.36
V
VIL
Input Low Voltage, Single-Ended
Output Voltage Reference;
NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
1.43
1.765
1.43
1.765
1.43
1.765
V
1.86
1.98
1.86
1.98
1.86
1.98
V
1200
150
1200
150
1200
mV
3.3
1.2
3.3
1.2
3. 3
V
200
µA
VBB
VPP
VCMR
IIH
IIL
150
1.2
800
200
-10
800
20 0
-10
800
-10
-200
-200
-200
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
3
µA
µA
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Ma x
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.495
1.53
1.565
V
VOL
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VIH
Input High Voltage, Single-Ended
1.275
1.56
1.275
1.56
1.275
-0.83
V
VIL
Input Low Voltage, Single-Ended
0.63
0.965
0.63
0.965
0.63
0.965
V
VPP
150
1200
150
1200
150
1200
mV
2.5
1.2
2.5
1.2
2.5
V
IIH
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
200
µA
IIL
Input
Low Current
VCMR
800
1.2
800
200
PCLK0, PCLK1
-10
800
200
-10
-10
µA
nPCLK0, nPCLK1
-200
-200
-200
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
µA
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Output High Voltage; NOTE 1
3.875
3.975
4.08
3.925
3.995
4.07
3.995
4.03
4.065
V
3.245
3.22
3.235
Symbol
Parameter
VOH
Units
VOL
Output Low Voltage; NOTE 1
3.105
3.38
3.125
3.315
3.14
3.33
V
VIH
Input High Voltage, Single-Ended
3.775
4.06
3.775
4.06
3.775
4.06
V
VIL
Input Low Voltage, Single-Ended
Output Voltage Reference;
NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
3.13
3.465
3.13
3.465
3.13
3.465
V
3.56
3.68
3.56
3.68
3.56
3.68
V
1200
150
1200
15 0
1200
mV
5
1.2
5
1.2
5
V
200
µA
VBB
VPP
VCMR
IIH
IIL
150
800
1.2
200
-10
800
200
-10
800
-10
-200
-200
-200
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
4
µA
µA
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol
-40°C
Parameter
IIH
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Output Voltage Reference;
NOTE 2
Peak-to-Peak
Input Voltage
Input High Voltage
Common Mode Range;
NOTE 3, 4
Input
PCLK[0:1],
High Current nPCLK[0:1]
IIL
Input
Low Current
VOH
VOL
VIH
VIL
VBB
VPP
VCMR
PCLK[0:1]
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
-1.125
-1.025
-0.92
-1.075
-1.005
-0.93
-1.005
-0.97
-0.935
V
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.765
-1.67
V
-1.225
-0.94
-1.225
-0.94
-1.225
-0.94
V
-1.87
-1.535
-1.87
-1.535
-1.87
-1.535
V
-1.44
-1.32
-1.44
-1.32
-1.44
-1.32
V
1200
150
1200
150
1200
mV
0
VEE+1.2V
0
VEE+1.2V
0
V
200
µA
150
800
VEE+1.2V
80 0
200
800
200
-10
-10
-10
µA
nPCLK[0:1]
-200
-200
-200
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
µA
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
-40°C
Symbol
Parameter
fMAX
Output Frequency
t PD
Propagation Delay; NOTE 1
Min
25°C
Typ
Max
Min
>3
570
Typ
85°C
Max
Min
>3
670
770
605
705
Typ
Max
>3
805
665
76 5
Units
GHz
875
ps
tsk(o)
Output Skew; NOTE 2, 4
23
35
23
35
23
35
ps
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
85
150
85
150
85
150
ps
t jit
tR/tF
Output Rise/Fall Time
20% to 80%
0.03
85
0.03
200
315
100
200
0.03
285
85
200
ps
31 5
ps
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
5
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
0
-10
-20
Input/Output Additive
Phase Jitter at 155.52MHz
-30
= 0.03ps (typical)
-40
SSB PHASE NOISE dBc/HZ
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
6
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
VCCO
Qx
VCC
SCOPE
nPCLK0,
nPCLK1
LVPECL
V
V
CMR
PCLK0,
PCLK1
VEE
-3.25V to -0.375V
VEE
DIFFERENTIAL INPUT LEVEL
OUTPUT LOAD AC TEST CIRCUIT
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(o)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
80%
nPCLK0,
nPCLK1
PCLK0,
PCLK1
nQ0:nQ9
80%
VSW I N G
Clock
Outputs
Cross Points
PP
nQx
20%
20%
tR
tF
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
PROPAGATION DELAY
7
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
Figure 2A shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
VCC
R1
1K
Single Ended Clock Input
PCLKx
V_REF
nPCLKx
C1
0.1u
R2
1K
FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can
be wired to accept single ended LVPECL levels. The reference
voltage level VBB generated from the device is connected to the
negative input. The C1 capacitor should be located as close as
possible to the input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
8
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
V CMR input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R3
120
R2
50
SSTL
R4
120
Zo = 60 Ohm
Zo = 50 Ohm
PCLK
PCLK
Zo = 60 Ohm
nPCLK
Zo = 50 Ohm
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R3
1K
R4
1K
PCLK
PCLK
R5
100
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerClockS
Input
R1
1K
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PCL K/n PC LK
R2
1K
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS
PCLK/nPCLK INPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
OUTPUTS
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUTS
ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FOUT
50Ω
VCC - 2V
FIN
Zo = 50Ω
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination.
Figure 6A shows standard termination for 5V LVPECL. The
termination requires matched load of 50Ω resistors pull down to
V CC - 2V = 3V at the receiver. Figure 6B shows Thevenin
equivalence of Figure 6A. In actual application where the 3V DC
power supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
PECL
PECL
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
R1
50
-
PECL
R1
125
R2
50
PECL
R2
125
3V
FIGURE 6B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
FIGURE 6A. STANDARD 5V LVPECL OUTPUT TERMINATION
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SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853111A LVPECL buffer. Figure 7 shows a schematic
example of the ICS853111A LVPECL clock buffer. In this
example, the input is driven by an LVPECL driver. CLK_SEL is
set at logic low to select PCLK0/nPCLK0 input.
Zo = 50
+
Zo = 50
R2
50
VCC
32
31
30
29
28
27
26
25
C6 (Option)
0.1u
Zo = 50 Ohm
1
2
3
4
5
6
7
8
Zo = 50 Ohm
R4
1K
R10
50
C8 (Option)
0.1u
R11
50
9
10
11
12
13
14
15
16
R9
50
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
VCCO
nQ9
Q9
nQ8
Q8
nQ7
Q7
VCCO
3.3V LVPECL
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
VCC
-
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
R1
50
R3
50
24
23
22
21
20
19
18
17
U1
ICS853111
VCC
Zo = 50
+
VCC=3.3V
Zo = 50
(U1-9)
VCC
(U1-16)
(U1-25)
(U1-32)
-
(U1-1)
R8
50
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
R7
50
C5
0.1uF
C7 (Option)
0.1u
R13
50
FIGURE 7. EXAMPLE ICS853111A LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111A.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853111A is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.25V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 85mA = 446.3mW
•
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 446.3mW + 309.4mW = 755.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.547W * 42.1°C/W = 93°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.935V
(VCC_MAX - VOH_MAX) = 0.935V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.67V
(VCCO_MAX - VOL_MAX) = 1.67V
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V
L
CCO_MAX
- VOH_MAX))/R ] * (VCCO _MAX- VOH_MAX) =
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V
L
CCO_MAX
- VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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RELIABILITY INFORMATION
TABLE 8 θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111A is: 1340
Pin compatible with MC100EP111 and MC100LVEP111
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
0.60
0.75
L
0.45
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS853111AY
ICS853111AY
32 Lead LQFP
tray
-40°C to 85°C
ICS853111AYT
ICS853111AY
32 Lead LQFP
1000 tape & reel
-40°C to 85°C
ICS853111AYLF
ICS853111AYL
32 Lead "Lead-Free" LQFP
tray
-40°C to 85°C
ICS853111AYFT
ICS853111AYL
32 Lead ""Lead-Free"" LQFP
1000 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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REVISION HISTORY SHEET
Rev
Table
A
T4A
T4D
T5
B
Page
11
13 & 14
1
3
4
5
7
11
13 & 14
3
B
B
T10
17
T4B
3
T4C, T4D
4
T4E
5
C
12
Description of Change
Corrected Figure 5C.
Power Considerations - corrected Power(outputs)MAX from 30.2mW to 30.94mW,
and revised Junction Temperature and Worse Case Power Dissipation
equations.
Features section - increased voltage range to 5.25V.
Power Supply table - increased maximum VCC to 5.25V.
Added 5V LVPECL DC Characteristics table.
AC Characteristics table - increased VEE range to -5.25V to 2.375V, and VCC
to 2.375V to 5.25V.
Corrected Output Load AC Test Circuit Diagram, VEE range from" -1.8V to 0.375V" to "-3.25V to -0.375V".
LVPECL clock Input Interface - added another CML driver diagram.
Power Considerations - changed Power(core)max from 3.8V to 5.25V and
recalculated equations.
Absolute Maximum Ratings, corrected Supply Voltage & Negative Supply
Voltage from 4.6V & -4.6V to 6V & -6V.
Ordering Information Table - added lead-free marking to par t number.
Updated datasheets.
LVPECL 3.3V DC Characteristics Table - corrected IIH max. from 150µA to
200µA; and IIL min. from -150µA to -200µA.
LVPECL DC Characteristics Tables - corrected IIH max. from 150µA to 200µA;
and IIL min. from -150µA to -200µA.
ECL DC Characteristics Table - corrected IIH max. from 150µA to 200µA; and IIL
min. from -150µA to -200µA.
Added Termination for 5V LVPECL Output section.
IDT ™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
18
Date
10/31/03
4/28/04
5/14/04
7/6/07
10/25/07
ICS853111AY REV. C OCTOBER 25, 2007
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
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© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo, ICS and HiPerClocks are
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