Multimedia SoC Vogager Family ‑ Embedded Graphics SM502 Key Features Mobile Multimedia Companion Chip PCI/32bit host bus support for the processor interface (SH-4, Power PC, Xscale, MIPS, ARM) 200 MHz DAC support 1280×1024 resolution Supports 18/24-bit TFT panel and 8/12-bit CSTN panel 128-bit 2D graphic engine 0/8MB embedded SDRAM Supports seven layers of display frames (2 hardware cursors, primary graphics, video, video alpha, alpha, and secondary graphics) Supports two 8-bit ports or one 16-bit port/ITU601 ZV capture port USB1.1 host and slave, UART/IrDA, I2C AC97 2 DMA controllers support 8051 u-controller embedded Power consumption < 500mW Overview The SM502 is a Mobile Multimedia Companion Chip (MMCC™) device packaged in a 297-pin Ball Grid Array and is backward-compatible with the SM501. Designed to comply with needs of the embedded sector, the SM502 has video and 2D capabilities. To decrease system costs, the SM502 supports a diverse array of I/Os, including analog RGB and digital LCD Panel interfaces, an 8-bit parallel interface, USB, UART, IrDA, two Zoom Video (ZV) interfaces, AC97 or I-S, SSP, PWM, and I-C. The additional GPIO bits that can be utilized to interface with external devices. The 2D engine has front-end color space conversion with 4:1 and 1:8 scaling support. The video engine supports two different video outputs (Dual Monitor) at 8, 16, or 32-bit per pixel and a 3-color hardware cursor per video output. The LCD Panel video pipe supports back-end YUV color space conversion with 4:1 and 1:212 scaling. A ZV port is also included as an interface for external circuitry for MPEG decoding or TV input. Applications Packaging Thin client Education machine UMPC Surveillance Medical patient monitors IPC Embedded product monitors Signage Military PDA 297-pin BGA (19mm×19mm) Video Layers and Data Processing Hardware Cursor 64x64, 2-bpp color CRT Graphics Layer 8/16/32-bpp color Hardware Cursor 64x64, 2-bpp color FIFO merge FIFO merge FIFO merge Alpha Layer 4 bits ·, 4/12-bpp color, 16-bpp transparent color alpha blend FIFO Video Alpha Layer 4 bits ·, 4/12-bpp color 8/16-bpp transparent color Video Layer 8/16/32-bpp color YUV 4:2:2 FIFO scaler FIFO scaler FIFO LUT alpha blend transparency merge LUT merge Graphics Layer 8/16/32-bpp color CRT / TV LUT Panel Multimedia SoC Vogager Family ‑ Embedded Graphics SM502 Block Diagram GPIO (64b) USB I/O Interface SSP (2x) 8b 8051 µ-controller Host CPU (Intel XScale, MIPS or Hitachi SH4) Host or PCI Digital 32b LCD Panel ZV Port SM502 Core MPEG/TV Analog Analog LCD or CRT ZV Port MPEG/TV AC97 or I²S Audio CODEC www.siliconmotion.com 32b UART (2x) or IrDA (2x), I²C SDRAM 2 to 64 MB This publication, including all photographs, illustrations and software, is protected under international copyright laws, with all rights reserved. Neither this publication, nor any of the material contained herein, may be reproduced without written consent of the manufacturer. © Copyright 2008 Silicon Motion, Inc.