A3998 Datasheet

A3998
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
Features and Benefits
Description
• 3.3/5 V switching regulator
• 1 to 2.5 V configurable linear regulator output
• Dual DMOS full bridge: drive two DC motors or
a single stepper motor
• ±1.5 A, 50 V output rating per bridge
• 4-bit microstepping capability
• Serial port control
• Configurable mixed, fast, and slow current decay
• Synchronous rectification for low power dissipation
• Internal UVLO and thermal shutdown circuitry
• Crossover-current protection
• OCP protection
Designed to provide the motor driver and power supply
requirements for printers and office automation equipment.
This integrated power IC incorporates two high current,
high performance, full bridge outputs, capable of 1.5 A at
50 V. Additionally two power supply rails are provided for
microprocessor or DSP supplies. A switching buck regulator
steps the supply down to a low voltage output that is adjustable
from 3.3 to 5 V. This voltage can be used to supply external 5 V
rails, it also feeds back into the part and supplies the integrated
linear regulator which is adjustable from 1 to 2.5 V.
The A3998 serial port provides flexible configuration for
the dual full bridge motor driver. Two full bridges can be
programmed to control one stepper motor or two DC motors.
Both bridges have integrated fixed off-time PWM control with
programmable decay mode selection.
Package: 32-contact QFN (suffix ET)
The A3998 is supplied in a low profile, 32-contact QFN,
5 × 5 mm, 0.90 mm nominal height, with exposed thermal pad
(suffix ET). The package is lead (Pb) free with 100% matte-tin
leadframe plating.
Approximate size
0.1 μF
CP1
0.22 μF
VREG
VREF
Gate Supply
Buffer
CP2
Functional Block Diagram
D/A
System
Control
Control
Logic
RS1
VBB
Serial
Port
Full Bridge
2
VBB
Monitor
D/A
OUT2B
PWM Control
Full Bridge 2
SENSE2
RS2
VBB
VOUT1
3.3 to 5V
1A
VREG
VIN
VBB
L1
VOUT1
To VREG
SW1
LDO
COUT1
220 μF
Q1
GD/VOUT2
R1
FB2
FB1
RCL2
CSN
D1
Switcher PWM Control
R3
POR
R2
RST
FB1
GND
GND
GND
CLK
100 ms
P
CAD
A3998-DS
0.22 μF
OUT2A
CLK
PMON
OUT1B
SENSE1
ENB2
STB
CLK
220 μF
OUT1A
Full Bridge
1
DATA
Controller
42 V
0.1 μF
VBB
PWM Control
Full Bridge 1
SLEEPn
ENB1
VCP
Charge Pump
FRST
R4
VOUT2
1 to 2.5 V
500 mA
COUT2
10 μF
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Selection Guide
Part Number
Packing*
A3998SETTR-T
1500 pieces per 7-in. reel
*Contact Allegro™ for additional packing options
Absolute Maximum Ratings*
Characteristic
Symbol
Load Supply Voltage
VBB
Output Current
IOUT
Sense Voltage
VSENSE
Notes
Rating
Unit
50
V
1.5
A
6
A
DC
0.52
V
tW < 1 μs
2.5
V
Motor, DC
Pulsed, tW < 1 μs
SW1 Pin Voltage
VSW
–1 to 50
V
Logic Pins Voltage Range
VIO
–0.3 to 5.5
V
VIN Pin Voltage
VIN
–0.3 to 6
V
FB Pins Voltage Range
VFB
–0.3 to 5.5
V
VREF Pin Voltage Range
VREF
–0.3 to 5.5
V
PMON, RST Pins Voltage Range
VRST
–0.3 to 5.5
V
VREG Pin Voltage Range
VREG
–0.3 to 8
V
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
S temperature range
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
Value
Unit
4-layer PCB based on JEDEC standard
30
ºC/W
Estimated, on 2-layer PCB with 1 in.2 of copper area each side
55
ºC/W
*Additional thermal information available on the Allegro website
Table of Contents
Specifications
Pin-out Diagram and Terminal List
Thermal Characteristics
Terminal List
2
2
3
Electrical Characteristics
4
Functional Description
7
Voltage Regulators
Switching Regulator
Linear Regulator
Serial Port
Serial Port Writing
Configuration Register
Motor Driver
Full Bridge Output Current Regulation
Fixed Off-Time
7
7
8
8
8
9
9
9
9
PWM Control Mode
Phase Control
Enable Logic
Fast Decay Time
PWM Blank Timer
Synchronous Rectification
Protection
Power-On Reset
Application Information
PCB Layout
Switcher
Motor Driver
Thermal Considerations
Switching Regulator Component Selection
Package Outline Drawing
9
10
10
10
10
10
11
11
16
16
16
16
16
16
19
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
32
31
30
29
28
27
26
25
GND
PMON
RSTN
VREF
FB1
FB2
GD/VOUT2
VIN
Pin-out Diagram
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PAD
CSN
VREG
NC
VCP
CP2
CP1
SW1
OUT1B
OUT2B
VBB
OUT2A
SENSE2
GND
SENSE1
OUT1A
VBB
9
10
11
12
13
14
15
16
GND
FRST
SLEEPN
CLK
DATA
STB
ENB1
ENB2
Terminal List Table
Number
Name
Function
Number
Name
Function
1,13,32
GND
Ground
18
SW1
DC to DC switch output
2
FRST
Control logic input
19
CP1
Charge pump capacitor terminal
3
SLEEPN
Control logic input, active low
20
CP2
Charge pump capacitor terminal
4
CLK
Control logic input
21
VCP
Reservoir capacitor terminal
5
DATA
Control logic input
22
NC
No connect
6
STB
Control logic input
23
VREG
7
ENB1
Control logic input
24
CSN
Current Sense/Reg select
Gate supply
8
ENB2
Control logic input
25
VIN
Logic supply/ LDO supply
9
OUT2B
DMOS full bridge 2, output B
26
GD/VOUT2
Gate drive output / VOUT2
Motor and switcher supply voltage
27
FB2
Feedback for VOUT2
DMOS full bridge 2, output A
28
FB1
Feedback for VOUT1
10, 16
VBB
11
OUT2A
12
SENSE2
Sense resistor terminal, bridge 2
29
VREF
Analog input
14
SENSE1
Sense resistor terminal, bridge 1
30
RSTN
Reset flag output
Power monitor flag output
15
OUT1A
DMOS full bridge 1, output A
31
PMON
17
OUT1B
DMOS full bridge 1, output B
–
PAD
Exposed thermal pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
ELECTRICAL CHARACTERISTICS1,2 Valid at TJ = 25°C, VBB = 50 V; unless otherwise specified
Characteristics
Load Supply Voltage Range
Bridge Output On-Resistance
VBB Pins Supply Current
VIN Pin Supply Current
Min.
Typ.3
Max.
Unit
Operating
9
–
50
V
Source driver, IOUT = –1.5 A
–
0.5
–
Ω
Sink driver, IOUT = 1.5 A
–
0.5
–
Ω
IBB
VREG regulated, IOUT = 0 mA, outputs on,
PWM = 50 kHz, Duty Cycle = 50%
–
5
10
mA
IBBS
Standby mode, regulator active
–
–
5
mA
–
5
8
mA
Symbol
VBB
RDS(on)RG
Test Conditions
IIN
Control Logic
Logic Inputs Voltage Range
Logic Input Voltage
Logic Pins Input Current (Except
ENB1,ENB2, FRST pins)
ENB1,ENB2, FRST Pins Input Current
Input Hysteresis
3
–
5.5
V
VIO(1)
VDD× 0.55
–
–
V
VIO(0)
–
–
VDD× 0.27
V
–20
<1.0
20
μA
–
66
100
μA
VIO
IIO
Operating
VIN = 0 to 5 V
IIO(1)
VIN = 3.3 V
IIO(0)
VIN = 0.8 V
VIOHYS
PWM change to source on
Propagation Delay Time
tpd
–
16
40
μA
200
–
700
mV
350
550
1000
ns
PWM change to source off
35
–
250
ns
PWM change to sink on
350
550
1000
ns
35
–
250
ns
tCOD
PWM change to sink off
300
425
1000
ns
Reset Timer
tPOR
70
100
130
ms
RSTN and PMON Pins Output
Voltage
VRST
IOUT = 1 mA
–
–
0.5
V
RSTN and PMON Pins Output
Leakage Current
Ileakage
VOUT = 5 V
–
–
1
μA
Power Monitor Threshold
VPM(th)
PMON pin, VBB falling
12
13
14
V
Power Monitor Hysteresis
VPMHYS
–
2
–
V
Crossover Delay
Supply Monitor
Protection Circuits
VIN Pin UVLO Threshold
VINUV(th)
VIN Pin UVLO Hysteresis
VINUVHYS
VBB Pins UVLO Threshold
VBBUV(th)
VBB Pins UVLO Hysteresis
VBBUVHYS
VIN rising
VBB rising
2.8
3
V
100
–
mV
6.6
7.1
7.6
V
0.7
0.9
1.1
V
FB1 Pin UVLO Threshold
VFBUV(th)
698
735
772
mV
FB1 Pin UVLO Hysteresis
VFBUVHYS
–
100
–
mV
TJSD
155
165
175
°C
TJSDHYS
–
20
–
°C
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VFB falling
–
–
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at TJ = 25°C, VBB = 50 V; unless otherwise specified
Characteristics
Min.
Typ.3
Max.
Unit
Does not include Cycle Skipping mode
(V = 9 to 50 V, I = 100 mA to 1 A)
0.98
1
1.02
V
Cycle Skipping mode
0.95
1
1.05
V
–400
–
100
nA
5
10
15
ms
Symbol
Test Conditions
DC to DC Converter
Feedback Voltage Regulation4
VFB1
Feedback Input Bias Current
IFB1
Soft Start Duration
tSS
Current Limit
Fixed Off-time
Buck Switch On-Resistance
VBB = 9 V
ICLREG
VFB > 400 mV
1.5
–
2.7
A
ICLFB
VFB < 400 mV
.5
–
1.2
A
VOUT
–
4
–
μs
I = 1 A, TJ = 25°C
–
0.6
–
Ω
tOFF
RDS(on)SW
Low Drop-Out Regulator
Feedback Voltage
VFB2
I = 0 to 500 mA
.98
1
1.02
V
Internal Current Limit
ICL2
CSN connected to VREG
525
–
750
mA
External Current Limit Threshold
VCL2
CSN connected to sense resistor
VIN Pin Voltage Range
VIN
180
200
220
mV
VOUT+0.6
–
5.5
V
0.0
–
2.6
V
Control Circuit
VREF Pin Input Voltage Range
Reference Input Current
Transconductance Error5
Internal Oscillator Frequency
VREFRNG
IREF
GmERR
fosc
Operating
–
–
±1
μA
VREF = 2.0, DAC = 15
VREF = 2.0, VBB = 0 to 50 V
–4
–
4
%
VREF = 2.0, DAC = 3
–10
–
10
%
3.4
4
4.6
MHz
1Negative
current is defined as coming out of (sourcing) the specified device pin.
limits are tested at a single temperature and assured over the range 0°C to 125°C by design and characterization.
3Typical data is for design information only.
4Average value of V
OUT relative to target.
5Gm
ERR =[(VREF × Current_Ratio / 5) – VSENSE] / (VREF × Current_Ratio / 5).
2Specified
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Normal Power-up Timing Diagram
VBB
Charge pump
OK (internal)
VOUT1
tSS
VOUT2
tPOR
RST
PMON
RST Function Timing with FRST Input
FRST
tPOR
RST
Overcurrent Protection (OCP) Timing Diagram
Outputs High-Z
VOUTxA
IOCP
IOUTx
VENBx
OCP Delay
OCP Fault Latch
tOCP
tOCP
SLEEPN
Motor Short
Motor driver outputs
disabled and serial
port reset
OCP fault latch clears
at SLEEPN edge
Normal DC
Motor Capacitance
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Functional Description
in the inductor from pumping the supply voltage up, the A3998
can skip PWM cycles. Cycle skipping mode can be activated any
time there is discontinuous current in the inductor.
Voltage Regulators
Switching Regulator
An adjustable fixed off-time, peak current controlled buck
regulator is used to provide external voltage to microprocessors
or DSPs. The switcher output is fed back into the device and
provides low voltage logic supply for the IC, improving overall
efficiency. The regulator can operate in both continuous and
discontinuous modes. An internal blanking circuit filters out transients due to the reverse recovery of the external clamp diode.
Soft Start An internal ramp generator and counter allow the out-
put to ramp-up slowly. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any DC load at start-up.
Internally, the ramp is set to 10 ms nominal rise time.
Shorted Load The regulator incorporates an overcurrent limit
to handle shorted load conditions at the regulator output. For
low output voltages at power-up, and in the case of a short, the
off-time is extended to prevent loss of control of the current limit
due to the minimum on-time of the switcher.
The switching regulator fixed off-time of approximately 4 μs is
appropriate for the VOUT1 range from 3.3 to 5 V.
Light Load Regulation The switching regulator enters Cycle
Skipping mode at light load conditions to maintain reasonable
voltage regulation. As the output current decreases, there remains
some energy that is stored during the power switch minimum
on-time. The stored energy is transferred to the output capacitor and the output voltage begins to increase. To prevent energy
The overcurrent limit has a foldback feature to reduce the current
limit when the output is overloaded (see figure 2). The voltage at
the feedback pin (FB) is monitored to determine which current
limit level to use. As the feedback voltage rises above approximately 400 mV, the foldback circuit is disabled.
L1
SW1
VBB
VOUT1
D1
ES R
R1
VCP
Monitor
ENABLE
FB1
VCP
Switch PWM
Control
R2
t OFF
VBB UVLO
TSD
COUT1
220 μF/35 V
Clamp
-
Error
Idemand
+
Ipeak
+
Comp
ENABLE
Internal
Oscillator
OR
GATE REG
Clock
Counter
Soft Start
Ramp Generation
1V
Figure 1. Implementation of switcher circuit; see table 3 for external component specifications.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Linear Regulator
An adjustable voltage rail from 1 to 2.5 V is integrated into the
device. The switcher output is fed back into the device through
the VIN pin and supplies the integrated linear pass element. To
reduce power dissipation in the A3998, the linear regulator can be
configured to drive the gate of an external N-channel FET. Using
the external FET significantly reduces power dissipation in the IC
and can allow the device to operate in high ambient temperature
environments.
The regulator has two configurations: Internal mode and External
mode. External mode is used to minimize power dissipation. In
External mode current is limited by selection of the sense resistor,
RCL. Internal mode is selected by connecting pin CSN to the
Internal Configuration When the internal pass element is configured the internal current limit is fixed at ICL2 . The regulator
has overcurrent protection with foldback. Figure 3 shows the I•V
characteristic of the linear regulator.
External Configuration When the external pass element is
configured the current is adjustable by selecting the value of a
current limit resistor RCL2 . When the voltage across the resistor
equals VCL2 the regulator enters current limit and will fold back
according to the waveform shown in figure 3. To calculate the
current limit use the formula below:
VCL2 / ILIM = RCL
6.0
(1)
where ILIM is the target current limit.
VVOUT1 = 5 V
5.0
VOUT1 Voltage (V)
VREG pin. Both internal and external configurations are current
limited.
Serial Port
4.0
VVOUT1 = 3.3 V
Serial Port Writing
The serial port is accessed for writing only, using the STB
(Strobe), CLK (clock), DATA and SLEEPN pins. Addressing
consists of word selection bits (D15:D14) followed by the bit
values for each parameter in the word. Timing requirements are
shown in figure 4.
3.0
2.0
1.0
0.0
0.0
VIN = 42 V
0.5
1.0
1.5
2.0
2.5
VOUT1 Current (A)
Figure 2. Switcher current limit with foldback
2.0
1.8
VVOUT2 = 1.8 V
VOUT2 Voltage (V)
1.6
1.4
VVOUT2 = 1.5 V
1.2
1.0
VVOUT2 = 1.0 V
0.8
0.6
0.4
VIN = 5 V
0.2
0.0
0.0
0.1
0.2
0.3
0.4
VOUT2 Current (A)
0.5
0.6
0.7
0.8
Figure 3. Linear current limit with foldback
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Configuration Register
A configuration register supporting four 16-bit words can be set
using the serial port.
Five bits (word 0/1, D6:D2) are available for each full bridge
to adjust the fixed off-time, tOFF , when Internal PWM current
control mode is selected.
The Configuration register is volatile memory accessed through
the serial port. The bit descriptions are shown in table 1. At a
power-on reset (POR), the bits are set to their default values, all
zeros with the exception of the MSB of the fixed off-time parameters, which are set to one.
The off-time is defined by the following equation:
tOFF = (1 + N) × TOSC × 8 – TOSC
(3)
where N is the word value, from 0 to 31, and TOSC is the period
of the internal oscillator.
Motor Driver
For example, given the internal oscillator frequency, fOSC , of
4 MHz (typ) (TOSC = 250 ns), the fixed off-time is adjustable
from 2 to 64 μs in increments of 2 μs.
Full Bridge Output Current Regulation
Maximum load current is regulated by an Internal PWM mode,
fixed off-time current control circuit. When the outputs of the
DMOS full bridges are turned on, current increases in the motor
winding until it reaches a value given by:
PWM Control Mode
The selection of Internal or External PWM control mode for each
full bridge is made in the Configuration register.
ITRIP = VREF × Current Ratio / (5 × RS)
(2)
where RS is the value of the sense resistor RS, and the Current
Ratio is as shown in table 2.
At the trip point, the sense comparator resets the source enable
latch, turning off the source driver. At this point, load inductance
causes the current to recirculate for the serial port programmed
fixed off-time period. The current path during recirculation is
determined by the configuration of slow/mixed decay mode and
the synchronous rectification control bits.
Fixed Off-Time
The PWM timer is programmable via the serial port to provide
fixed off-time PWM signals to the A3998 internal control block.
D
C
STB
• Selection of Internal control mode (word 2, D0 and D7) sets
the Internal PWM Decay Mode (Mixed or Slow), and allows
the configuration of Fixed Off-Time and Fast Decay Time. In
Mixed Decay mode, during the first portion of the off-time
period, the A3998 operates in Fast Decay mode, until the Fast
Decay time count is reached. The rest of the fixed off-time period the A3998 operates in Slow Decay mode. If the Fast Decay
Time duration is longer than the Fixed Off-Time duration, the
device effectively operates in Fast Decay mode throughout the
period.
• Selection of External control mode (word 2, D1 and D8) sets
the External PWM Decay Mode (Fast or Slow). In this mode, a
chopping signal on the Enable pins (ENBx) are used to provide
external PWM current control.
F
E
CLK
MSB
DATA
A
LSB - D0
G
B
SLEEPN
H
A.
B.
C.
D.
Minimum Data Setup Time
Minimum Data Hold Time
Minimum Setup Strobe to Clock Rising Edge
Minimum Clock High Pulse Width
15 ns
10 ns
50 ns
50 ns
E.
F.
G.
H.
Minimum Clock Low Pulse Width
50 ns
Minimum Setup Clock Rising Edge to Strobe 50 ns
Minimum Strobe Pulse Width
50 ns
Minimum Sleep to Clock Setup Time
100 ns
Figure 4. Serial Port Timing Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Phase Control
This setting sets the relative states of the full-bridge outputs. This
determines if the device operates in the forward or reverse (relative) direction:
Serial Port
Configuration Bit
(Word 2)
Blank Time Two bits (word 0/1, D1:D0) are available for each
full bridge to set the current sense comparator blank time when
any output driver is switched on. The settings are according to the
following table (TOSC is the period of the internal oscillator):
Serial Port Configuration Bit
(Word 0/1)
Phase
Blank Time
D2/D9
State
OUTA
OUTB
D1
D0
0
Reverse
Low
High
0
0
1
Forward
High
Low
0
1
6 × TOSC
1
0
12 × TOSC
1
1
24 × TOSC
Enable Logic
The ENB1 and ENB2 input terminals are provided for external
PWM control of the two full bridges. When ENBx is set to logic
high, output on the corresponding full bridge is enabled. When
set to logic low, the bridge output is chopped.
Fast Decay Time
Four bits (word 0/1, D10:D7) are available for each full bridge to
set the Fast Decay portion, tFD , of the fixed off-time when Internal PWM control, Mixed Decay mode is selected.
The Fast Decay portion is defined by:
tFD = (1 + N) × TOSC × 8 – TOSC
(4)
where N is the word value, from 0 to 15.
For example, given the internal oscillator frequency, fOSC , of
4 MHz (typ) (TOSC = 250 ns), the fixed off-time is adjustable
from 2 to 32 μs in increments of 2 μs. For tFD > tOFF , the device
effectively operates in Fast Decay mode.
PWM Blank Timer
When a source driver turns on, a current spike occurs due to the
reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To
prevent this current spike from erroneously resetting the source
enable latch, the sense comparator is blanked.
The programmable blanking function is enabled while the blank
timer runs, which is after the off-time counter expires. When the
Enable (ENBx) signal is chopped, or the Phase setting in the the
Configuration register is changed, a PWM-off cycle is initiated
and the blank timer is reset.
4 × TOSC
For example, given the internal oscillator frequency, fOSC , of
4 MHz (typ) (TOSC = 250 ns), the blank time is adjustable from
1 to 6 μs.
Synchronous Rectification
When a PWM-off cycle is triggered, either by an Enable chop
command or an Internal PWM control mode Fixed Off-Time
cycle, the load current recirculates according to the decay mode
selected by the Configuration register settings. After a short
crossover delay, the synchronous rectification feature turns-on the
appropriate MOSFET (or pair of MOSFETs, for the Mixed Decay
portion of the off-time) during the current decay and effectively
shorts-out the body diodes with the low RDS(on) driver. This lowers power dissipation significantly and can eliminate the requirement for external Schottky diodes.
Synchronous rectification can be configured in active mode or
passive mode via the serial port (word 0/1, D11):
• Active mode prevents reversal of load current by turning-off
synchronous rectification when a zero current level is detected.
• Passive mode allows reversal of current, but turns-off synchronous rectification if the load current inversion ramps up to the
ITRIP current limit (see equation 1).
SLEEPN Pin Active low input signal to reset serial port Configu-
ration register and enter Standby mode. During Standby mode,
the regulators can still operate.
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10
A3998
Protection
Switching Regulator The buck switch is disabled under the fol-
lowing fault conditions:
• VBB < VBBUV(th)
• VCP < VBB + 5 V
• Thermal shutdown fault
Thermal Protection A thermal shutdown circuit turns-off all
drivers and disables the switching regulator in the event of a fault
due to excessive junction temperature. The serial port Configuration register is not reset.
Shutdown occurs when the junction temperature reaches TJSD ,
165°C (typ). Thermal shutdown has a hysteresis, TJSDHYS, of
approximately 20°C (typ). The outputs of the device remain disabled until the fault condition is removed.
PMON Pin Open drain output, logic high indicates VBB is above
the UVLO threshold.
Undervoltage Lockout At power-up, and in the event of low
VIN , the UVLO circuit disables the drivers and the serial port
Configuration register is reset to the default, POR state.
OCP When an overcurrent event is detected, the serial port
Configuration register is reset to the default (POR) state. This
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
fault is latched and can only be reset by cycling the power to the
A3998 ( power-on reset, POR) or by cycling Standby mode (via
the SLEEPN pin).
Note: An overcurrent fault event will not be generated during a
shorted load condition if the blank time is programmed shorter
than the tOCP . In this case, the overcurrent protection is still
active, however, the internal current control circuit will operate as
normal and terminate the source driver on-state upon completion
of the blank time, before the OCP can trip the fault line and reset
the serial port.
Power-On Reset
FRST Pin Active high input signal forces reset (POR).
RSTN Pin An open drain output, RSTN will be low if either of
following conditions are true:
• VFB1 < VFBUV(th)
• FRST high
If neither of the conditions are true, there will be a 100 ms delay
before RSTN goes high. (See RST Function with FRST Input
timing diagram.)
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11
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Table 1. Configuration Register Bit Map
Bit #
Function
Reset (POR) Value
Word 0
D0
Bridge 1 Blank Time LSB
0
D1
Bridge 1 Blank Time MSB
0
D2
Bridge 1 Off Time LSB
0
D3
Bridge 1 Off Time Bit 1
0
D4
Bridge 1 Off Time Bit 2
0
D5
Bridge 1 Off Time Bit 3
0
D6
Bridge 1 Off Time MSB
1
D7
Bridge 1 Fast Decay LSB
0
D8
Bridge 1 Fast Decay Bit 1
0
D9
Bridge 1 Fast Decay Bit 2
0
D10
Bridge 1 Fast Decay MSB
0
D11
Bridge 1 Synchronous Rectification Control:
0 = Active
1 = Passive
0
D12
Unused
0
D13
Unused
–
D14
Word Select 0 = 0
–
D15
Word Select 1 = 0
–
D0
Bridge 2 Blank Time LSB
0
D1
Bridge 2 Blank Time MSB
0
D2
Bridge 2 Off Time LSB
0
D3
Bridge 2 Off Time Bit 1
0
D4
Bridge 2 Off Time Bit 2
0
D5
Bridge 2 Off Time Bit 3
0
D6
Bridge 2 Off Time MSB
1
D7
Bridge 2 Fast Decay LSB
0
D8
Bridge 2 Fast Decay Bit 1
0
Word 1
D9
Bridge 2 Fast Decay Bit2
0
D10
Bridge 2 Fast Decay MSB
0
D11
Bridge 2 Synchronous Rectification Control:
0 = Active
1 = Passive
0
D12
Unused
0
D13
Unused
–
D14
Word Select 0 = 1
–
D15
Word Select 1 = 0
–
Continued on the next page…
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12
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Table 1. Configuration Register Bit Map (continued)
Bit #
Function
Reset (POR) Value
Word 2
D0
Bridge 2 Internal PWM Mode:
0 = Mixed decay mode
1 = Slow decay mode
0
D1
Bridge 2 External PWM Mode (ENB2 chopping):
0 = Fast decay mode
1 = Slow decay mode
0
D2
Bridge 2 Phase
0
D3
Bridge 2 DAC LSB (Current Ratio bit)
0
D4
Bridge 2 DAC Bit 2 (Current Ratio bit)
0
D5
Bridge 2 DAC Bit 3 (Current Ratio bit)
0
D6
Bridge 2 DAC Bit 4 (Current Ratio bit)
0
D7
Bridge 1 Internal PWM Mode:
0 = Mixed decay mode
1 = Slow decay mode
0
D8
Bridge 1 External PWM Mode (ENB1 chopping):
0 = Fast decay mode
1 = Slow decay mode
0
D9
Bridge 1 Phase
0
D10
Bridge 1 DAC LSB (Current Ratio bit)
0
D11
Bridge 1 DAC Bit 2 (Current Ratio bit)
0
D12
Bridge 1 DAC Bit 3 (Current Ratio bit)
0
D13
Bridge 1 DAC Bit 4 (Current Ratio bit)
0
D14
Word Select 0 = 0
–
D15
Word Select 1 = 1
–
Continued on the next page…
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13
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Table 1. Configuration Register Bit Map (continued)
Bit #
Function
Reset (POR) Value
Word 3
D0
Thermal Monitor:
0 = Normal function
1 = RSTN = thermal analog output, V = K × TJ
0
D1
Charge Pump:
0 = Normal Operation
1 = Disable Charge Pump
0
D2
Reserved For Test
0
D3
Reserved For Test
0
D4
Reserved For Test
0
D5
Reserved For Test
0
D6
Reserved For Test
0
D7
Reserved For Test
0
D8
Reserved For Test
0
D9
Reserved For Test
0
D10
Reserved For Test
0
D11
Reserved For Test
0
D12
Reserved For Test
0
D13
Reserved For Test
0
D14
Word Select 0 = 1
–
D15
Word Select 1 = 1
–
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Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Table 2. Current Ratio Configuration*
DAC Bit 4
DAC Bit 3
DAC Bit 2
DAC LSB
Current Ratio
(%)
1
1
1
1
100.0
1
1
1
0
95.65
1
1
0
1
91.30
1
1
0
0
86.95
1
0
1
1
82.61
1
0
1
0
78.26
1
0
0
1
73.91
1
0
0
0
69.56
0
1
1
1
60.87
0
1
1
0
52.17
0
1
0
1
43.48
0
1
0
0
34.78
0
0
1
1
26.08
0
0
1
0
17.39
0
0
0
1
0
0
0
0
0
Disabled
*Internal PWM control mode selected
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15
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Application Information
PCB Layout
Switcher
The board layout has a significant impact on the performance of
the device. It is important to isolate high current ground returns,
in order to minimize ground bounce that could produce reference
errors in the device. The method used to isolate power ground
from noise sensitive circuitry is a star ground. This approach
makes sure the high current components such as the input capacitor, output capacitor, and diode have very low impedance paths
to each other. Figure 5 illustrates the technique. The ground from
each of the components should be very close to each other and
be connected on the same surface as the components. Internal
ground planes should not be used for the star ground connection, because vias add impedance to the current path. In order to
further reduce noise effects on the PCB, noise sensitive traces
should not be connected to internal ground planes.
The feedback network from the switcher output should have an
independent ground trace that goes directly to the exposed pad
underneath the device. The exposed pad should be connected to
internal ground planes and to any exposed copper used for heat
dissipation. If the grounds from the device also are connected
directly to the exposed pad, the ground reference from the feedback network will be less susceptible to noise injection or ground
bounce.
L
Q1
CIN
D
COUT
RLOAD
To reduce radiated emissions from the high frequency switching
nodes it is important to have an internal ground plane directly
under the LX node. The plane should not be broken directly
under the switching path because the lowest impedance path for
radiated emissions is back to the star ground using the ground
plane directly under the signal trace. If another trace does break
the return path, the energy will have to find another path, which
is through radiated emissions or through stray eddy currents.
Motor Driver
In order to use PWM current control, a low-value resistor is
placed between the LSSx pin and ground for current sensing
purposes. To minimize ground-trace IR drops in sensing the
output current level, the current sensing resistor should have an
independent ground return to the star ground point. This trace
should be as short as possible. For low-value sense resistors, the
IR drops in the PCB can be significant, and should be taken into
account. When selecting a value for the sense resistor be sure not
to exceed the maximum voltage on the SENSEx pin of ±500 mV
at maximum load. During overcurrent events, this rating may be
exceeded for short durations.
Thermal Considerations
The PCB should have a thick ground plane. For optimum
electrical and thermal performance, the A3998 must be soldered
directly onto the board. On the underside of the A3998 package is
an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad must be soldered directly to an exposed
surface on the PCB in order to achieve optimal thermal conduction. Thermal vias are used to transfer heat to other layers of the
PCB. The load supply pin, VBB, should be decoupled with an
electrolytic capacitor (typically 100 μF) in parallel with a lower
valued ceramic capacitor placed as close as practicable to the
device
Switching Regulator Component Selection
External component recommended values are provided in table 3.
Current path (on-cycle )
Current path (off-cycle )
Star Ground
VOUT1 The regulator requires an external clamping diode, D1,
inductor, L1, and filter capacitor, COUT1 (see figure 1).
The output voltage is determined by an external resistive voltage
divider, according to the following formula:
Figure 5. Star Ground Connection
VOUT1 = VFB1 × (1 + R1 / R2)
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(5)
16
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
PCB Layout Diagram
COUT2
VOUT2
GND
GND
VOUT1
Q1
L1
R4
R3
R1
R2
RCL2
U1
CVREG
GND
COUT1
CVCP
CCP
GND
D1
CVBB1
CVBB2
VBB
RS2
RS1
GND
OUT2B OUT2A
R4
R2
OUT1A
OUT1B
R3
VOUT2
COUT2
R1
Q1
VIN
FB2
FB1
GD/VOUT2
FRST
VREF
RSTN
GND
GND
PMON
VOUT1
VREG
A3998
SLEEPN
CLK
RCL2
CSN
NC
CP2
VBB
OUT1A
SENSE1
GND
SENSE2
OUT2A
SW1
VBB
CP1
ENB1
OUT2B
STB
ENB2
L1
CCP
OUT2B
OUT2A
Trace (2 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Thermal Vias
D1
GND
OUT1B
CVBB2
RS2
PCB
COUT1
CVCP
Solder
Signal (1 oz.)
CVREG
VCP
PAD
DATA
A3998
CVBB1
VBB
RS1
OUT1A
OUT1B
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17
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
The total resistance from VOUT1 to FB1 to GND should be less
than 10 kΩ.
and
D1 The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
than the maximum input voltage expected during any operating
condition. The duty cycle for high input voltages can be very
close to 100%.
Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total
maximum current available that can be drawn from the switching
regulator. The maximum total current available is:
VL(ON) = VBB – Iav × RDS(on) – Iav × RL – VOUT1
ILOAD(max) = ICL(min) – IR / 2
L1 The inductor must be rated to handle the total load current
(11)
Where ICL(min) is from the Electrical Characteristics table.
and the value chosen must keep the ripple current to a reasonable
value. The ripple current, IR , can be calculated by:
COUT1 The output capacitor main consideration is voltage ripple
IR = VL(OFF) × (tOFF / L)
(6)
VL(OFF) = VOUT1 + Vf + Iav × RL
(7)
where
(10)
on the output. For electrolytic output capacitors, a low ESR type
is recommended. The peak to peak output ripple is simply:
IR(pp) = IR × ESR
(12)
fPWM = 1 / ( tON + tOFF )
(8)
Note that the ripple current can be decreased by increasing the
inductor value. The minimum voltage rating of the capacitor is
10 V, however, because ESR decreases with voltage, the most
cost effective choice may be a higher rated voltage.
tON = IR × L / VL(ON)
(9)
VOUT2 This output requires a 10 μF ceramic output capacitor,
The switching frequency can then be estimated by:
where
COUT2.
Table 3. Recommended Components
Configuration
Output
fPWM
Component
Symbol
Description
Representative Component
VOUT1x
L1
COUT1
5V/1A
220 kHz
230 kHz
3BSumida RCH1216BNP-680K
220 μF / 25 V, ESR = 72 mΩ
Rubycon ZL 25ZL220M8x11.5
D1
60 V / 3 A Schottky diode
NSQ03A06
R1
2 kΩ
R2
499 Ω
L1
68 μH
COUT1
3.3V/1A
68 μH
4BSumida RCH1216BNP-680K
220 μF / 25 V, ESR = 72 mΩ
Rubycon ZL 25ZL220M8x11.5
D1
60 V / 3 A Schottky diode
Vishay SS36
R1
2 kΩ
R2
866 Ω
Q1
External MOSFET - Cgs < 1000 pF
RSx
Sense resistor
VOUT2x
COUT2
10 μF /10 V X5R
R3, R4
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18
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
Package ET, 32-Pin QFN
0.30
5.00 ±0.15
32
32
1
2
0.50
1.00
1
2
A
5.00 ±0.15
3.40
5.00
1
33X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
0.90 ±0.10
0.50 BSC
3.40
C
5.00
C
PCB Layout Reference View
Concept Drawing For Reference Only; not for tooling use
(reference JEDEC MO-220VHHD-6)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.50±0.05
3.40
B
2
1
32
3.40
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 QFN50P500X500X100-33V6M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
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19
A3998
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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