X5001 ® Data Sheet April 6, 2005 CPU Supervisor FN8125.0 DESCRIPTION FEATURES • 200ms power-on reset delay • Low VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Selectable nonvolatile watchdog timer —0.2, 0.6, 1.4 seconds —Off selection —Select settings through software • Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off • 2.7V to 5.5V operation • SPI mode 0 interface • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Watchdog change latch • High reliability • Available packages —8-lead TSSOP —8-lead SOIC —8 pin PDIP This device combines three popular functions, Poweron Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The watchdog timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user’s system is protected from low voltage conditions by the device’s low VCC detection circuitry. When VCC falls below the minimum VCC trip point, the system is reset. RESET is asserted until VCC returns to proper operating levels and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The device utilizes Intersil’s proprietary Direct Write™ cell for the watchdog timer control bits and the VTRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. BLOCK DIAGRAM Watchdog Transition Detector SI SO RESET Data Register Reset & Watchdog Timebase Command SCK Watchdog Timer Decode & Control CS/WDI Logic Power-on/ Low Voltage REset VCC + VTRIP 1 Generation - CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X5001 PIN CONFIGURATION 8-Lead TSSOP 8-Lead SOIC/PDIP RESET 1 8 SCK VCC 2 7 SI CS/WDI 3 6 SO 4 5 X5001 CS/WDI 1 8 VCC SO 2 7 RESET VSS VPE 3 6 SCK VPE VSS 4 5 SI X5001 PIN DESCRIPTION Pin (SOIC/PDIP) Pin TSSOP Name Function 1 1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 2 2 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 5 8 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 6 9 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or watchdog bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 3 6 VPE VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last valid programmed level. To readjust the VTRIP level, requires that the VPE pin be pulled to a high voltage (15-18V). 4 7 VSS Ground 8 14 VCC Supply Voltage 7 13 RESET 3-5,10-12 NC 2 Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET goes active if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS/WDI will reset the watchdog timer. RESET goes active on power-up at 1V and remains active for 200ms after the power supply stabilizes. No internal connections FN8125.0 April 6, 2005 X5001 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5001 activates a poweron reset circuit. This circuit goes active at 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5001 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until Vcc returns and exceeds VTRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the watchdog register determine the watchdog timer period. Vcc Threshold Reset Procedure The X5001 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5001 threshold may be adjusted. The procedure is described below, and requires the application of a high voltage control signal. 3 Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WPE pin to the programming voltage VP. Then a VTRIP programming command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 01h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply greater than 3V to the VCC pin and tie the WPE pin to the programming voltage VP. Then a VTRIP command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 03h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation. FN8125.0 April 6, 2005 X5001 Figure 1. Sample VTRIP Reset Circuit 4.7K VP Adjust VTRIP Adj. Run 1 8 2 3 7 X5001 6 4 5 RESET µC SCK SI SO CS Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP value) VPE = 15-18V VPE CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 SCK 16 Bits 16 Bits SI 03h 0001h 02h 0001h Figure 3. Reset VTRIP Level Sequence (VCC > 3V) VPE = 15-18V VPE CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 SCK 16 BITS Bits 16 Bits SI 03h 0001h 4 02h 0003h FN8125.0 April 6, 2005 X5001 Figure 4. VTRIP Programming Sequence VTRIP Programming Execute Reset VTRIP Sequence Set VCC = VCC Applied = Desired VTRIP New VCC Applied = Old VCC Applied + Error Execute Set VTRIP Sequence New VCC Applied = Old VCC Applied - Error Apply 5V to VCC Execute Reset VTRIP Sequence Decrement VCC (VCC = VCC - 50mV) NO RESET pin goes active? YES Error < 0 Measured VTRIP Desired VTRIP Error > 0 Error = 0 DONE SPI INTERFACE The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the CS/WDI line and asserts RESET output if there is no activity within user selectable time out period. The device also monitors the VCC supply and asserts the RESET if VCC falls below a preset minimum (VTRIP). The device contains an 8-bit 5 watchdog timer register to control the watchdog time out period. The current settings are accessed via the SI and SO pins. All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. FN8125.0 April 6, 2005 X5001 Read Watchdog Timer Register Operation Watchdog Timer Register 7 6 5 4 3 2 1 0 0 0 0 WD1 WD0 0 0 0 If there is not a nonvolatile write in progress, the read watchdog timer instruction returns the setting of the watchdog timer control bits. The other bits are reserved and will return’0’ when read. See Figure 3. Watchdog Timer Control Bits The watchdog timer control bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the set watchdog timer (SWDT) instruction. Watchdog Control Bits WD1 Watchdog Time Out (Typical) WD0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled If a nonvolatile write is in progress, the read watchdog timer register Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, a separate read watchdog timer instruction should be used to determine the current status of the watchdog control bits. RESET Operation The RESET (X5001) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit. The RESET output is an open drain output and requires a pull up resistor. Write Watchdog Register Operation Changing the watchdog timer register is a two step process. First, the change must be enabled with by setting the watchdog change latch (see below). This instruction is followed by the set watchdog timer (SWDT) instruction, which includes the data to be written (Figure 5). Data bits 3 and 4 contain the watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be “0”. Watchdog Change Latch The watchdog change latch must be SET before a Write watchdog timer operation is initiated. The Enable Watchdog Change (EWDC) instruction will set the latch and the Disable Watchdog Change (DWDC) instruction will reset the latch (See Figure 6) This latch is automatically reset upon a power-up condition and after the completion of a valid nonvolatile write cycle. Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The watchdog change latch is reset. – The RESET signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: – A EWDC instruction must be issued to enable a change to the watchdog timeout setting. – CS must come HIGH at the proper clock count in order to implement the requested changes to the watchdog timeout setting. Table 1. Instruction Set Definition Instruction Format Note: Instruction Name and Operation 0000 0110 EWDC: Enable Watchdog Change Operation 0000 0100 DWDC: Disable Watchdog Change Operation 0000 0001 SWDT: Set Watchdog Timer control bits: Instruction followed by contents of register: 000(WD1) (WD0)000 See Watchdog Timer Settings and Figure 7 0000 0101 RWDT: Read Watchdog Timer control bits Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first. 6 FN8125.0 April 6, 2005 X5001 Figure 5. Read Watchdog Timer Setting CS 0 1 2 3 4 5 6 7 ... SCK RWDT Instruction ... SI W D 1 SO W D 0 ... Figure 6. Enable Watchdog Change/Disable Watchdog Change Sequence CS 0 1 2 3 4 5 6 7 SCK Instruction (1 Byte) SI High Impedance SO Figure 7. Write Watchdog Timer Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Data Byte Instruction 6 SI SO High Impedance 7 5 4 3 W W D D 1 0 FN8125.0 April 6, 2005 X5001 Figure 8. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation) CS 0 1 2 3 4 5 6 7 SCK RWDT Instruction SI Nonvolatile Write in Progress SO SO HIGH During 1st Bit While in the Nonvolatile Write Cycle Figure 9. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation) CS 0 1 2 3 4 5 6 7 SCK RWDT Instruction SI Nonvolatile Write in Progress SO SO HIGH During Nonvolatile Write Cycle 8 FN8125.0 April 6, 2005 X5001 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Min. 0°C Max. Voltage Option -1.8 -2.7 or -2.7A -4.5 or -4.5A +70°C Note: Supply Voltage Limits 1.8V to 3.6V 2.7V to 5.5V 4.5V to 5.5V PT= Package, Temperature D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Typ Max. 5 Unit mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open 0.4 mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open VCC standby current WDT=OFF 1 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB2 VCC standby current WDT=ON 50 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB3 VCC standby current WDT=ON 20 µA CS = VCC, VIN = VSS or VCC, VCC = 3.6V ILI Input leakage current 0.1 10 µA VIN = VSS to VCC ILO Output leakage current 0.1 10 µA VOUT = VSS to VCC V ICC1 VCC write current (Active) ICC2 VCC read current (Active) ISB1 Min. Test Conditions VIL(1) VIH(1) Input LOW voltage -0.5 VCC x 0.3 Input HIGH voltage VCC x 0.7 VCC + 0.5 V VOL1 Output LOW voltage 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < VCC < 3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V VCC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH voltage VCC-0.8 V VCC > 3.3V, IOH = -1.0mA VOH2 Output HIGH voltage VCC-0.4 V 2V < VCC ≤ 3.3V, IOH = -0.4mA VOH3 Output HIGH voltage VCC-0.2 V VCC ≤ 2V, IOH = -0.25mA VOLRS Reset output LOW voltage V IOL = 1mA 9 0.4 FN8125.0 April 6, 2005 X5001 POWER-UP TIMING Symbol tPUR (2) (2) tPUW Parameter Min. Max. Unit Power-up to read operation 1 ms Power-up to write operation 5 ms Max. Unit Conditions Output capacitance (SO, RESET) 8 pF VOUT = 0V Input capacitance (SCK, SI, CS) 6 pF VIN = 0V CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol COUT(2) CIN (2) Test Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 3V A.C. TEST CONDITIONS 5V 3.3kΩ 1.64kΩ Output Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x0.5 RESET 1.64kΩ 100pF 30pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 1.8V-3.6V SymboL Parameter 2.7V-5.5V Min. Max. 0 1 Min. Max. Unit 0 2 MHz fSCK Clock frequency tCYC Cycle time 1000 500 ns tLEAD CS lead time 400 200 ns tLAG CS lag time 400 200 ns tWH Clock HIGH time 400 200 ns tWL Clock LOW time 400 200 ns tSU Data setup time 100 50 ns tH Data hold time 100 50 ns tRI(3) tFI(3) Input rise time 2 2 µs Input fall time 2 2 µs tCS tWC (4) CS deselect time Write cycle time 10 250 150 10 ns 10 ms FN8125.0 April 6, 2005 X5001 Data Output Timing 1.8V-3.6V Symbol Parameter 2.7V-5.5V Min. Max. Min. Max. Unit 0 1 0 2 MHz fSCK Clock frequency tDIS Output disable time 400 200 ns Output valid from clock low 400 200 ns tV tHO 0 0 ns Output rise time 300 150 ns (3) Output fall time 300 150 ns tRO tFO Output hold time (3) Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Figure 10. Data Output Timing CS tCYC tWH tLAG SCK tV SO SI tHO MSB Out tWL tDIS MSB–1 Out LSB Out ADDR LSB IN Figure 11. Data Input Timing tCS CS tLEAD tLAG SCK tSU SI SO tH MSB In tRI tFI LSB In High Impedance 11 FN8125.0 April 6, 2005 X5001 SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Figure 12. Power-Up and Power-Down Timing VTRIP VTRIP VCC tPURST 0 Volts tF tPURST tRPD tR RESET (X5001) RESET Output Timing Symbol Min. Typ. Max. Unit VTRIP Reset trip point voltage, X5001PT-4.5A Reset trip point voltage, X5001PT-4.5 Reset trip point voltage, X5001PT-2.7A Reset trip point voltage, X5001PT-2.7 Reset trip point voltage, X5001PT-1.8 4.50 4.25 2.85 2.55 1.70 4.63 4.38 2.92 2.63 1.75 4.75 4.50 3.00 2.70 1.80 V tPURST Power-up reset timeout 100 200 280 ms tRPD(5) VCC detect to reset/output 500 ns tF(5) VCC fall time 0.1 ns tR(5) VCC rise time 0.1 ns 1 V VRVALID Note: Parameter Reset valid VCC (5) This parameter is periodically sampled and not 100% tested. PT = Package, Temperature 12 FN8125.0 April 6, 2005 X5001 Figure 13. CS vs. RESET Timing CS tCST RESET tWDO tRST tWDO tRST RESET Output Timing Symbol Parameter Min. Typ. Max. Unit Watchdog timeout period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec tCST CS pulse width to reset the watchdog 400 tRST Reset Timeout 100 tWDO ns 200 300 ms VTRIP Programming Timing Diagram VCC (VTRIP) VTRIP tTSU tTHD VP VPE tVPS tVPH tPCS CS tVPO tRP SCK SI 03h 13 0001h 02h 0001h or 0003h FN8125.0 April 6, 2005 X5001 VTRIP Programming Parameters Parameter Description Min. Max. Unit tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tPCS VTRIP programming CS inactive time 1 µs tTSU VTRIP setup time 1 µs tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time tVPO VTRIP program enable voltage Off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRIP programmed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25°C.] -25 +25 mV Vtr VTRIP program voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV VTRAN 10 ms VTRIP programming parameters are periodically sampled and are not 100% tested. 14 FN8125.0 April 6, 2005 X5001 VCC Supply Current vs. Temperature (ISB) tWDO vs. Voltage/Temperature (WD1, 0 = 1, 1) 1.85 Isb (µA) 14 1.80 1.75 18 Reset (seconds) Watchdog Timer On (VCC = 5V) 17 20 15 Watchdog Timer On (VCC = 3V) 11 Watchdog Timer Off (VCC = 3V, 5V) 0.55 0.35 -40C 1.65 -40°C 1.60 1.55 25°C 1.50 90°C 1.45 1.0 25C Temp (c) 1.70 1.40 1.7 90C VTRIP vs. Temperature (programmed at 25°C) 3.1 Voltage 4.5 tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0) 0.85 5.025 VTRIP = 5V 5.000 0.80 Reset (seconds) 4.975 Voltage 3.525 VTRIP = 3.5V 3.500 3.475 2.525 25°C 0.70 90°C 0.65 0.60 2.475 0 25 Temperature 1.7 85 tPURST vs. Temperature 275 Reset (seconds) 270 265 260 255 250 245 240 25 Degrees °C 15 4.5 3.1 Voltage tWDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 280 Time (ms) 0.75 VTRIP = 2.5V 2.500 235 -40 -40°C 90 0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 -40°C 25°C 90°C 1.7 3.1 4.5 Voltage FN8125.0 April 6, 2005 X5001 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) FOOTPRINT 0.030" Typical 8 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 16 FN8125.0 April 6, 2005 X5001 PACKAGING INFORMATION 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) (4.16) (7.72) Detail A (20X) (1.78) .031 (.80) .041 (1.05) (0.42) (0.65) All Measurements Are Typical See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 17 FN8125.0 April 6, 2005 X5001 Ordering Information VCC Range VTRIP Range Package Operating Temperature Range Part Number RESET (Active LOW) 4.5-5.5V 4.5.4.75 8-Pin PDIP 0-70°C X5001P-4.5A 8-Lead SOIC 0-70°C X5001S8-4.5A 8-Lead TSSOP 0-70°C X5001V8-4.5A 8-Pin PDIP 0-70°C X5001P 8-Lead SOIC 0-70°C X5001S8 8-Lead TSSOP 0-70°C X5001V8 4.5-5.5V 4.25.4.5 2.7-5.5V 2.85-3.0 8-Lead SOIC 0-70°C X5001S8-2.7A 2.7-5.5V 2.55-2.7 8-Lead SOIC 0-70°C X5001S8-2.7 8-Lead TSSOP 0-70°C X5001V8-2.7 Part Mark Information 8-Lead SOIC 8-Lead TSSOP X5001 YWW XX YWW XXXXX 501AG = 1.8 to 3.6V, 0 to +70°C, VTRIP = 1.7-1.8V 501AH = 1.8 to 3.6V, -40 to +85°C, VTRIP = 1.7-1.8V 501F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.55-2.7V 501G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.55-2.7V 501AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85-3.0V 501AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85-3.0V X501 = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.25-4.5V 501I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.25-4.5V 501AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.5-4.75V 501AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.5-4.75V AG = 1.8 to 3.6V, 0 to +70°C, VTRIP = 1.7-1.8V AH = 1.8 to 3.6V, -40 to +85°C, VTRIP = 1.7-1.8V F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.55-2.7V G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.55-2.7V AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85-3.0V AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85-3.0V Blank = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.25-4.5V I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.25-4.5V AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.5-4.75V AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.5-4.75V YWW = year/work week device is packaged. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN8125.0 April 6, 2005