5 4 3 2 1 LAN8720A RMII PHY Customer Evaluation Board Assy 6584 D D PCB Revision C Schematic Revision 1.3 Design Details Board: Assy 6584 Chip: SMSC LAN8720A C Circuit Diagrams utilizing SMSC Products Are Included As A Means Of Illustrating Typical Semiconductor Applications: Consequently Complete Information Sufficient For Construction Purposes Is Not Necessarily Given. The Information Has Been Carefully Checked And Is Believed To Be Entirely Reliable. However, No Responsibility Is Assumed For Inaccuracies. Furthermore, Such Information Does Not Convey To The Purchaser Of The Semiconductor Devices Described Any License Under The Patent Rights Of SMSC Or Others. SMSC Reserves The Right To Make Changes At Any Time In Order To Improve Design And Supply The Best Product Possible. Board Form Factor: MII Add-On Card Assembly: 24 Lead QFN w/ Exposed GND Pad Revision History ITEM BLOCK DIAGRAM Rev 1.0: Initial release, Rev C C Page(s) Title Page LAN8720A / RMII / Magnetics 1 Configuration Settings 3 2 Rev 1.1: B U3 (page 2) - Changed from 74LVC1G07 to 74LVC1G17 in rework prior to release of all Revision C boards. B "Configuration Resistor Settings" (Pg. 03): Created new table. Configuration Resistor Settings" table, (Pg. 03): Correction to signal name within table from "nINT/TXEN/TXD4" to "nINT/REFCLKO Signal". Added text to signal "nINT" pull-up jumper. Rev 1.2: All Pages - Changed from LAN8720 to LAN8720A Rev 1.3: A C19 changed from 0.1uF to 470pF. A Title LAN8720A RMII PHY Customer Evaluation Board Size Assembly No. Engineer R. W. Date: 5 4 3 2 6584 Tuesday, May 18, 2010 1 PCB Rev Schematic Rev C Sheet 1.3 1 of 3 5 4 3 2 1 LAN8720A / Magnetics / RMII Connector VDDCR Decoupling Capacitors +5V AVDD +3.3V VR1 1 TP2 C1 1.0uF 16V 10% Test Point - Red +5V D VDDCR FB1 OUT 5 2 GND 3 ON/OFF BYPS 4 Vin 2.0A/0.050 DCR TP3 TP1 LP2992IM5-3.3 SOT23-5 C4 0.01uF 50V 10% +5V Test Point - Green VDDCR DNP Test Point - Orange +3.3V C2 4.7uF 6.3V 10% C18 0.1uF 16V 10% R12 0 TP5 RMII +5V decoupling capacitors to be placed near RMII connector C5 0.1uF 16V 10% C6 0.1uF 16V 10% C3 4.7uF 6.3V 10% C19 470pF 50V 5% C20 1.0uF 16V 10% D C21 4.7uF 6.3V 10% DNP Note: C19& C20 decoupling capacitors for VDDCR should be placed as close to LAN8720A as possible. C21 is for internal use only. Test Point - Purple VDDIO + C16 0.1uF 16V 10% Note: Place 0 Ohm resistor close to magnetics module . C17 10uF 25V 10% - VDDIO VDDCR R13 49.9 1/10W 1% R14 49.9 1/10W 1% R15 49.9 1/10W 1% R16 49.9 1/10W 1% R17 0 Place 49.9 Ohm resistors close to LAN8720A. LED1_CATHODE LED1_ANODE R_CRS R10 100 nRST 9 A C 6 2 RXP 23 RXN 22 CRS_DV/MODE2 LED1/REGOFF LED2/nINTSEL 15 RCV RXP 3 LAN8720A TXEN TXD0 TXD1 11 U1 DNP 5173278-2 TD- LED1 (Green) = LINK/ACT nINT/REFCLKO RXER/PHYAD0 16 17 18 CRS_DV/MODE2 2 RXN 3 2 LED1/REGOFF LED2/nINTSEL 24 RBIAS C8 0.022uF 50V 10% 5 XTAL1/CLKIN XTAL2 4 XTAL2 25 XTAL1/CLKIN RBIAS 75 5 RXCT 6 RD- QFN24_4X4MM_EP2P5MM C9 10pF 50V 5% DNP R22 12.1K 1/10W 1% C10 10pF 50V 5% DNP C11 10pF 50V 5% DNP 6 1000 pF NC 8 CHS GND C12 10pF 50V 5% DNP C 3 75 7&8 7 nRST LED2 (Yellow) = SPEED RD+ 2 kV YEL A 14 10 TXEN TXD0 TXD1 TXN RXD1/MODE1 RXD0/MODE0 12 TXCLK TXEN TXD0 TXD1 nINT/REFCLKO RXER/PHYAD0 20 1 75 C 100 TXN 7 8 4&5 75 11 R7 RXD1/MODE1 RXD0/MODE0 TXCT MTG 100 100 100 TD+ 4 MTG R3 R4 R5 MDIO MDC 16 R_RXD1 R_RXD0 R_RXDV R_RXCLK R_RXER 12 13 15 MDIO MDC MDIO MDC GND +5V MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V RJ45 1 GND HEADER_2x10 RMII Signal Test Point Header +5V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +5V TXP TXP 21 14 MDIO R_RXD0 R_RXCLK TXCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GRN XMIT 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD2A VDD1A 2 4 6 8 10 12 14 16 18 20 GND_EP C P1 1 3 5 7 9 11 13 15 17 19 nRST MDC R_RXD1 R_RXER nINT TXEN TXD0 TXD1 R_CRS VDDIO J1 10 T1 Pulse J0011D01BNL VDDCR +5V 1 19 VDDIO C7 0.1uF 16V 10% 9 +3.3V R11 1.50K 1/10W 1% LED2_ANODE LED2_CATHODE Reset Generator Note: Capacitors C9 through C12 are optional for EMI purposes and are not populated on the LAN8720A evaluation board. These capacitors are required for operation in an EMI constrained environment. VDDIO +3.3V R44 4.75K 1% U4 VTH = 2.63V Treset = 20 mS R51 4 VCC 3 MR nRST 2 RESET VDDIO 10.0K B SPST_MOM 1 C15 0.1uF 10V 10% B R25 4.75K TXCLK MIC6315-26D2UY SOT-143_BIG1 TXCLK 0 R49 XTAL1/CLKIN nINT DNP RMII Clock Source Selection Jumpers REGOFF & INTSEL Configuration Resistors PHY Address / nINT Strap / Mode Select Resistors REGOFF R45 1 2 3 XTAL1 LED1/REGOFF 1 EXTCLK50 0 1 REFCLKO LED1/REGOFF 1 2 3 nINT/REFCLKO XTAL2 EN R20 10.0 1/10W 1% 4 2 GND OUT 3 50.000MHz CLK50 2 3 C22 0.1uF 10V 10% TP4 R29 4.75K 1/10W 1% Test Point - Black GND R30 4.75K 1/10W 1% LED1_CATHODE MTG1 1 MTG2 1 NC VDDIO RXD1/MODE1 CRS_DV/MODE2 nINTSEL VCC 5 IN OUT 4 LED2/nINTSEL 1 1 R42 LED2_ANODE 3 25.000MHz HC49US 1 GND C13 30pF 50V 5% 3 Plated Hole w_GND RXER/PHYAD0 0 C23 0.1uF 10V 10% 3 Plated Hole w_GND A Y1 2 NC 74LVC1G17 C14 30pF 50V 5% LED2/nINTSEL R37 4.75K 1/10W 1% R39 4.75K 1/10W R43 2 LED2_CATHODE R33 4.75K 1/10W 1% DNP R32 4.75K 1/10W 1% DNP 3 R31 4.75K 1/10W 1% DNP Title 330 LAN8720A / Magnetics / (R)MII Connector Size Assembly No. Engineer R. W. Date: 5 NC RXD0/MODE0 U3 1 0 AVDD 2 VCC R28 4.75K 1/10W 1% 330 3 1 R23 3-Pad Resistor Default Population Settings: 1--2 U2 R48 4.75K R24 4.75K 1/10W 1% DNP DNP 0 A MODE0 3 1.00M EXTCLK50 Note: U3 must be depopulated when sourcing a 50MHz external (offboard) clock via the R_RXCLK pin. R47 4.75K DNP R21 2 MODE1 1210 R38 4.75K 1/10W R41 MODE2 LED1_ANODE 3 3-Pad Resistor Default Population Settings: 1--2 R_RXCLK PHYADD0 R40 2 0 R46 nINT/REFCLKO VDDIO CLKIN +3.3V 0 R50 DNP AVDD XTAL1/CLKIN nINT 50MHz TX Clock Signal Input (if provided on TXCLK by RMII MAC) GND S1 4 3 2 6584 Thursday, January 06, 2011 1 PCB Rev Schematic Rev C Sheet 1.3 2 of 3 5 4 3 2 1 Configuration Settings D D Configuration Settings C B SIGNAL POPULATE DEPOPULATE PHYAD[0] = 0 R37 R24 PHYAD[0] = 1 R24 R37 MODE[0] = 0 MODE[1] = 0 MODE[2] = 0 R31 R32 R33 R30 R29 R28 MODE[0] = 1 MODE[1] = 1 MODE[2] = 1 R30 R29 R28 R31 R32 R33 Default Default Default Internal 1.2V Reg. Enabled Internal 1.2V Reg. Disabled R40 & R41: 1-2 R40 & R41: 2-3 R40 & R41: 2-3 R40 & R41: 1-2 Default Interrupt Function Enabled on nINT/TXER/TXD4 Signal R50, R42 & R43: 2-3 R42 & R43: 1-2 Interrupt Function Disabled on nINT/TXER/TXD4 Signal R42 & R43: 1-2 R50, R42 & R43: 2-3 Default 25.000MHz Crystal Clock Source Enabled R20, R48, R45 & R46: 1-2 R47, R49 R45 & R46: 2-3 Default 25MHz Crystal Clock Source Disabled, with Offboard 50MHz Clock Source Provided on TXCLK R48, R49 R20, R47, R45 & R46: 1-2 R45 & R46: 2-3 Interrupt Function must be enabled in this configuration. 25MHz Crystal Clock Source Disabled, with Offboard 50MHz Clock Source Provided on RXCLK R48, R45 & R46: 2-3 U3, R20, R47, R49 R45 & R46: 1-2 Interrupt Function must be enabled in this configuration. 25MHz Crystal Clock Source Disabled, with Onboard 50MHz Clock Source Provided on RXCLK U3, R47, R45 & R46: 2-3 R20, R48, R49 R45 & R46: 1-2 Interrupt Function must be enabled in this configuration. 25MHz Crystal Clock Source Disabled, with Onboard 50MHz Clock Source Provided on RXCLK via REFCLK0 U3, R47, R45: 2-3 R46: 1-2 R20, R48, R49 R45: 1-2 R46: 2-3 Interrupt Function must be disabled in this configuration. COMMENTS Default C Interrupt Function must be disabled in this configuration. B A A Title Configuration Settings Size Assembly No. Engineer R. W. Date: 5 4 3 2 6584 Tuesday, May 18, 2010 1 PCB Rev Schematic Rev C Sheet 1.3 3 of 3