IDT ICS9148-08

Integrated
Circuit
Systems, Inc.
ICS9148-08
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-08 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include four CPU, seven PCI and Twelve SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Plus the IOAPIC output powered by
VDDL1. One 48 MHz for USB, and one 24 MHz clock for
Super IO. Spread Spectrum built in ±1.5% modulation to
reduce the EMI. Serial programming I2C interface allows
changing functions, stop clock programing and Frequency
selection. Rise time adjustment for VDD at 3.3V or 2.5V CPU.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PCI, CPU, DIMM). The
add on card might have a pull up or pull down.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
2.5V or 3.3V outputs; CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns,
center 2.6 ns.
No external load cap for CL=18pF crystals
±250 ps CPU, PCI clock skew
400ps (cycle to cycle) CPU jitter
Smooth frequency switch , with selections from 50 to 83.3
MHz CPU.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant input.
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into
20pF loads while maintaining 50±5% duty cycle. The REF
and 24 and 48 MHz clock outputs typically provide better
than 0.5V/ns slew rates.
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-08 Rev A 092297P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-08
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
CPU3.3#_2.51 ,2
IN
GND
PWR
4
X1
IN
5
X2
OUT
VDD2
PCICLK_F
FS11 , 2
PCICLK0
FS21 , 2
PCICLK(1:4)
PCICLK5
PWR
OUT
IN
OUT
IN
OUT
OUT
PCI_STOP#1
IN
6,14
7
8
10, 11, 12, 13
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
SDRAM (0:11)
OUT
19,30,36
VDD3
PWR
23
24
SDATA
SCLK
IN
IN
OUT
24MHz
25
26
40, 41, 43, 44
42
MODE1 , 2
IN
FS0
CPUCLK(0:3)
VDDL2
OUT
IN
OUT
PWR
REF1
OUT
48MHz
1, 2
46
CPU_STOP# 1
47
48
IOAPIC
VDDL1
IN
OUT
PWR
DESCRIPTION
Ref (0:1), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU,
LOW=3.3V CPU1 . Latched input2
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock
Frequency select pin. Latched Input
PCI clock output.
Frequency select pin. Latched Input
PCI clock outputs.
PCI clock output. (In desktop mode, MODE=1)
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
SDRAM clock outputs.
Supply for SDRAM (0:11), PLL core and 24,48MHz clocks,
nominal 3.3V
Data input for I2 C serial input.
Clock input of I2 C input
24MHz output clock
Pin 15, pin 46 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock
Frequency select pin. Latched Input
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318 MHz reference clock, (in Desktop Mode, MODE=1) This
REF output is the STRONGER buffer for ISA BUS loads.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in
Mobile Mode, MODE=0)
IOAPIC clock output. 14.318 MHz Powered by VDDL1.
Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic high to VDD or logic low to GND.
2
ICS9148-08
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
0
1
Pin 46
Pin 15
CPU_STOP#
(INPUT)
REF1
(OUTPUT)
PCI_STOP#
(INPUT)
PCICLK5
(OUTPUT)
Power Management Functionality
PCICLK
(0:5)
PCICLK_F,
REF,
24/48MHz
and SDRAM
Crystal
OSC
VCO
CPU_STOP#
PCI_STOP#
CPUCLK
Outputs
0
1
Stopped Low
Running
Running
Running
Running
1
1
Running
Running
Running
Running
Running
1
0
Running
Stopped Low
Running
Running
Running
CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
CPU3.3#_2.5
Input level
(Latched Data)
1
0
Buffer Selected for
operation at:
2.5V VDD
3.3V VDD
Functionality
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS2
FS1
FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU,
SDRAM(MHz)
50.0
75.0
83.3
68.5
55.0
75.0
60.0
66.8
PCICLK
(MHz)
25.0 (1/2 CPU)
30 (CPU/2.5)
33.3
34.25 (1/2 CPU)
27.5 (1/2 CPU)
37.5 (1/2 CPU)
30.0 (1/2 CPU)
33.4 (1/2 CPU)
REF, IOAPIC
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
3
ICS9148-08
General I2C serial interface information
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknowledge bit between each byte.
A.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D2(H)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
B.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
ACK
Byte 0
ACK
Byte 1
ACK
Byte 0, 1, 2, etc in sequence until STOP.
C.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D.
The input is operating at 3.3V logic levels.
E.
The data byte format is 8 bit bytes.
F.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H.
At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 6:4
Bit 3
Bit 1
Bit 0
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
PCI
CPU clock
Bit6 Bit5 Bit4
33.4(1/2 CPU)
66.8
111
30.0 (1/2 CPU)
60.0
110
37.5 (1/2 CPU)
75.0
101
27.5 (1/2 CPU)
55.0
100
34.5 (1/2 CPU)
68.5
011
33.3
83.3
010
30.0 (CPU/2.5)
75.0
001
25.0 (1/2 CPU)
50.0
000
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
4
PWD
0
Note1
0
0
Note 1. Default at Power-up will be for
latched logic inputs to define
frequency. Bits 4, 5, 6 are default to
000, and if bit 3 is written to a 1 to
use Bits 6:4, then these should be
defined to desired frequency at same
write cycle.
Note: PWD = Power-Up Default
0
0
I2C is a trademark of Philips Corporation
ICS9148-08
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Byte 2: PCIActive/Inactive Register (1 = enable, 0 = disable)
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit
Bit 7
Bit 6
Pin #
7
PWD
1
1
Bit 5
15
1
Bit
Bit
Bit
Bit
Bit
14
12
11
10
8
1
1
1
1
1
4
3
2
1
0
Description
(Reserved)
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
(Desktop only)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. PCICLK5 only in Desktop Mode
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Pin #
47
46
2
PWD
1
1
1
1
1
1
1
1
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching. These outputs are designed to be
configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
17
18
20
21
Byte 6: Optional Register For Possible Future Requirements
Description
(Reserved)
(Reserved)
(Reserved)
IOAPIC0 (Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes:
1. Inactive means outputs are held LOW and are disabled from
switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the
normal modes of operation.
2. REF1 only in Desktop Mode
Pin #
-
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Note: PWD = Power-Up Default
5
ICS9148-08
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS9148-08. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU
clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS9148-08.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
6
ICS9148-08
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-08. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148-08 internally. The minimum that the PCICLK (0:5) clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock
off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
7
ICS9148-08
Shared Pin Operation Input/Output Pins
or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as possible,
as it passes through the programming resistor pad(s).
Pins 2, 7, 8, 25 and 26 on the ICS9148-08 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic
1) power supply or the GND (logic 0) voltage potential. A
10 Kilohm(10K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load
on the output clock during the subsequent operating
period.
Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the device’s internal logic. Figs. 2a and b provide
a single resistor loading option where either solder spot tabs
Fig. 1
8
ICS9148-08
Fig. 2a
Fig. 2b
9
ICS9148-08
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Input Frequency
1
Input Capacitance
1
Transition Time
1
Clk Stabilization
1
Skew
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
Fi
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66MHz
VDD = 3.3 V
MIN
2
VSS-0.3
-5
-200
12
TYP
MAX UNITS
VDD+0.3
V
0.8
V
0.1
5
µA
2
µA
-100
µA
100
160
mA
14.318
16
MHz
36
5
45
pF
pF
CIN
CINX
Logic Inputs
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
2
ms
TSTAB
From VDD = 3.3 V to 1% target Freq.
2
ms
500
4
ps
ns
t CPU-SDRAM1
tCPU-PCI1
1
CONDITIONS
27
VT = 1.5 V
VT = 1.5 V
1
2.6
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Operating Supply
Current
CL = 0 pF; Select @ 66.8 MHz
IDD2.5OP
1
Skew
1
t CP U-SDRAM2
t CP U-P CI2
VT = 1.5 V; VTL = 1.25 V
VT = 1.5 V; VTL = 1.25 V
1
Guaranteed by design, not 100% tested in production.
10
TYP
8
MAX
UNITS
20
mA
800
4
ps
ps
ICS9148-08
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
Output Impedance
Output Impedance
1
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew
Jitter, Cycle-to-cycle
Jitter, One Sigma
Jitter, Absolute
1
1
1
1
CONDITIONS
MIN
TYP
MAX UNITS
RDSP2B
VO = VDD *(0.5)
13.5
45
Ohm
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
VO = VDD *(0.5)
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
13.5
2
45
Ohm
V
V
mA
mA
19
2.2
0.3
-20
26
0.4
-16
tr2B
VOL = 0.4 V, VOH = 2.0 V
2.2
2.5
ns
tf2B
VOH = 2.0 V, VOL = 0.4 V
1.1
1.6
ns
dt2B
VT = 1.25 V
55
%
tsk2B
VT = 1.25 V
250
ps
tjcyc-cyc2B
VT = 1.25 V
200
300
ps
tj1s2B
VT = 1.25 V
50
150
ps
tjabs2B
VT = 1.25 V
+250
ps
45
-250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
Output Impedance
Output Impedance
1
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew
Jitter, One Sigma
Jitter, Absolute
1
1
1
CONDITIONS
MIN
TYP
MAX UNITS
RDSP 1
VO = VDD *(0.5)
10
24
Ohm
RDSN1
VOH1
VOL1
IOH1
IOL1
VO = VDD *(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
2.4
24
Ohm
V
V
mA
mA
41
3
0.2
-60
50
0.4
-40
tr1
VOL = 0.4 V, VOH = 2.4 V
1.6
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
1.2
2
ns
d t1
VT = 1.5 V
51
55
%
tsk1
VT = 1.5 V
100
250
ps
tj1s1
VT = 1.5 V
100
300
ps
tjabs1
VT = 1.5 V
500
ps
45
-500
Guaranteed by design, not 100% tested in production.
11
ICS9148-08
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
Output Impedance
Output Impedance
1
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew
Jitter, One Sigma
Jitter, Absolute
1
1
1
CONDITIONS
MIN
RDSP 1
VO = VDD *(0.5)
10
RDSN1
VOH1
VOL1
IOH1
IOL1
VO = VDD *(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
2.4
41
TYP
MAX UNITS
24
Ω
24
Ω
V
V
mA
mA
3
0.2
-60
50
0.4
-40
Tr1
VOL = 0.4 V, VOH = 2.4 V
1.6
2
ns
Tf1
VOH = 2.4 V, VOL = 0.4 V
1.2
2
ns
Dt1
VT = 1.5 V
52
55
%
Tsk1
VT = 1.5 V
150
250
ps
Tj1s1
VT = 1.5 V
50
150
ps
Tjabs1
VT = 1.5 V
+250
ps
45
-250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
Output Impedance
Output Impedance
1
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
Jitter, One Sigma
Jitter, Absolute
1
1
1
CONDITIONS
MIN
RDSP4B
VO = VDD *(0.5)
13.5
RDSN4B
VOH4B
VOL4B
IOH4B
IOL4B
VO = VDD *(0.5)
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
13.5
2
19
TYP
MAX UNITS
45
Ohm
45
Ohm
V
V
mA
mA
2.2
0.3
-20
26
0.4
-16
Tr4B
VOL = 0.4 V, VOH = 2.0 V
1.4
1.7
ns
Tf4B
VOH = 2.0 V, VOL = 0.4 V
1.3
1.6
ns
Dt4B
VT = 1.25 V
60
%
Tj1s4B
VT = 1.25 V
3
%
Tjabs4B
VT = 1.25 V
5
%
50
1
-5
Guaranteed by design, not 100% tested in production.
12
ICS9148-08
Electrical Characteristics - 24,48MHz, REF(0:1)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
Output Impedance
1
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
Jitter, One Sigma
Jitter, Absolute
1
1
1
CONDITIONS
MIN
TYP
MAX UNITS
RDSP 5
VO = VDD *(0.5)
20
60
Ohm
RDSN5
VOH5
VOL5
IOH5
IOL5
VO = VDD *(0.5)
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
20
2.4
60
Ohm
V
V
mA
mA
16
2.6
0.3
-32
25
0.4
-22
tr5
VOL = 0.4 V, VOH = 2.4 V
1.7
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
1.6
4
ns
d t5
VT = 1.5 V
53
55
%
tj1s5
VT = 1.5 V
1
3
%
tjabs5
VT = 1.5 V
3
8
%
45
Guaranteed by design, not 100% tested in production.
13
ICS9148-08
SSOP Package
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
MIN.
.620
D
NOM.
.625
N
MAX.
.630
48
Ordering Information
ICS9148F-08
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
14
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.