A4987 Datasheet

A4987
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
Features and Benefits
Description
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The A4987 is a dual DMOS full-bridge stepper motor driver
with parallel input communication and overcurrent protection.
Each full-bridge output is rated up to 35 V and ±1 A. The A4987
includes fixed off-time pulse width modulation (PWM) current
regulators, along with 2- bit nonlinear DACs (digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps. The PWM current regulator uses the
Allegro™ patented mixed decay mode for reduced audible
motor noise, increased step accuracy, and reduced power
dissipation.
Low RDS(ON) outputs
Internal mixed current decay mode
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
3.3 and 5 V compatible logic supply
Thin profile QFN and TSSOP packages
Thermal shutdown circuitry
Short-to-ground protection
Shorted load protection
Low current Sleep mode, < 10 μA
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Packages:
24-contact QFN
4 mm × 4 mm × 0.75 mm
(ES package)
The outputs are protected from shorted load and short-toground events, which protect the driver and associated circuitry
from thermal damage or flare-ups. Other protection features
include thermal shutdown with hysteresis, undervoltage lockout
(UVLO) and crossover current protection. Special power-up
sequencing is not required.
Approximate size
The A4987 is supplied in two packages, a 24-contact QFN (ES)
and a 24-pin TSSOP (LP). Both packages have exposed thermal
pads for enhanced thermal performance. The 24-contact ES is
4 mm × 4 mm, with a nominal overall package height of 0.75
mm. The 24-pin LP is a TSSOP with 0.65 pitch and an overall
package height of ≤1.2 mm. Both packages are lead (Pb) free,
with 100% matte tin leadframe plating.
24-pin TSSOP
with exposed thermal pad
(LP Package)
Typical Application Diagram
VDD
0.1 μF
0.1 μF
0.22 μF
0.22 μF
Microcontroller or
Controller Logic
VREG ROSC
CP1
CP2
VCP
VDD
VBB1
VBB2
OUT1A
SLEEP
IN01
A4987
OUT1B
SENSE1
IN02
PH1
IN11
OUT2A
IN12
OUT2B
PH2
VREF
4987-DS, Rev. 5
GND
GND
SENSE2
100 μF
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Selection Guide
Part Number
Package
Packing
A4987SESTR-T
24-pin QFN with exposed thermal pad
1500 pieces per 7-in. reel
A4987SLPTR-T
24-pin TSSOP with exposed thermal pad
4000 pieces per 13-in. reel
Absolute Maximum Ratings
Rating
Units
Load Supply Voltage
Characteristic
Symbol
VBB
Notes
35
V
Output Current
IOUT
±1
A
Logic Input Voltage
VIN
–0.3 to 5.5
V
Logic Supply Voltage
VDD
–0.3 to 5.5
V
–2.0 to 37
V
VSENSE
–0.5 to 0.5
V
Motor Outputs Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
VREF
TA
Range S
5.5
V
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Functional Block Diagram
VCP
CHARGE PUMP
REGULATOR
VREG
CP2
CP1
Rosc
0.1 μF
0.1 μF
OSC
0.22 μF
DMOS FULL-BRIDGE 1
VBB1
-
Sense2
To
VBB2
OCP
+
DAC
OUT1A
VREF
PWM Latch
BLANKING
Mixed Decay
OSC
OUT1B
VDD
GATE
DRIVE
IN01
SENSE1
IN02
PH1
CONTROL
LOGIC
IN11
DMOS FULL-BRIDGE 2
VBB2
IN12
PH2
OCP
SLEEP
OSC
VCP VREG
+
PWM Latch
BLANKING
Mixed Decay
VREF
OUT2B
VREG
DAC
VREF
Sense2
SENSE2
GND
Sense2
GND
-
REF
OUT2A
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A4987
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics
Output Drivers
Min.
Typ.2
Max.
Units
8
0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
700
700
–
–
–
–
–
–
–
–
35
35
5.5
900
900
1.3
1.3
4
2
10
8
5
10
V
V
V
mΩ
mΩ
V
V
mA
mA
μA
mA
mA
μA
VIN(1)
VDD0.7
–
–
V
VIN(0)
–
–
V
μA
Symbol
Load Supply Voltage Range
VBB
Logic Supply Voltage Range
VDD
Output On Resistance
RDS(ON)
Body Diode Forward Voltage
VF
Motor Supply Current
IBB
Logic Supply Current
IDD
Test Conditions
Operating
During Sleep Mode
Operating
Source Driver, IOUT = –800 mA
Sink Driver, IOUT = 800 mA
Source Diode, IF = –800 mA
Sink Diode, IF = 800 mA
fPWM < 50 kHz
Operating, outputs disabled
Sleep Mode
fPWM < 50 kHz
Outputs off
Sleep Mode
Control Logic
Logic Input Voltage
Logic Input Current
Logic Input Pull-down
Logic Input Hysteresis
Blank Time
IIN(1)
IIN(0)
RIN02
RIN12
VHYS(IN)
tBLANK
Fixed Off-Time
tOFF
Reference Input Voltage Range
Reference Input Current
VREF
IREF
Current Trip-Level Error3
errI
Crossover Dead Time
Protection
Overcurrent Protection Threshold4
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VDD Undervoltage Lockout
VDD Undervoltage Hysteresis
tDT
IOCPST
TTSD
TTSDHYS
VDDUVLO
VDDUVLOHYS
VIN = VDD0.7
VIN = VDD0.3
As a % of VDD
OSC = VDD or GND
ROSC = 25 kΩ
VREF = 2 V, %ITripMAX = 33.3%
VREF = 2 V, %ITripMAX = 66.7%
VREF = 2 V, %ITripMAX = 100.00%
VDD rising
–20
<1.0
VDD0.3
20
–20
<1.0
20
μA
–
–
5
0.7
20
23
0
–3
–
–
–
100
100
50
11
1
30
30
–
0
–
–
–
475
–
–
19
1.3
40
37
4
3
±15
±5
±5
800
kΩ
kΩ
%
μs
μs
μs
V
μA
%
%
%
ns
1.1
–
–
2.7
–
–
165
15
2.8
90
–
–
–
2.9
–
A
°C
°C
V
mV
1For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3V
ERR = [(VREF/8) – VSENSE] / (VREF/8).
4Overcurrent protection (OCP) is tested at T = 25°C in a restricted range and guaranteed by characterization.
A
2Typical
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
Value Units
ES package; estimated, on 4-layer PCB, based on JEDEC standard
37
ºC/W
LP package; on 4-layer PCB, based on JEDEC standard
28
ºC/W
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.5
5.0
4.5
Power Dissipation, PD (W)
4.0
(R
3.5
θJ
A
3.0
(R
2.5
θJ
2.0
A
=3
7º
=
C/
28
W
ºC
/W
)
)
1.5
1.0
0.5
0.0
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Functional Description
Device Operation. The A4987 is designed to operate one
stepper motor in full, half, or quarter step mode. The currents in
each of the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control
circuitry. Each full-bridge peak current is set by the value of
an external current sense resistor, RSx , and a reference voltage,
VREFx .
Percentages of the peak current are set using a 2-bit nonlinear
DAC that programs 33%, 66%, or 100% of the peak current, or
disables the outputs.
Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP . Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows
through the motor winding and the current sense resistor, RSx.
When the voltage across RSx equals the DAC output voltage, the
current sense comparator resets the PWM latch. The latch then
turns off the appropriate source driver and initiates a fixed off
time decay mode.
The maximum value of current limiting is set by the selection of
RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by
ITripMAX = VREF / ( 8
 RS)
where RS is the resistance of the sense resistor (Ω) and VREF is
the input voltage on the REF pin (V).
The 2-bit DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
Itrip = (%ITripMAX / 100)
× ITripMAX
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The off-time, tOFF, is determined by the
ROSC terminal. The ROSC terminal has two settings:
▪ ROSC tied to VDD or ground — off-time internally set to 30 μs
▪ ROSC through a resistor to ground — off-time is determined by
the following formula:
tOFF ≈ ROSC ⁄ 825
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (μs), is approximately
tBLANK ≈ 1 μs
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is
shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the
¯Ē
¯Ē
¯P̄¯ input goes
device will remain disabled (latched) until the S̄L̄
high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 1.
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time (≈1 μs) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into
a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in figure 2.
During a shorted load event it is normal to observe both a positive and negative current spike as shown in figure 3, due to the
direction change implemented by the Mixed decay feature. This
is shown in figure 3. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A4987
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
5 A / div.
Fault latched
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
VREG (VREG). This internally-generated voltage is used to
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4987 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4987 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
t→
Figure 1. Short-to-ground event
5 A / div.
Fixed off-time
Sleep Mode ( S̄¯L̄¯Ē¯Ē¯P̄¯ ). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator, and
¯Ē
¯Ē
¯P̄¯ pin puts the A4987 into
charge pump. A logic low on the S̄L̄
Sleep mode. When emerging from Sleep mode, in order to allow
the charge pump to stabilize, provide a delay of 1 ms before issuing a logic command.
t→
Figure 2. Shorted load (OUTxA → OUTxB) in
Slow decay mode
Mixed Decay Operation. The bridge operates in Mixed
Decay mode, as shown in figures 5 through 7. As the trip point
is reached, the A4987 initially goes into a fast decay mode for
31.25% of the off-time, tOFF. After that, it switches to Slow Decay
mode for the remainder of tOFF. A timing diagram for this feature
appears in figure 4.
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recirculates in Mixed Decay mode. This synchronous rectification
feature turns on the appropriate FETs during current decay, and
effectively shorts out the body diodes with the low FET RDS(ON).
This reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches
zero (0 A), preventing reversal of the load current.
5 A / div.
Fixed off-time
Fast decay portion
(direction change)
t→
Figure 3. Shorted load (OUTxA → OUTxB) in Mixed decay mode
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
PHx
IN0x
IN1x
100.00
70.71
See Enlargement A
IOUT
0
–70.71
–100.00
Enlargement A
toff
IPEAK
tFD
tSD
Slow Decay
Mixed Decay
IOUT
Fa
st
De
ca
y
t
Symbol
toff
IPEAK
Characteristic
Device fixed off-time
Maximum output current
tSD
Slow decay interval
tFD
Fast decay interval
IOUT
Device output current
Figure 4. Current Decay Modes Timing Chart
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Application Layout
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A4987 must be soldered directly onto the board. On the underside of the A4987 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A4987, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor
(CIN2). This is necessary because the ceramic capacitor will be
responsible for delivering the high frequency current components.
The sense resistors, RSx , should have a very low impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. The SENSEx
pins have very short traces to the RSx resistors and very thick,
low impedance traces directly to the star ground underneath the
device. If possible, there should be no other components on the
sense circuits.
Solder
A4987
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
OUT2A OUT1A
OUT2B
OUT1B
Thermal Vias
GND
OUT2B
PH2
OUT1A
SENSE1
VBB1
VDD
C1
C2
CAPACITANCE
VDD
SLEEP
ROSC
ROSC
BULK
GND
A4987
VCP
IN11
C4
IN01
IN12
C4
REF
CP2
IN02
C6
C3
PH1
GND
CP1
VREG
C3
GND
OUT1B
PAD
GND
C1
OUT2A
VBB2
OUT2B
U1
SENSE2
C7
GND
C7
OUT1B
R5
R4
R5
R4
OUT1A
OUT2A
VBB
ES package configuration shown
C6
C2
ROSC
VDD
VBB
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
OUT2B
C3
U1
GND
C6
GND
C4
GND
C3
OUT2A
C5
R4
C4
ROSC
R5
C5
OUT1A
C1
IN11
ROSC
GND
GND
CAPACITANCE
C2
VDD
ROSC
SLEEP
VDD
IN01
C1
BULK
VCP
VREG
GND
REF
VDD
GND
PH2
OUT2B
CP2
INO2
IN12
GND
OUT1B
GND
A4987
CP1
VBB2
PAD
C6
SENSE2
OUT2A
R4
OUT1A
SENSE1
VBB1
R5
OUT1B
PH1
C2
GND
VBB
VBB
LP package typical application and circuit layout
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Pin Circuit Diagrams
VDD
VBB
VBB
8V
GND
GND
SENSE
GND
CP2
GND
GND
GND
GND
GND
VBB
10 V
CP1
40 V
PGND
VREG
VCP
VREG
DMOS
Parasitic
GND
8V
IN01
IN02
IN11
IN12
PH1
PH2
VREF
ROSC
SLEEP
VBB
OUT
DMOS
Parasitic
8V
GND
DMOS
Parasitic
GND
GND
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Step Sequencing Diagrams
100.0
100.0
66.7
Phase 1
(%)
66.7
Phase 1
(%)
0
–66.7
–66.7
–100.0
–100.0
100.0
100.0
66.7
Phase 2
(%)
0
66.7
Phase 2
(%)
0
0
–66.7
–66.7
–100.0
–100.0
Full step 2 phase
Half step 2 phase
Modified full step 2 phase
Modified half step 2 phase
Figure 5. Step Sequencing for Full-Step Increments.
Figure 6. Step Sequencing for Half-Step Increments.
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
100.0
66.7
33.3
Phase 1
(%)
0
–33.3
–66.7
–100.0
100.0
66.7
33.3
Phase 2
(%)
0
–33.3
–66.7
–100.0
Figure 7. Step Sequence for Quarter-Step Increments
Step Sequencing Settings
Full
1/2
1
1/4
1
2
1
2
3
4
3
5
6
2
4
7
8
5
9
10
3
6
11
12
7
13
14
4
8
15
16
* Denotes modified step mode
Phase 1
(%ITripMax)
I01
I11
PHASE
Phase 2
(%ITripMax)
I02
I12
PHASE
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
H
H
L
L
L
L
L
H
H
H
L
L
L
L
L
H
x
1
1
1
1
1
1
1
x
0
0
0
0
0
0
0
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
L
L
1
1
1
1
X
0
0
0
0
0
0
0
X
1
1
1
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Pin-out Diagrams
LP Package
19 VBB1
20 SENSE1
21 OUT1A
22 OUT2A
24 VBB2
23 SENSE2
ES Package
CP1 1
24 GND
CP2 2
23 PH2
VCP 3
22 OUT2B
OUT2B
1
18 OUT1B
PH2
2
17 PH1
IN02 5
GND
3
16 GND
IN12 6
CP1
4
15 REF
IN11 7
CP2
5
14 IN01
ROSC 8
VCP
6
13 VDD
SLEEP 9
SLEEP 12
ROSC 11
IN11 10
9
IN12
8
VREG
IN02
7
PAD
21 VBB2
VREG 4
20 SENSE2
PAD
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
VDD 10
15 OUT1B
IN01 11
14 PH1
REF 12
13 GND
Terminal List Table
Number
Name
CP1
Description
ES
LP
4
1
Charge pump capacitor terminal
CP2
5
2
Charge pump capacitor terminal
PH1
17
14
Logic input
Logic input
PH2
2
23
GND
3, 16
13, 24
IN02
8
5
Logic input
IN12
9
6
Logic input
Ground*
NC
–
–
No connection
OUT1A
21
18
DMOS Full Bridge 1 Output A
OUT1B
18
15
DMOS Full Bridge 1 Output B
OUT2A
22
19
DMOS Full Bridge 2 Output A
OUT2B
1
22
DMOS Full Bridge 2 Output B
REF
15
12
Gm reference voltage input
IN11
10
7
Logic input
ROSC
11
8
Timing set
SENSE1
20
17
Sense resistor terminal for Bridge 1
SENSE2
23
20
Sense resistor terminal for Bridge 2
S̄¯L̄¯Ē¯Ē¯P̄¯
12
9
Logic input
IN01
14
11
Logic input
VBB1
19
16
Load supply
VBB2
24
21
Load supply
VCP
6
3
Reservoir capacitor terminal
VDD
13
10
Logic supply
VREG
7
4
Regulator decoupling terminal
PAD
–
–
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
14
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
ES Package, 24-Pin QFN with Exposed Thermal Pad
0.30
4.00 ±0.15
24
1
2
0.50
24
0.95
1
2
A
2.70
4.00 ±0.15
4.10
2.70
4.10
25X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
0.75 ±0.05
0.50 BSC
C
C
PCB Layout Reference View
For Reference Only; not for tooling use (reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
0.45 MAX
B
2.70
2
1
C Reference land pattern layout (reference IPC7351
QFN50P400X400X80-25W6M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
24
2.70
15
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
7.80 ±0.10
24
0.65
0.45
4° ±4
+0.05
0.15 –0.06
B
3.00±0.05 4.40 ±0.10 6.40 ±0.20
A
1
6.10
(1.00)
2
4.32±0.05
0.25
24X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.60 ±0.15
0.65
1.20 MAX
0.15 MAX
C
SEATING PLANE
GAUGE PLANE
1.65
4.32
C
PCB Layout Reference View
For reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
16
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4987
Revision History
Revision
Revision Date
Rev. 5
March 21, 2012
Description of Revision
Update Step Sequence and example layout
Copyright ©2009-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
17
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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