48xa0_2v220.pdf

HT48RA0-2/HT48CA0-2
Remote Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals
- HA0075E MCU Reset and Oscillator Circuits Application Note
- HA0076E HT48RAx/HT48CAx Software Application Note
- HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing
Features
· Operating voltage: 2.0V~3.6V
· 62 powerful instructions
· Ten bidirectional I/O lines
· Up to 1ms instruction cycle with 4MHz system clock
· 4 Schmitt trigger input lines
· All instructions in 1 or 2 machine cycles
· One carrier output (1/2 or 1/3 duty)
· 14-bit table read instructions
· On-chip crystal and RC oscillator
· One-level subroutine nesting
· Watchdog Timer
· Bit manipulation instructions
· 1K´14 program memory
· Low voltage reset function
· 32´8 data RAM
· 20-pin SSOP package
· HALT function and wake-up feature reduce power
consumption
General Description
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, watchdog timer,
HALT and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range of
application possibilities such as industrial control, consumer products, and particularly suitable for use in
products such as infrared remote controllers and various subsystem controllers.
The HT48RA0-2/HT48CA0-2 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product
applications. The mask version HT48CA0-2 is fully pin
and functionally compatible with the OTP version
HT48RA0-2 device.
Rev. 2.20
1
September 5, 2008
HT48RA0-2/HT48CA0-2
Block Diagram
S T A C K
P ro g ra m
C o u n te r
P ro g ra m
S Y S C L K /4
In s tr u c tio n
R e g is te r
M
M P
U
X
D A T A
M e m o ry
F r e q u e n c y D iv id e r
C a r r ie r C o n tr o l
W D T
P C 0 C o n tro l
A L U
P O R T B
S T A T U S
P B
S h ifte r
T im in g
G e n e ra to r
S
C 1
S
P B 0 ~ P B 1
P B 2 ~ P B 5
P O R T A
P A
O S
R E
V D
V S
P C 0 /R E M
M U X
In s tr u c tio n
D e c o d e r
O S C 2
L e v e l o r C a r r ie r
P A 0 ~ P A 7
A C C
D
Pin Assignment
P A 1
1
2 0
P A 2
P A 0
2
1 9
P A 3
P B 1
3
1 8
P A 4
P B 0
4
1 7
P A 5
P C 0 /R E M
5
1 6
P A 6
V D D
6
1 5
P A 7
O S C 2
7
1 4
P B 2
O S C 1
8
1 3
P B 3
V S S
9
1 2
P B 4
R E S
1 0
1 1
P B 5
H T 4 8 R A 0 -2 /H T 4 8 C A 0 -2
2 0 S S O P -A
Rev. 2.20
2
September 5, 2008
HT48RA0-2/HT48CA0-2
Pin Description
I/O
Code
Option
Description
PA0~PA7
I/O
¾
Bidirectional 8-bit input/output port with pull-high resistors. Each bit can be determined as NMOS output or Schmitt trigger input by software instructions.
PB0, PB1
I/O
Wake-up
or None
2-bit bidirectional input/output lines with pull-high resistors. Each bit can be determined as NMOS output or Schmitt trigger input by software instructions.
Each bit can also be configured as wake-up input by code option.
PB2~PB5
I
PC0/REM
O
Level or
Carrier
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
OSC2
OSC1
O
I
Crystal
or RC
RES
I
¾
Pin Name
Wake-up or 4-bit Schmitt trigger input lines with pull-high resistors. Each bit can be configNone
ured as a wake-up input by code option.
Level or carrier output pin
PC0 can be set as CMOS output pin or carrier output pin by code option.
OSC1, OSC2 are connected to an RC network or a crystal (determined by
code option) for the internal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock (NMOS open drain output).
Schmitt trigger reset input. Active low.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+4.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
2.0
¾
3.6
V
VDD
Operating Voltage
¾
IDD
Operating Current
3V
No load, fSYS=4MHz
¾
0.7
1.5
mA
ISTB
Standby Current
3V
No load, system HALT
¾
¾
1
mA
VIL1
Input Low Voltage for I/O Ports
3V
¾
0
¾
0.2VDD
V
VIH1
Input High Voltage for I/O Ports
3V
¾
0.8VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
3V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
3V
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset Voltage
¾
Temperature=25°C*
1.8
1.9
2.0
V
IOL
I/O Ports Sink Current
3V
VOL=0.1VDD
4
8
¾
mA
IOH
PC0/REM Output Source Current
3V
VOH=0.9VDD
-2
-4
¾
mA
RPH
Pull-high Resistance
3V
20
60
100
kW
¾
Note: ²*² Guaranteed at 25°C only
Rev. 2.20
3
September 5, 2008
HT48RA0-2/HT48CA0-2
A.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock
3V
¾
400
¾
4000
kHz
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
¾
1024
¾
tSYS
0.25
1
2
ms
tSST
System Start-up Timer Period
¾
Power-up, reset or wake-up
from HALT
tLVR
Low Voltage Width to Reset
¾
¾
Note: tSYS=1/fSYS
Functional Description
Execution Flow
Program Counter - PC
The HT48RA0-2/HT48CA0-2 system clock can be derived from a crystal/ceramic resonator oscillator. It is internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed and its contents specify a maximum of 1024 addresses.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
T 1
S y s te m
T 2
T 3
T 4
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
In s tr u c tio n C y c le
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Initial reset
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
0
0
0
0
0
0
0
0
0
0
*9
*8
@7
@6
@3
@2
@1
@0
Skip
Program Counter + 2
Loading PCL
@5
@4
Jump, call branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*9~*0: Program counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
@[email protected]: PCL bits
Rev. 2.20
4
September 5, 2008
HT48RA0-2/HT48CA0-2
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, the remaining 2 bits are read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), where P indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
All table related instructions need 2 cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
Stack Register - STACK
Program Memory - ROM
This is a special part of the memory used to save the
contents of the program counter (PC) only. The stack is
organized into one level and is neither part of the data
nor part of the program space, and is neither readable
nor writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine signaled by a return instruction (RET), the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
The program memory is used to store the program instructions which are to be executed. It also contains
data and table and is organized into 1024´14 bits, addressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for the initialization program. After chip reset, the program always begins execution at
location 000H.
· Table location
If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be
lost (only the most recent return address is stored).
Any location in the EPROM space can be used as
look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m]
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
0 0 0 H
Data Memory - RAM
The data memory is designed with 42´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(32´8). Most of them are read/write, but some are read
only.
D e v ic e in itia liz a tio n p r o g r a m
The unused space before 20H is reserved for future expanded usage and reading these locations will return
the result 00H. The general purpose data memory, addressed from 20H to 3FH, is used for data and control
information under instruction command.
n 0 0 H
P ro g ra m
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through memory pointer register (MP;01H).
L o o k - u p ta b le ( 2 5 6 w o r d s )
3 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 3
Program Memory
Table Location
Instruction(s)
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*9~*0: Table location bits
P9~P8: Current program counter bits
Rev. 2.20
@[email protected]: Table pointer bits
5
September 5, 2008
HT48RA0-2/HT48CA0-2
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result ²1². Any writing operation to MP will only transfer
the lower 7-bit data to MP.
0 2 H
0 3 H
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
Accumulator
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
capable of carrying out immediate data operations. Data
movement between two data memory locations has to
pass through the accumulator.
0 9 H
0 A H
S T A T U S
0 B H
S p e c ia l P u r p o s e
D a ta M e m o ry
0 C H
0 D H
Arithmetic and Logic Unit - ALU
0 E H
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions.
0 F H
1 0 H
1 1 H
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
1 2 H
P A
· Logic operations (AND, OR, XOR, CPL)
1 3 H
1 4 H
· Rotation (RL, RR, RLC, RRC)
P B
1 5 H
· Increment and Decrement (INC, DEC)
1 6 H
1 7 H
P C
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
: U n u s e d
The ALU not only saves the results of a data operation but
also changes the contents of the status register.
R e a d a s "0 0 "
1 F H
2 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(3 2 B y te s )
3 F H
Status Register - STATUS
This 8-bit status register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watchdog time-out
flag (TO). It also records the status information and controls the operation sequence.
RAM Mapping
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other register. Any data written into the status register
will not change the TO or PDF flags. In addition it should
be noted that operations related to the status register
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF
is set by executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 2.20
6
September 5, 2008
HT48RA0-2/HT48CA0-2
may give different results from those intended. The TO
and PDF flags can only be changed by the Watchdog
Timer overflow, chip power-up, clearing the Watchdog
Timer and executing the HALT instruction.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift for the oscillator. No other external components are
needed. Instead of a crystal, the resonator can also be
connected between OSC1 and OSC2 to get a frequency
reference, but two external capacitors in OSC1 and
OSC2 are required.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on executing the subroutine call, the status
register will not be automatically pushed onto the stack.
If the contents of the status are important and if the subroutine can corrupt the status register, precautions must
be taken to save it properly.
Watchdog Timer - WDT
The clock source of the WDT is implemented by instruction clock (system clock divided by 4). The clock source
is processed by a frequency divider and a prescaller to
yield various time out periods.
Oscillator Configuration
There are two oscillator circuits implemented in the
microcontroller.
WDT time out period =
Clock Source
2n
Where n= 8~11 selected by code option.
O S C 1
O S C 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
(N M O S o p e n
d r a in o u tp u t)
This timer is designed to prevent a software malfunction
or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by code option. If the Watchdog Timer is disabled,
all the executions related to the WDT result in no operation and the WDT will lose its protection purpose. In this
situation the logic can only be restarted by an external
logic.
O S C 2
R C
O s c illa to r
System Oscillator
Both are designed for system clocks; the RC oscillator
and the Crystal oscillator, which are determined by code
options. No matter what oscillator type is selected, the
signal provides the system clock. The HALT mode stops
the system oscillator and ignores the external signal to
conserve power.
A WDT overflow under normal operation will initialize ²chip
reset² and set the status bit ²TO². To clear the contents of
the WDT prescaler, three methods are adopted; external
reset (a low level to RES), software instructions, or a HALT
instruction. There are two types of software instructions.
One type is the single instruction ²CLR WDT², the other
type comprises two instructions, ²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, only one can
be active depending on the code option - ²CLR WDT
times selection option². If the ²CLR WDT² is selected (i.e..
CLR WDT times equal one), any execution of the CLR
WDT instruction will clear the WDT. In case ²CLR WDT1²
and ²CLR WDT2² are chosen (i.e.. CLR WDT times equal
two), these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
If an RC oscillator is used, an external resistor between
OSC1 and VSS in needed and the resistance must
range from 51kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of the
oscillation may vary with VDD, temperature and the chip
itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.
C le a r W D T
F r e q u e n c y D iv id e r
C lo c k S o u r c e
( S y s te m C lo c k /4 )
3 - b it C o u n te r
P r e s c a lle r
( 8 - b it)
C o d e O p tio n
S e le c t
C o d e
O p tio n
W D T
T im e - o u t
C lo c k S o u r c e
2 n
(n = 8 ~ 1 1 )
Watchdog Timer
Rev. 2.20
7
September 5, 2008
HT48RA0-2/HT48CA0-2
Power Down Operation - HALT
extra-delay of 1024 system clock pulses when the system powers up or when the system awakes from a HALT
state.
The HALT mode is initialized by the HALT instruction
and results in the following...
When a system power up occurs, an SST delay is added
during the reset period. But when the reset comes from
the RES pin, the SST delay is disabled. Any wake-up
from HALT will enable the SST delay.
· The system oscillator turns off and the WDT stops.
· The contents of the on-chip RAM and registers remain
unchanged.
· WDT prescaler are cleared.
The functional unit chip reset status is shown below.
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
Program Counter
The system can quit the HALT mode by means of an external reset or an external falling edge signal on port B.
An external reset causes a device initialization. Examining the TO and PDF flags, the reason for chip reset
can be determined. The PDF flag is cleared when the
system powers up or execute the CLR WDT instruction
and is set when the HALT instruction is executed. The
TO flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the program counter and SP,
the others keep their original status.
000H
WDT Prescaler
Clear
Input/Output ports
Input mode
Stack Pointer
Points to the top of the stack
Carrier output
Low level
V D D
R E S
tS
S S T T im e - o u t
The port B wake-up can be considered as a continuation
of normal execution. Each bit in port B can be independently selected to wake up the device by the code option.
Awakening from an I/O port stimulus, the program will
resume execution of the next instruction.
C h ip
R e s e t
Reset Timing Chart
Once a wake-up event(s) occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up.
V
V
D D
1 0 0 k W
1 0 0 k W
R E S
R E S
0 .1 m F
There are three ways in which a reset can occur:
· RES reset during normal operation
Note:
· WDT time-out reset during normal operation
Some registers remain unchanged during reset conditions. Most registers are reset to the ²initial condition²
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
H i-n o is e
R e s e t
C ir c u it
0 .1 m F
Reset Circuit
· RES reset during HALT
0
1 0 k W
B a s ic
R e s e t
C ir c u it
Reset
PDF
D D
0 .0 1 m F
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
TO
S T
Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H A L T
W D T
RESET Conditions
W D T
T im e - o u t
R e s e t
R e s e t
R E S
O S C 1
S S T
1 0 -s ta g e
R ip p le C o u n te r
Note: ²u² means unchanged.
P o w e r - o n D e te c tio n
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
Rev. 2.20
Reset Configuration
8
September 5, 2008
HT48RA0-2/HT48CA0-2
The chip reset status of the registers is summarized in the following table:
Register
Program Counter
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
000H
000H
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
0011 1111
0011 1111
0011 1111
0011 1111
uuuu uuuu
PC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
Note:
²u² means unchanged
²x² means unknown
Carrier
The following table shows examples of carrier frequency selection.
The HT48RA0-2/HT48CA0-2 provides a carrier output
which shares the pin with PC0. It can be selected to be a
carrier output (REM) or level output pin (PC0) by code
option. If the carrier output option is selected, setting
PC0=²0² to enable carrier output and setting PC0=²1² to
disable it at low level output.
fSYS
455kHz
where m=2 or 3 and n=0~3, both are selected by code
option. If m=2, the duty cycle of the carrier output is 1/2
duty. If m=3, the duty cycle of the carrier output can be
1/2 duty or 1/3 duty also determined by code option (with
the exception of n=0).
Detailed selection of the carrier duty is shown below:
1/2
3
1/3
6, 12, 24
1/2 or 1/3
F r e q u e n c y D iv id e r
C lo c k S o u r c e
( S y s te m C lo c k /4 )
V
3 - b it C o u n te r
1 /2 o r 1 /3 d u ty
1 /2
C o d e O p tio n
1 /3
37.92kHz
1/3 only
3
56.9kHz
1/2 only
2
Both PA and PB for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA, PB0~PB1 and PC output operation, all
data are latched and remain unchanged until the output
latch is rewritten.
Duty Cycle
2, 4, 8, 16
m´2n
There are an 8-bit bidirectional input/output port, a 4-bit
input with 2-bit I/O port and one-bit output port in the
HT48RA0-2/HT48CA0-2, labeled PA, PB and PC which
are mapped to [12H], [14H], [16H] of the RAM, respectively. Each bit of PA can be selected as NMOS output or
Schmitt trigger with pull-high resistor by software instruction. PB0~PB1 have the same structure with PA,
while PB2~PB5 can only be used for input operation
(Schmitt trigger with pull-high resistors). PC is only
one-bit output port shares the pin with carrier output. If
the level option is selected, the PC is CMOS output.
Clock Source
m´2n
m´2n
Duty
Input/Output Ports
The clock source of the carrier is implemented by instruction clock (system clock divided by 4) and processed by a frequency divider to yield various carry
frequency.
Carry Frequency=
fCARRIER
C a r r ie r D u ty
S e le c t
D D
L e v e l
C o d e O p tio n
( c a r r ie r o r le v e l)
C a r r ie r
R E M /P C 0
C a r r ie r
L e v e l
R e a d p a th fo r r e a d - m o d ify - w r ite
P C 0 D a ta R e g is te r
Carrier/Level Output
Rev. 2.20
9
September 5, 2008
HT48RA0-2/HT48CA0-2
V
D a ta b u s
W r ite
D
W e a k
P u ll- u p
Q
C K
S
D D
P A 0 ~ P A 7
P B 0 ~ P B 1
Q
C h ip R e s e t
R e a d D a ta
S y s te m
W a k e -u p
C o d e O p tio n
P B 0 ~ P B 1 o n ly
PA, PB Input/Output Lines
V
D D
P u ll- u p
R e a d D a ta
D a ta b u s
S y s te m
P B 2 ~ P B 5
W a k e -u p
C o d e O p tio n
PB Input Lines
When the PA and PB0~PB1 is used for input operation,
it should be noted that before reading data from pads, a
²1² should be written to the related bits to disable the
NMOS device. That is, the instruction ²SET [m].i² (i=0~7
for PA, i=0~1 for PB) is executed first to disable related
NMOS device, and then ²MOV A, [m]² to get stable data.
Low Voltage Reset - LVR
After chip reset, PA and PB remain at a high level input
line while PC remain at high level output, if the level option is selected.
The LVR includes the following specifications:
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
Each bit of PA, PB0~PB1 and PC output latches can be
set or cleared by the ²SET [m].i² and ²CLR [m].i²
(m=12H, 14H or 16H) instructions respectively.
· The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m]²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
The relationship between VDD and VLVR is shown below.
V D D
3 .6 V
Each line of PB has a wake-up capability to the device
by code option. The highest seven bits of PC are not
physically implemented, on reading them a ²0² is returned and writing results in a no-operation.
V
Note: The bit 6 and Bit 7 the PB register (14H) are unused in the HT48RA0-2/HT48CA0-2, any read from that
will return the value ²0². User Should be very careful in
transferring the program from the HT48RA0A or
HT48RA0-1/HT48CA0-1 device to the HT48RA0-2/
HT48CA0-2 device.
Rev. 2.20
L V R
1 .9 V
0 .9 V
10
September 5, 2008
HT48RA0-2/HT48CA0-2
V
D D
3 .6 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
²*2² Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Code Option
The following table shows eight kinds of code option in the HT48RA0-2/HT48CA0-2. All the code options must be defined to ensure proper system functioning.
No.
Code Option
1
WDT time-out period selection
2n
Time-out period=
, where n=8~11.
Clock Source
2
WDT enable/disable selection. This option is to decide whether the WDT timer is enabled or disabled.
3
CLR WDT times selection. This option defines how to clear the WDT by instruction. ²One time² means that the
CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, the WDT can be cleared.
4
Wake-up selection. This option defines the wake-up activity function. External input pins (PB only) all have the
capability to wake-up the chip from a HALT.
5
Carrier/level output selection. This option defines the activity of PC0 to be carrier output or level output.
6
Carry frequency selection.
Clock Source
Carry frequency=
, where n=0~3.
(2 or 3) ´ 2n
Carrier duty selection. There are two types of selection: 1/2 duty or 1/3 duty.
7
If carrier frequency=Clock Source/(2, 4, 8 or 16), the duty cycle will be 1/2 duty.
If carrier frequency=Clock Source/3, the duty cycle will be 1/3 duty.
If carrier frequency=Clock Source/(6, 12 or 24), the duty cycle can be 1/2 duty or 1/3 duty.
8
System oscillator selection. RC or crystal oscillator.
9
LVR function: enable or disable
Rev. 2.20
11
September 5, 2008
HT48RA0-2/HT48CA0-2
Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
0 .1 m F
P A 0 ~ P A 7
V
D D
P B 0 ~ P B 1
4 7 0 p F
O S C 1
P B 2 ~ P B 5
R
O S C
P C 0 /R E M
C 1
V S S
fS
Y S
/4
O S C 2
O S C 1
R 1
O S C
C ir c u it
O S C 1
C 2
O S C 2
H T 4 8 R A 0 -2 /H T 4 8 C A 0 -2
Note:
R C S y s te m O s c illa to r
5 1 k W < R O S C < 1 M W
O S C 2
O S C
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
C ir c u it
1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 2.20
12
September 5, 2008
HT48RA0-2/HT48CA0-2
Example
P B 1
P B 2
P B 0
P B 3
P A 3
P B 4
P A 2
P B 5
P A 1
P A 7
P A 0
V
P A 6
D D
P A 5
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
P A 4
R E S
0 .1 m F
V S S
3 3 W
1 W
V D D
1 0 0 m F
V b a t
2 2 0 W ~ 1 k W
O S C
C ir c u it
P C 0 /R E M
O S C 1
O S C 2
H T 4 8 R A 0 -2 /H T 4 8 C A 0 -2
Rev. 2.20
13
September 5, 2008
HT48RA0-2/HT48CA0-2
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 2.20
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September 5, 2008
HT48RA0-2/HT48CA0-2
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 2.20
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
15
September 5, 2008
HT48RA0-2/HT48CA0-2
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 2.20
16
September 5, 2008
HT48RA0-2/HT48CA0-2
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 2.20
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September 5, 2008
HT48RA0-2/HT48CA0-2
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 2.20
18
September 5, 2008
HT48RA0-2/HT48CA0-2
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 2.20
19
September 5, 2008
HT48RA0-2/HT48CA0-2
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 2.20
20
September 5, 2008
HT48RA0-2/HT48CA0-2
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 2.20
21
September 5, 2008
HT48RA0-2/HT48CA0-2
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 2.20
22
September 5, 2008
HT48RA0-2/HT48CA0-2
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 2.20
23
September 5, 2008
HT48RA0-2/HT48CA0-2
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 2.20
24
September 5, 2008
HT48RA0-2/HT48CA0-2
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 2.20
25
September 5, 2008
HT48RA0-2/HT48CA0-2
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 2.20
26
September 5, 2008
HT48RA0-2/HT48CA0-2
Package Information
20-pin SSOP (150mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 2.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
150
¾
158
C
8
¾
12
C¢
335
¾
347
D
49
¾
65
E
¾
25
¾
F
4
¾
10
G
15
¾
50
H
7
¾
10
a
0°
¾
8°
27
September 5, 2008
HT48RA0-2/HT48CA0-2
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 20S (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
16.8+0.3
-0.2
T2
Reel Thickness
22.2±0.2
Rev. 2.20
28
September 5, 2008
HT48RA0-2/HT48CA0-2
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 20S (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0+0.3
-0.1
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.0±0.1
K0
Cavity Depth
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 2.20
2.3±0.1
0.30±0.05
13.3
29
September 5, 2008
HT48RA0-2/HT48CA0-2
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 2.20
30
September 5, 2008
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